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ARM: DRA72x: Add support for detection of SR2.0
Add support for detection of SR2.0 version of DRA72x family of processors. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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5 changed files with 9 additions and 0 deletions
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@ -775,6 +775,7 @@ void __weak hw_data_init(void)
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break;
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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*prcm = &dra7xx_prcm;
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*dplls_data = &dra72x_dplls;
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*omap_vcores = &dra722_volts;
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@ -807,6 +808,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
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*regs = &ioregs_dra7xx_es1;
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break;
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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*regs = &ioregs_dra72x_es1;
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break;
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@ -373,6 +373,9 @@ void init_omap_revision(void)
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case DRA722_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = DRA722_ES1_0;
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break;
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case DRA722_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = DRA722_ES2_0;
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break;
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default:
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*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
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}
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@ -438,6 +438,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
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}
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break;
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
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*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
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break;
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@ -670,6 +671,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
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case DRA752_ES1_1:
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case DRA752_ES2_0:
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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bug_00339_regs_ptr = dra_bug_00339_regs;
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*iterations = sizeof(dra_bug_00339_regs)/
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sizeof(dra_bug_00339_regs[0]);
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@ -60,6 +60,7 @@
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#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
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#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
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#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
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#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
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/* UART */
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#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
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@ -700,6 +700,7 @@ static inline u8 is_dra72x(void)
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#define DRA752_ES1_1 0x07520110
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#define DRA752_ES2_0 0x07520200
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#define DRA722_ES1_0 0x07220100
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#define DRA722_ES2_0 0x07220200
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/*
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* SRAM scratch space entries
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