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https://github.com/AsahiLinux/u-boot
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0d6faf2bd0
Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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arm11 | ||
arm720t | ||
arm920t | ||
arm926ejs | ||
arm946es | ||
arm1136 | ||
arm1176 | ||
armv7 | ||
armv7m | ||
armv8 | ||
pxa | ||
sa1100 | ||
Makefile | ||
u-boot-spl.lds | ||
u-boot.lds |