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ARM: DRA7: Add support for manual mode configuration
In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
eda6fbcc8c
commit
71bed1855f
4 changed files with 140 additions and 2 deletions
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@ -13,6 +13,7 @@
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mux_dra7xx.h>
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#include <asm/omap_common.h>
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static int isolate_io(u32 isolate)
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@ -80,7 +81,94 @@ static int update_delay_mechanism(u32 base)
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return 0;
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}
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void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads)
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static u32 calculate_delay(u32 base, u16 offset, u16 den)
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{
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u16 refclk_period, dly_cnt, ref_cnt;
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u32 reg, q, r;
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refclk_period = readl(base + CFG_REG_2_OFFSET) &
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CFG_REG_REFCLK_PERIOD_MASK;
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reg = readl(base + offset);
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dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
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ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
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if (!dly_cnt || !den)
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return 0;
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/*
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* To avoid overflow and integer truncation, delay value
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* is calculated as quotient + remainder.
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*/
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q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
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r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
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(2 * dly_cnt * den);
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return q + r;
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}
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static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
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{
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u32 g_delay_coarse, g_delay_fine;
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u32 a_delay_coarse, a_delay_fine;
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u32 c_elements, f_elements;
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u32 total_delay, reg = 0;
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g_delay_coarse = g_delay / 920;
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g_delay_fine = ((g_delay % 920) * 10) / 60;
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a_delay_coarse = a_delay / cpde;
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a_delay_fine = ((a_delay % cpde) * 10) / fpde;
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c_elements = g_delay_coarse + a_delay_coarse;
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f_elements = (g_delay_fine + a_delay_fine) / 10;
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if (f_elements > 22) {
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total_delay = c_elements * cpde + f_elements * fpde;
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c_elements = total_delay / cpde;
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f_elements = (total_delay % cpde) / fpde;
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}
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reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
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reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
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reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
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reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
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return reg;
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}
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static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
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int niodelays)
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{
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struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
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u32 reg, cpde, fpde, i;
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if (!niodelays)
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return 0;
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cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
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88);
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if (!cpde)
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return ERR_CPDE;
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fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
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264);
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if (!fpde)
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return ERR_FPDE;
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for (i = 0; i < niodelays; i++, iodelay++) {
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reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
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fpde);
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writel(reg, base + iodelay->offset);
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}
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return 0;
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}
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void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays)
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{
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int ret = 0;
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@ -109,6 +197,11 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads)
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/* Configure Mux settings */
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do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
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/* Configure Manual IO timing modes */
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ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
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if (ret)
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goto err;
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ret = isolate_io(DEISOLATE_IO);
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err:
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@ -133,6 +226,12 @@ err:
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case ERR_DEISOLATE_IO:
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puts("IODELAY: De-isolation of Device IOs failed\n");
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break;
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case ERR_CPDE:
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puts("IODELAY: CPDE calculation failed\n");
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break;
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case ERR_FPDE:
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puts("IODELAY: FPDE calculation failed\n");
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break;
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default:
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debug("IODELAY: IO delay recalibration successfully completed\n");
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}
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@ -35,6 +35,14 @@
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#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
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#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
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/* CONFIG_REG_3/4 */
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#define CFG_REG_3_OFFSET 0x18
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#define CFG_REG_4_OFFSET 0x1C
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#define CFG_REG_DLY_CNT_SHIFT 16
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#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16)
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#define CFG_REG_REF_CNT_SHIFT 0
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#define CFG_REG_REF_CNT_MASK (0xFFFF << 0)
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/* CTRL_CORE_SMA_SW_0 */
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#define CTRL_ISOLATE_SHIFT 2
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#define CTRL_ISOLATE_MASK (1 << 2)
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@ -53,6 +61,23 @@
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#define ERR_DEISOLATE_IO 0x2
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#define ERR_ISOLATE_IO 0x4
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#define ERR_UPDATE_DELAY 0x8
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#define ERR_CPDE 0x3
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#define ERR_FPDE 0x5
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/* CFG_XXX */
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#define CFG_X_SIGNATURE_SHIFT 12
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#define CFG_X_SIGNATURE_MASK (0x3F << 12)
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#define CFG_X_LOCK_SHIFT 10
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#define CFG_X_LOCK_MASK (0x1 << 10)
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#define CFG_X_COARSE_DLY_SHIFT 5
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#define CFG_X_COARSE_DLY_MASK (0x1F << 5)
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#define CFG_X_FINE_DLY_SHIFT 0
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#define CFG_X_FINE_DLY_MASK (0x1F << 0)
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#define CFG_X_SIGNATURE 0x29
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#define CFG_X_LOCK 1
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void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
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struct iodelay_cfg_entry const *iodelay,
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int niodelays);
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void __recalibrate_iodelay(struct pad_conf_entry const *array, int npads);
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#endif
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@ -61,6 +61,8 @@
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#define MODE_SELECT (1 << 8)
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#define DELAYMODE_SHIFT 4
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#define MANUAL_MODE MODE_SELECT
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#define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
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#define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
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#define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
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@ -18,6 +18,18 @@
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Structure for Iodelay configuration registers.
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* Theoretical max for g_delay is 21560 ps.
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* Theoretical max for a_delay is 1/3rd of g_delay max.
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* So using u16 for both a/g_delay.
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*/
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struct iodelay_cfg_entry {
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u16 offset;
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u16 a_delay;
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u16 g_delay;
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};
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struct pad_conf_entry {
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u32 offset;
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u32 val;
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