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armv8: ls2080a: Remove debug server support

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Debug server feature has been dropped from roadmap.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-08-03 12:33:00 -07:00
parent b392a6d4b0
commit b63a950629
10 changed files with 1 additions and 323 deletions
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6
README
View file

@ -4947,12 +4947,6 @@ The Freescale Layerscape Debug Server Support supports the loading of
"Debug Server firmware" and triggering SP boot-rom.
This firmware often needs to be loaded during U-Boot booting.
- CONFIG_FSL_DEBUG_SERVER
Enable the Debug Server for Layerscape SoCs.
- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
Define minimum DDR size required for debug server image
- CONFIG_SYS_MC_RSV_MEM_ALIGN
Define alignment of reserved memory MC requires

5
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View file

@ -18,7 +18,6 @@
#include <asm/arch/mp.h>
#endif
#include <fm_eth.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@ -457,10 +456,6 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size)
#ifdef CONFIG_SYS_MEM_TOP_HIDE
#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
#endif
/* Carve the Debug Server private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_DEBUG_SERVER
ram_top -= debug_server_get_dram_block_size();
#endif
/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET

9
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View file

@ -33,15 +33,6 @@
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
/* SP (Cortex-A5) related */
#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL

5
board/freescale/ls2080a/ls2080a.c
View file

@ -12,7 +12,6 @@
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <asm/arch/soc.h>
@ -60,10 +59,6 @@ int dram_init(void)
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_DEBUG_SERVER
debug_server_init();
#endif
return 0;
}
#endif

4
board/freescale/ls2080aqds/ls2080aqds.c
View file

@ -12,7 +12,6 @@
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
@ -265,9 +264,6 @@ int dram_init(void)
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_DEBUG_SERVER
debug_server_init();
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif

4
board/freescale/ls2080ardb/ls2080ardb.c
View file

@ -13,7 +13,6 @@
#include <hwconfig.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
@ -229,9 +228,6 @@ int dram_init(void)
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_DEBUG_SERVER
debug_server_init();
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif

1
drivers/misc/Makefile
View file

@ -16,7 +16,6 @@ obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o
endif
obj-$(CONFIG_FSL_IIM) += fsl_iim.o
obj-$(CONFIG_GPIO_LED) += gpio_led.o

250
drivers/misc/fsl_debug_server.c
View file

@ -1,250 +0,0 @@
/*
* Copyright (C) 2014 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/system.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl_debug_server.h>
DECLARE_GLOBAL_DATA_PTR;
static int debug_server_ver_info_maj, debug_server_ver_info_min;
/**
* Copying Debug Server firmware to DDR
*/
static int debug_server_copy_image(const char *title, u64 image_addr,
u32 image_size, u64 debug_server_ram_addr)
{
debug("%s copied to address %p\n", title,
(void *)debug_server_ram_addr);
memcpy((void *)debug_server_ram_addr, (void *)image_addr, image_size);
return 0;
}
/**
* Debug Server FIT image parser checks if the image is in FIT
* format, verifies integrity of the image and calculates
* raw image address and size values.
*
* Returns 0 if success and -1 if any of the above mentioned
* task fail.
**/
int debug_server_parse_firmware_fit_image(const void **raw_image_addr,
size_t *raw_image_size)
{
int format;
void *fit_hdr;
int node_offset;
const void *data;
size_t size;
const char *uname = "firmware";
char *desc;
char *debug_server_ver_info;
char *debug_server_ver_info_major, *debug_server_ver_info_minor;
/* Check if the image is in NOR flash */
#ifdef CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
fit_hdr = (void *)CONFIG_SYS_DEBUG_SERVER_FW_ADDR;
#else
#error "CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR not defined"
#endif
/* Check if Image is in FIT format */
format = genimg_get_format(fit_hdr);
if (format != IMAGE_FORMAT_FIT) {
printf("Debug Server FW: Not a FIT image\n");
goto out_error;
}
if (!fit_check_format(fit_hdr)) {
printf("Debug Server FW: Bad FIT image format\n");
goto out_error;
}
node_offset = fit_image_get_node(fit_hdr, uname);
if (node_offset < 0) {
printf("Debug Server FW:Can not find %s subimage\n", uname);
goto out_error;
}
/* Verify Debug Server firmware image */
if (!fit_image_verify(fit_hdr, node_offset)) {
printf("Debug Server FW: Bad Debug Server firmware hash");
goto out_error;
}
if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) {
printf("Debug Server FW: Failed to get FW description");
goto out_error;
}
debug_server_ver_info = strstr(desc, "Version");
debug_server_ver_info_major = strtok(debug_server_ver_info, ".");
debug_server_ver_info_minor = strtok(NULL, ".");
debug_server_ver_info_maj =
simple_strtoul(debug_server_ver_info_major, NULL, 10);
debug_server_ver_info_min =
simple_strtoul(debug_server_ver_info_minor, NULL, 10);
/* Debug server version checking */
if ((debug_server_ver_info_maj < DEBUG_SERVER_VER_MAJOR) ||
(debug_server_ver_info_min < DEBUG_SERVER_VER_MINOR)) {
printf("Debug server FW mismatches the min version required\n");
printf("Expected:%d.%d, Got %d.%d\n",
DEBUG_SERVER_VER_MAJOR, DEBUG_SERVER_VER_MINOR,
debug_server_ver_info_maj,
debug_server_ver_info_min);
goto out_error;
}
/* Get address and size of raw image */
fit_image_get_data(fit_hdr, node_offset, &data, &size);
*raw_image_addr = data;
*raw_image_size = size;
return 0;
out_error:
return -1;
}
/**
* Return the actual size of the Debug Server private DRAM block.
*
* NOTE: For now this function always returns the minimum required size,
* However, in the future, the actual size may be obtained from an environment
* variable.
*/
unsigned long debug_server_get_dram_block_size(void)
{
return CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE;
}
int debug_server_init(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
int error, timeout = CONFIG_SYS_DEBUG_SERVER_TIMEOUT;
int debug_server_boot_status;
u64 debug_server_ram_addr, debug_server_ram_size;
const void *raw_image_addr;
size_t raw_image_size = 0;
debug("debug_server_init called\n");
/*
* The Debug Server private DRAM block was already carved at the end of
* DRAM by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
*/
debug_server_ram_size = debug_server_get_dram_block_size();
if (gd->bd->bi_dram[1].start)
debug_server_ram_addr =
gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
else
debug_server_ram_addr =
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
#ifdef CONFIG_FSL_MC_ENET
debug_server_ram_addr += mc_get_dram_block_size();
#endif
error = debug_server_parse_firmware_fit_image(&raw_image_addr,
&raw_image_size);
if (error != 0)
goto out;
debug("debug server (ram addr = 0x%llx, ram size = 0x%llx)\n",
debug_server_ram_addr, debug_server_ram_size);
/*
* Load the Debug Server FW at the beginning of the Debug Server
* private DRAM block:
*/
debug_server_copy_image("Debug Server Firmware",
(u64)raw_image_addr, raw_image_size,
debug_server_ram_addr);
/* flush dcache */
flush_dcache_range((unsigned long)debug_server_ram_addr,
(unsigned long)debug_server_ram_addr +
(unsigned long)debug_server_ram_size);
/*
* Tell SP that the Debug Server FW is about to be launched. Before that
* populate the following:
* 1. Write the size allocated to SP Memory region into Bits {31:16} of
* SCRATCHRW5.
* 2. Write the start address of the SP memory regions into
* SCRATCHRW5 (Bits {15:0}, contain most significant bits, Bits
* {47:32} of the SP Memory Region physical start address
* (SoC address)) and SCRATCHRW6 (Bits {31:0}).
* 3. To know the Debug Server FW boot status, set bit 0 of SCRATCHRW11
* to 1. The Debug Server sets this to 0 to indicate a
* successul boot.
* 4. Wakeup SP by writing 0x1F to VSG GIC reg VIGR2.
*/
/* 512 MB */
out_le32(&gur->scratchrw[5 - 1],
(u32)((u64)debug_server_ram_addr >> 32) | (0x000D << 16));
out_le32(&gur->scratchrw[6 - 1],
((u32)debug_server_ram_addr) & 0xFFFFFFFF);
out_le32(&gur->scratchrw[11 - 1], DEBUG_SERVER_INIT_STATUS);
/* Allow the changes to reflect in GUR block */
mb();
/*
* Program VGIC to raise an interrupt to SP
*/
out_le32(CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2, 0x1F);
/* Allow the changes to reflect in VIGR2 */
mb();
dmb();
debug("Polling for Debug server to launch ...\n");
while (1) {
debug_server_boot_status = in_le32(&gur->scratchrw[11 - 1]);
if (!(debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK))
break;
udelay(1); /* throttle polling */
if (timeout-- <= 0)
break;
}
if (timeout <= 0) {
printf("Debug Server FW timed out (boot status: 0x%x)\n",
debug_server_boot_status);
error = -ETIMEDOUT;
goto out;
}
if (debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK) {
printf("Debug server FW error'ed out (boot status: 0x%x)\n",
debug_server_boot_status);
error = -ENODEV;
goto out;
}
printf("Debug server booted\n");
printf("Detected firmware %d.%d, (boot status: 0x0%x)\n",
debug_server_ver_info_maj, debug_server_ver_info_min,
debug_server_boot_status);
out:
if (error != 0)
debug_server_boot_status = -error;
else
debug_server_boot_status = 0;
return debug_server_boot_status;
}

8
include/configs/ls2080a_common.h
View file

@ -153,11 +153,6 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_NAND_BASE 0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
/* Debug Server firmware */
#define CONFIG_FSL_DEBUG_SERVER
/* 2 sec timeout */
#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
/* MC firmware */
#define CONFIG_FSL_MC_ENET
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
@ -175,8 +170,7 @@ unsigned long long get_qixis_addr(void);
* It will be used by MC and Debug Server. The MC region must be
* 512MB aligned, so the min size to hide is 512MB.
*/
#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024)
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024)
#endif

32
include/fsl_debug_server.h
View file

@ -1,32 +0,0 @@
/*
* Copyright (C) 2014 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FSL_DBG_SERVER_H__
#define __FSL_DBG_SERVER_H__
#include <asm/io.h>
#include <common.h>
/*
* Define Debug Server firmware version information
*/
/* Major version number: incremented on API compatibility changes */
#define DEBUG_SERVER_VER_MAJOR 0
/* Minor version number: incremented on API additions (backward
* compatible); reset when major version is incremented.
*/
#define DEBUG_SERVER_VER_MINOR 1
#define DEBUG_SERVER_INIT_STATUS (1 << 0)
#define DEBUG_SERVER_INIT_STATUS_MASK (0x00000001)
int debug_server_init(void);
unsigned long debug_server_get_dram_block_size(void);
#endif /* __FSL_DBG_SERVER_H__ */