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lpc32xx: cpu: add support for soft reset
Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset). To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
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parent
d75b532a9e
commit
576007aec9
1 changed files with 17 additions and 6 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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* Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -20,12 +20,23 @@ void reset_cpu(ulong addr)
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/* Enable watchdog clock */
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setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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/* Reset pulse length is 13005 peripheral clock frames */
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writel(13000, &wdt->pulse);
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/* To be compatible with the original U-Boot code:
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* addr: - 0: perform hard reset.
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* - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
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if (addr == 0) {
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/* Reset pulse length is 13005 peripheral clock frames */
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writel(13000, &wdt->pulse);
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/* Force WDOG_RESET2 and RESOUT_N signal active */
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writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
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&wdt->mctrl);
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/* Force WDOG_RESET2 and RESOUT_N signal active */
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writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
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| WDTIM_MCTRL_M_RES2, &wdt->mctrl);
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} else {
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/* Force match output active */
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writel(0x01, &wdt->emr);
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/* Internal reset on match output (no pulse on "RESOUT_N") */
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writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
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}
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while (1)
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/* NOP */;
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