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armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

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According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Mingkai Hu 2016-09-07 17:56:08 +08:00 committed by York Sun
parent 9578c4273d
commit 13f7988067
1 changed files with 15 additions and 0 deletions
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15
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
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@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
#endif
#ifdef CONFIG_LS1046A
/* Initialize the L2 RAM latency */
mrs x1, S3_1_c11_c0_2
mov x0, #0x1C7
/* Clear L2 Tag RAM latency and L2 Data RAM latency */
bic x1, x1, x0
/* Set L2 data ram latency bits [2:0] */
orr x1, x1, #0x2
/* set L2 tag ram latency bits [8:6] */
orr x1, x1, #0x80
msr S3_1_c11_c0_2, x1
isb
#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)