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17648 commits

Author SHA1 Message Date
Tom Warren
b1747fdb82 qspi: t210: Use dev_read calls to get FDT data like base, freq
This Tegra QSPI driver hadn't been brought up to date with how
DM drivers are fetching data from the FDT now, and was pulling
in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
to work the same way it does in the tegra114 SPI driver, using
dev_read_ functions.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02 14:30:02 -07:00
Tom Warren
2fcc3ba1b7 qspi: t210: Fix QSPI clock and tap delays
When claim_bus was setting the clock, it reset the QSPI controller,
which wipes out any tap delays set by previous bootloaders (nvtboot,
CBoot for example on Nano). Instead of doing that in claim_bus, which
gets called a lot, moved clock setting to probe(), and set tap delays
there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
save works reliably again.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02 14:30:02 -07:00
Tom Warren
3c8cf24032 qspi: t210: Fix claim_bus's use of the wrong bus/device
claim_bus() is passed a udevice *dev, which is the bus device's parent.
In this driver, claim_bus assumed it was the bus, which caused the
'priv' info pointer to be wrong, and periph_id was incorrect. This in
turn caused the periph clock call to assign the wrong clock (PLLM
instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
working w/this errant clock, but it was moot as QSPI wasn't active
unless you probed it, and that wasn't happening until I posted a patch
to enable env save to QSPI for Nano (coming soon).

Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02 14:30:02 -07:00
Tom Warren
a482f32992 mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-02 14:30:01 -07:00
Tom Warren
5e965e8140 mmc: t210: Add autocal and tap/trim updates for SDMMC1/3
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-04-02 14:30:01 -07:00
Jagan Teki
05c65a82c3 video: rockchip: Support 4K resolution for rk3399, HDMI
The default resolution for rockchip display is 1920x1080
which failed to work on 4K HDMI out displays on rk3399.

So, mark the default resolution as 3480x2160 for rk3399
HDMI out.

This would work all the hdmi display resolutions till
4K.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02 15:52:01 +02:00
Jagan Teki
e67243f1a3 video: rockchip: Fix vop modes for rk3399
VOP display endpoint pipeline configuration differs
between rk3288 vs rk3399.

These VOP pipeline configuration depends on how the
different display interfaces connected in sequence to
IN and OUT ports like for,

RK3288:

vopb_out: port {
	#address-cells = <1>;
	#size-cells = <0>;
	vopb_out_edp: endpoint@0 {
		reg = <0>;
		remote-endpoint = <&edp_in_vopb>;
	};
	vopb_out_hdmi: endpoint@1 {
		reg = <1>;
                remote-endpoint = <&hdmi_in_vopb>;
        };
        vopb_out_lvds: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&lvds_in_vopb>;
        };
        vopb_out_mipi: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi_in_vopb>;
        };
};

RK3399:

vopb_out: port {
         #address-cells = <1>;
         #size-cells = <0>;
         vopb_out_edp: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&edp_in_vopb>;
         };
         vopb_out_mipi: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&mipi_in_vopb>;
         };
         vopb_out_hdmi: endpoint@2 {
                reg = <2>;
                remote-endpoint = <&hdmi_in_vopb>;
         };
         vopb_out_mipi1: endpoint@3 {
                reg = <3>;
                remote-endpoint = <&mipi1_in_vopb>;
         };
         vopb_out_dp: endpoint@4 {
                reg = <4>;
                remote-endpoint = <&dp_in_vopb>;
         };
};

here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399.

The rockchip vop driver often depends on this determined endpoint
number and stored in vop_mode. So based on this vop_mode the bpp
and pin polarity would configure on detected display interface.

Since, the existing driver using rk3288 vop mode settings enabling
the same will result wrong display interface configuration for rk3399.

Add the patch for fixing these vop modes for rk3399.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02 15:47:35 +02:00
Jagan Teki
b1bcd61665 clk: rk3399: Set empty for vopl assigned-clocks
During vidconsole probe, the device probe will try to
check whether the assigned clocks on that video console
node is initialized or not? and return an error if not.

But, unlike Linux U-Boot won't require to handle these
vopl assigned-clocks since core clocks are enough to
handle the video out to process.

So, mark them as empty in set_rate to satisfy clk_set_defaults
so-that probe happened properly.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02 15:44:56 +02:00
Tudor Ambarus
52e2565bfb spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses
This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.

Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
[jagan: use 16 bit array with tmp variable]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-02 17:17:09 +05:30
Tudor Ambarus
ba03a6c944 spi: atmel-quadspi: fix possible MMIO window size overrun
The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.

There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).

Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.

Fixes: 24c8ff4684 ("spi: Add Atmel QuadSPI driver")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-02 17:15:55 +05:30
Tom Rini
2b18b89156 Merge branch 'next' of git://git.denx.de/u-boot-usb into next 2020-03-31 17:24:19 -04:00
Tom Rini
150db4264d Merge branch '2020-03-31-master-imports'
- mpc8xxx GPIO, SPI bugfixes
- Add VxWorks to FIT images
- macb ethernet driver bugfix
2020-03-31 10:07:01 -04:00
Michal Simek
7f6b0f3357 net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.
When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
 did you mean ‘MACB_MCF’?
  writel((value), (port)->regs + MACB_##reg)
                                 ^~~~~

It has been caused by changing macros name by commit below.

Fixes: 6c636514d4 ("net: macb: sync header definitions as taken from Linux")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-31 10:06:53 -04:00
Rasmus Villemoes
4856cc7a97 mpc8xxx_spi: implement real ->set_speed
Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.

Based on work by Klaus H. Sørensen.

Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:53 -04:00
Rasmus Villemoes
391c40048b mpc8xxx_spi: always use 8-bit characters, don't read or write garbage
There are a few problems with the current driver.

First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:

=> md.l 0x0 8
00000000: 45454545 45454545 05050505 05050505    EEEEEEEE........
00000010: 00000000 00000000 07070707 07070707    ................
=> sf probe 0
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48
SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> md.l 0x0 8
00000000: ff000000 45454545 05050505 05050505    ....EEEE........
00000010: 00000000 00000000 07070707 07070707    ................

(here I've change the first debug statement to a printf, and made it
print the din/dout pointers rather than the uints they point at).

Second, as we can also see above, it always writes a full 32 bits,
even if a smaller amount was requested. So for example

=> mw.l $loadaddr 0xaabbccdd 8
=> md.l $loadaddr 8
02000000: aabbccdd aabbccdd aabbccdd aabbccdd    ................
02000010: aabbccdd aabbccdd aabbccdd aabbccdd    ................
=> sf read $loadaddr 0x400 6
device 0 offset 0x400, size 0x6
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48
SF: 6 bytes @ 0x400 Read: OK
=> sf read 0x02000010 0x400 8
device 0 offset 0x400, size 0x8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64
SF: 8 bytes @ 0x400 Read: OK
=> md.l $loadaddr 8
02000000: 45454545 45450000 aabbccdd aabbccdd    EEEEEE..........
02000010: 45454545 45454545 aabbccdd aabbccdd    EEEEEEEE........

Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:

=> mw.l $loadaddr 0xaabbccdd 4
=> md.l $loadaddr 4
02000000: aabbccdd aabbccdd aabbccdd aabbccdd    ................
=> sf read $loadaddr 0x444 10
device 0 offset 0x444, size 0x10
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128
SF: 16 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 3031392e 30342d30    U-Boot 2019.04-0
=> mw.l $loadaddr 0xaabbccdd 4
=> sf read $loadaddr 0x444 0xb
device 0 offset 0x444, size 0xb
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88
SF: 11 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 31392e00 aabbccdd    U-Boot 219......

Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.

Based on work by Klaus H. Sørensen.

Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:53 -04:00
Rasmus Villemoes
1a7b462dee mpc8xxx_spi: put max_cs to use
Currently, max_cs is write-only; it's just set in
mpc8xxx_spi_ofdata_to_platdata and not otherwise used.

My mpc8309 was always resetting during an "sf probe 0". It turns out
dm_gpio_set_dir_flags() was being called with garbage, since nothing
had initialized priv->gpios[0] - our device tree used "cs-gpios"
rather than "gpios", so gpio_request_list_by_name() had returned 0.

That would have been a lot easier to figure out if the chip select
index was sanity checked, so rename max_cs to cs_count, and reject a
xfer with a too large cs index.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Klaus H. Sorensen
3fb22bc2f8 gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.

This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.

Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.

It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)

Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Rasmus Villemoes
dd4cf53f98 gpio: mpc8xxx: don't do RMW on gpdat register when setting value
The driver correctly handles reading back the value of an output gpio
by reading from the shadow register for output, and from gpdat for
inputs.

Unfortunately, when setting the value of some gpio, we do a RMW cycle
on the gpdat register without taking the shadow register into account,
thus accidentally setting other output gpios (at least those whose
value cannot be read back) to 0 at the same time.

When changing a gpio from input to output, we still need to make sure
it initially has the requested value. So, the procedure is

- update the shadow register
- compute the new gpdir register
- write the bitwise and of the shadow and new gpdir register to gpdat
- write the new gpdir register

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Rasmus Villemoes
1d7ad9fa05 gpio: mpc8xxx: don't modify gpdat when setting gpio as input
Since some chips don't support reading back the value of output gpios
from the gpdat register, we should not do a RMW cycle (i.e., the
clrbits_be32) on the gpdat register when setting a gpio as input, as
that might accidentally change the value of some other (still
configured as output) gpio.

The extra indirection through mpc8xxx_gpio_set_in() does not help
readability, so just fold the gpdir update into
mpc8xxx_gpio_direction_input().

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Tom Rini
962bb2e31b Merge branch 'master' of git://git.denx.de/u-boot-sh
- Fixes for Gen 2 V2H Blanche
2020-03-31 10:04:39 -04:00
Tom Rini
8e4af8f6d8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Fixes env variable for layerscape platforms, disable hs200.
- Fixes board fixup, mux setting, enable gic, fspi on lx2160a, Fixes I2C
  DM Warning on ls1043a, ls1046a
- Fixes RGMII port on ls1046ardb, ls1046ardb and DM_USB Warning on
  ls1012afrdm, ls1021aiot
2020-03-30 14:14:07 -04:00
Biwen Li
bb1165f900 dm: arm64: ls1046a: add i2c DM support
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:12:13 +05:30
Vladimir Oltean
f83567e0c0 pci-host-ecam-generic: access config space independent of system-wide bus id
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.

Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.

Fixes: 3675cb044e ("PCI: Add driver for a 'pci-host-ecam-generic' host controller")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:11:56 +05:30
Madalin Bucur
4fb2264b28 armv8/ls1046ardb: RGMII ports require internal delay
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.

Fixes: cc1aa218f5 ("armv8/ls1046a: RGMII PHY requires internal
	delay on Tx")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:06:52 +05:30
Madalin Bucur
00160cf32e armv8/ls1043ardb: RGMII ports require internal delay
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.

Fixes: 5a78a472f6 ("armv8/ls1043a: RGMII PHY requires internal
	delay on Tx")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:06:52 +05:30
Madalin Bucur
e219d7d0f1 net: fman: add support for all RGMII delay modes
The RGMII modes that include internal delay were not all
properly treated in the memac code. Add support for all
RGMII delay modes.

Fixes: 111fd19e3b ("fm/mEMAC: add mEMAC frame work")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30 08:06:52 +05:30
Marek Vasut
061ef41fcf clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2
The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30 03:49:23 +02:00
Kever Yang
ac28e59a57 usb: Migrate to support live DT for some driver
Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT.
This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use
ofnode as parameter instead of fdt offset. And all the drivers who use
these APIs update to use live dt APIs at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-30 03:48:53 +02:00
Kever Yang
2be1130a93 usb: ehci-msm: Use dev interface to get device address
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2020-03-30 03:48:53 +02:00
Kever Yang
eea4810804 usb: dwc3-of-simple: Drop redundant inclding header file
The fdtdec.h is no use in this file, remove the include code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-30 03:48:53 +02:00
Nicolas Heemeryck
5b5699cdc9 timer: sti: use clk API to get timer clock rate
Retrieve clock rate through device tree. This mimics the behavior of
arm_global_timer in Linux.

Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:23:35 +01:00
Nicolas Heemeryck
123123d695 timer: sti: convert to livetree
Update STI timer to support a live tree

Signed-off-by: Nicolas Heemeryck <nicolas.heemeryck@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:23:33 +01:00
Alain Volmat
c324465576 i2c: stm32f7_i2c: allows for any bus frequency
Do not limit to 3 (100KHz, 400KHz, 1MHz) bus frequencies, but
instead allow for any frequency. Depending on the requested
frequency (via the clock-frequency DT entry), use the spec
data from either Standard, Fast or Fast Plus mode.

In order to do so, the driver do not use anymore spec identifier
by directly handle the requested frequency and from it retrieve
the corresponding spec data to be used for the computation
of the timing register.

Signed-off-by: Alain Volmat <alain.volmat@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:23:32 +01:00
Patrick Delaunay
9368bdfebd ram: stm32mp1: the property st, phy-cal becomes optional
This parameter "st,phy-cal" becomes optional and when it is
absent the built-in PHY calibration is done.

It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
except if DDR_PHY_CAL_SKIP is defined.

This patch also impact the ddr interactive mode
- the registers of the param 'phy.cal' are initialized to 0 when
  "st,phy-cal" is not present in device tree (default behavior when
  DDR_PHY_CAL_SKIP is not activated)
- the info 'cal' field can be use to change the calibration behavior
  - cal=1 => use param phy.cal to initialize the PHY, built-in training
             is skipped
  - cal=0 => param phy.cal is absent, built-in training is used (default)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:23:30 +01:00
Patrick Delaunay
d424e6786f ram: stm32mp1: reduce delay after BIST reset for tuning
Reduce the delay after BIST delay, from 1ms to 10us
which is enough accoriding datasheet.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:23:26 +01:00
Patrick Delaunay
b604a41c6b ram: stm32mp1_ddr: fix self refresh disable during DQS training
DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not
to enter in self refresh mode during the execution of this phase.
Depending on settings, it can be set after the DQS training.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:23:18 +01:00
Patrick Delaunay
8c9ce08075 ram: stm32mp1: update BIST config for tuning
Update the BIST config to compute the real use mask for the real
bank, row and col of the used DDR. The values are get from addrmap
register value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:20:50 +01:00
Patrick Delaunay
27e7b4edea ram: stm32mp1: tuning: deactivate derating during BIST test
The derating (timing parameter derating using MR4 read value)
can't be activated during BIST test, as the MR4 read answer will
be not understood by BIST (BISTGSR.BDONE bit stay at 0,
BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200).

This patch only impacts the tuning on LPDDR2/LPDDR3,
if derateen.derate_enable = 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:20:50 +01:00
Patrick Delaunay
f711d1f080 ram: stm32mp1: tuning: add timeout for polling BISTGSR.BDDONE
Avoid to block the tuning procedure on BIST error (not finished
BIST procedure) by adding a 1000us timeout on the polling of
BISTGSR.BDDONE executed to detect the end of BIST.

The normal duration of the BIST test is around 5us.

This patch also cleanup comments.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:20:50 +01:00
Patrick Delaunay
1c55a91b9d ram: stm32mp1: don't display the prompt two times
Remove one "DDR>" display on command
- next
- step
- go

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:20:50 +01:00
Patrick Delaunay
c8eb4e038c ram: stm32mp1: display result for software read DQS gating
Display result information for software read DQS gating, the tuning 0
which be used by CubeMX DDR tuning tools.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:20:50 +01:00
Patrick Delaunay
e9a20f8a19 ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDR
Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2
form 1.2V to 1.25V for 32bits configuration.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:20:50 +01:00
Patrick Delaunay
0c90e0cf63 clk: stm32mp1: add SPI5_K support
Add clock support for SPI5, as this instance is available on extension
connector of ST board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:18:09 +01:00
Patrick Delaunay
69ffb5577a clk: stm32mp1: correct CKSELR masks
Correct three masks used to access on the RCC register
RCC_QSPICKSELR, RCC_FMCCKSELR and RCC_ADCCKSELR: only 3 bits.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24 14:18:09 +01:00
Andre Przywara
48313fe510 sunxi: Move common defconfig options to Kconfig
Some config symbols are found in *almost* every _defconfig file for
Allwinner boards, because those options are actually a platform choice,
and not a per-board decision.
Some of these options are older, some have recently been added.

Move those options to be set for all Allwinner boards in their
respective Kconfig files.

The rationales are as follows:
- NR_DRAM_BANKS: All Allwinner SoC map DRAM at one contiguous region of
  address space only, starting at 1 GB. So it's always one bank.
- SPL_{DOS,EFI}_PARTITION: The Allwinner SPL does only support raw MMC
  accesses, we don't care about filesystems or partitions in there, so
  there is no need to define those symbols at all.
- USE_PREBOOT: We start USB early when a keyboard is configured, using the
  preboot env variable, so we need to set this variable.
- SYS_RELOC_GD_ENV_ADDR: We don't specify any ENV_ADDR, so need this
  symbol to be set (according to 8d8ee47e03).
- SYS_USB_EVENT_POLL_VIA_INT_QUEUE: According to commit eab9433aa5,
  specifying this reduces the latency of the USB keyboard handling, so
  this was formerly enabled in config headers for all Allwinner boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-03-18 18:25:00 +05:30
Tom Rini
2738f0edea Merge tag 'ti-v2020.07-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
K3 J721E:
* OSPI boot support
* Support for loading remote cores in R5 SPL
* PMIC ESM Support
* Minor fixes for R5F and C7x remoteproc drivers

K3 AM654:
* Update AVS class 0 voltages.
* Add I2C nodes

DRA7xx/AM57xx:
* Fixed Android boot on AM57xx

AM33/AM43/Davinci:
* switch to driver model for the net and mdio driver for baltos
* Add DM/DTS support for omap video driver
* Enable fastboot on am335x-evm
2020-03-17 11:59:58 -04:00
Chris Packham
6d8eae9ab7 watchdog: Handle timer wrap around
On some platforms/architectures the value from get_timer() can wrap.
This is particularly problematic when long-running code needs to measure
a time difference as is the case with watchdog_reset() which tries to
avoid tickling the watchdog too frequently.

Use time_after() from time.h instead of a plain > comparison to avoid
any issues with the time wrapping on a system that has been sitting in
u-boot for a long time.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-03-16 11:25:12 +01:00
Heiko Schocher
80e8b8add0 bootcounter: add DM support for memory based bootcounter
add DM/DTS support for the memory based bootcounter
in drivers/bootcount/bootcount.c.

Let the old implementation in, so boards which have
not yet convert to DM/DTS do not break.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-16 08:05:00 +01:00
Jun Chen
27d483bfa3 i2c: designware_i2c: add 'hs_hcnt' and 'hs_lcnt' for high speed
Add support for high speed if scl_sda_cfg exist.

Signed-off-by: Jun Chen <ptchentw@gmail.com>
Signed-off-by: Jun Chen <jun.chen@vatics.com>
2020-03-16 08:04:29 +01:00
Jun Chen
be26342314 i2c: designware_i2c: remove 'has_high_speed'
Remove 'has_high_speed' config since we can check high speed support
from IC_COMP_PARAM_1 register.

Signed-off-by: Jun Chen <ptchentw@gmail.com>
Signed-off-by: Jun Chen <jun.chen@vatics.com>
2020-03-16 08:04:17 +01:00
Jun Chen
565e328b95 i2c: designware_i2c: check is high speed possible support
To read IC_COMP_PARAM_1[3:2] to check is high speed possible,
and fall back to fast mode if not.

Signed-off-by: Jun Chen <ptchentw@gmail.com>
Signed-off-by: Jun Chen <jun.chen@vatics.com>
2020-03-16 08:04:09 +01:00
Jun Chen
70c894f85e i2c: designware_i2c: Fix IC_CON register setting for high speed mode
IC_CON[2:1] should be 3 for high speed mode

Signed-off-by: Jun Chen <ptchentw@gmail.com>
Signed-off-by: Jun Chen <jun.chen@vatics.com>
2020-03-16 08:03:53 +01:00
Masahiro Yamada
0c17bb1cbe misc: i2c_eeprom: store pagesize instead of pagewidth in i2c_eeprom_drv_data
Associate the pagesize with compatible strings, and copy it to
priv->pagesize. This is more straight-forward.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-16 08:03:29 +01:00
Suman Anna
445b45042c remoteproc: k3-r5: Fix rproc init failure on Split-mode _only_ devices
The R5F subsystem/cluster on K3 SoCs can support both LockStep and
Split-modes (superset) or just Split-mode depending on an eFUSE
capability register. The LockStep configuration bit is Read-only
though on Split-mode _only_ devices and as such the System Firmware
does not allow the LockStep mode bit to be configured on such devices.
The current logic in k3_r5f_rproc_configure() fails on Split-mode
devices because of this unconditional programming of the LockStep
mode bit, and results in the probe failure shown during the
"rproc init" step at U-Boot prompt.

Fix this by limiting the LockStep mode bit clear configuration only on
devices supporting both LockStep/Split-modes.

Fixes: 4c850356a8 ("remoteproc: Introduce K3 remoteproc driver for R5F subsystem")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-16 12:33:19 +05:30
Masahiro Yamada
ed6dd4e460 misc: i2c_eeprom: remove pagewidth field from i2c_eeprom
This struct member is not used in any effective way. Remove it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-16 08:03:05 +01:00
Suman Anna
0438a0a181 remoteproc: k3-r5: Fix rproc init failure for Main R5FSS0
The Main R5FSS0 cluster is also enabled to probe the R5F remoteproc
driver within R5 SPL for booting the Core0 very early. This results
in a ti_sci_power_domain_on failure during the probe from the A72
U-Boot when "rproc init" is executed at U-Boot prompt, and doesn't
enumerate all the rproc devices.

Fix this by suppressing the power_domain_on altogether using the
flag DM_FLAG_DEFAULT_PD_CTRL_OFF added in commit af94ad418d
("dm: core: Allow for not controlling the power-domain by DM framework").

Fixes: fac6aa817a ("configs: j721e_evm_r5: Enable R5F remoteproc support")
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-16 12:33:03 +05:30
Suman Anna
42005817ee remoteproc: k3-dsp: Add support for L2RAM loading on C66x DSPs
The resets for the DSP processors on K3 SoCs are managed through the
Power and Sleep Controller (PSC) module. Each DSP typically has two
resets - a global module reset for powering on the device, and a local
reset that affects only the CPU while allowing access to the other
sub-modules within the DSP processor sub-systems.

The C66x DSPs have two levels of internal RAMs that can be used to
boot from, and the firmware loading into these RAMs require the
local reset to be asserted with the device powered on/enabled using
the module reset. Enhance the K3 DSP remoteproc driver to add support
for loading into the internal RAMs. The local reset is deasserted on
SoC power-on-reset, so logic has to be added in probe in remoteproc
mode to balance the remoteproc state-machine.

Note that the local resets are a no-op on C71x cores, and the hardware
does not supporting loading into its internal RAMs.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-16 12:32:47 +05:30
Suman Anna
1e53d5b585 remoteproc: k3-dsp: Add a sanity check for DSP boot address alignment
The DSP remote processors on K3 SoCs require a boot register to be
programmed with a boot address, and these boot addresses need to be
aligned on certain address boundaries. The current code does not have
any error checks, and relies on the System Firmware to perform the
checking. Add logic to perform this sanity check within the remoteproc
driver itself to detect these anomalies specifically, and print a
meaningful trace. This avoids the cumbersome debug of root-causing
such failures from the corresponding TI-SCI failure.

The C66x and C71x DSP cores have different alignment needs and are
as follows:
	C66x DSP = 1 KB (0x400)
	C71x DSP = 2 MB (0x200000)

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-16 12:32:47 +05:30
Suman Anna
0020003ef3 remoteproc: k3-dsp: Fix unbalanced state machine in k3_dsp_start
The global module reset is deasserted through the ti_sci_power_domain_on()
call in k3_dsp_start(), but is not asserted back if the local module reset
fails. Fix this.

While at this, remove the stale comment about assigned-clock-rates that
seems to have been copied from the K3 ARM64 Remoteproc driver.

Fixes: ab827b3857 ("remoteproc: Introduce K3 C66 and C71 remoteproc driver")
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-16 12:32:47 +05:30
Heiko Schocher
ba6fb2f6ac dm: i2c-gpio: add support for clock stretching
This adds support for clock stretching to the i2c-gpio driver. This is
accomplished by switching the GPIO used for the SCL line to an input
when it should be driven high, and polling on the SCL line value until
it goes high (indicating that the I2C slave is no longer pulling it
low).

This is enabled by default; for gpios which cannot be configured as
inputs, the i2c-gpio,scl-output-only property can be used to fall back
to the previous behavior.

Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-03-16 07:55:06 +01:00
Michael Auchter
7383edc2fb dm: i2c-gpio: rework gpio get/set functions
This patch reworks i2c-gpio to make it easier to switch out the
implementation of the sda/scl get/set functions. This is in preparation
for a patch to conditionally implement clock stretching support.

Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-03-16 07:48:15 +01:00
Marek Vasut
4368c6a2bc i2c: gpio: Run deblock sequence on probe
Add deblock dequence for the I2C bus, needed on some devices. This sequence
is issued once, when probing the driver, and is controlled by DT property,
"i2c-gpio,deblock".

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-03-16 07:46:31 +01:00
Marek Vasut
a191728633 i2c: Add option to send start condition after deblocking
Add option to send start condition after deblocking SDA.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-03-16 07:46:21 +01:00
Marek Vasut
7231522a5e i2c: Export i2c_deblock_gpio_loop()
Export the i2c_deblock_gpio_loop() so it can be used in other places in
U-Boot. In particular, this is useful in the GPIO I2C driver, which claims
the SDA/SCL GPIOs and thus prevents the i2c_deblock() implementation from
claiming the pins as GPIOs again.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-03-16 07:46:04 +01:00
Marek Vasut
1f746a2c82 i2c: Make deblock delay and SCL clock configurable
Make the delay between SCL line changes and the number of SCL clock
changes configurable as a parameter of the deblock function. No
functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-03-16 07:45:53 +01:00
Michal Simek
92a19be258 watchdog: Align Kconfig properties
Just cleanup help indentation to be the same for all options.
It means <tab><space><space> indentation.

OMAP3 should be indented by tabs which is also fixed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-03-13 09:30:30 -04:00
Angelo Durgehello
1886024a0e serial: mcfuart: renaming to a more appropriate name
All drivers seems to align now to serial_xxx maning, so, aligning
also this driver, to allow to be found easily.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-03-13 09:29:50 -04:00
Angelo Durgehello
ce5e3ea799 serial: mcfuart: fix uart port index
Actually, using dev->seq value before probe to deduce the current
serial port index leads to reading an invalid seq value (-1).
So, getting dev->seq at probe time.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-03-13 09:28:17 -04:00
Tom Rini
db3b1818b7 Pull request for UEFI sub-system for efi-2020-04-rc4 (3)
This pull request provides the hardware RNG driver for Amlogic systems needed
 for the EFI_RNG_PROTOCOL.
 
 Furthermore bug fixes are provided:
 
 * correct an error message in the efidebug command
 * correct an error in the 'efidebug rm' command
 * remove an unnecessary assignment in efi_queue_event()
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Merge tag 'efi-2020-04-rc4-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-04-rc4 (3)

This pull request provides the hardware RNG driver for Amlogic systems needed
for the EFI_RNG_PROTOCOL.

Furthermore bug fixes are provided:

* correct an error message in the efidebug command
* correct an error in the 'efidebug rm' command
* remove an unnecessary assignment in efi_queue_event()
2020-03-12 12:51:44 -04:00
Heinrich Schuchardt
bc40eb278b drivers/rng: add Amlogic hardware RNG driver
Add support for the hardware random number generator of Amlogic SOCs.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-03-11 08:29:58 +01:00
Heinrich Schuchardt
c312c4b4dc drivers/rng: simplify Kconfig
For all sandbox systems with DM_RNG we enable RNG_SANDBOX. So we can simply
set the default to yes.

All rng drivers depend on DM_RNG. Use a single 'if' instead of individual
dependencies. Now 'make menuconfig' shows the individual drivers neatly
indented under the DM_RNG entry.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-03-11 08:29:58 +01:00
Tom Rini
36bdcf7f3b Merge tag 'mmc-2020-3-9' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- DM support for CAxxxx SoCs
- eMMC board for presidio-asic
- Add defer probe for mmc sdhci
- TI SoCs mmc misc update
2020-03-10 21:13:26 -04:00
Anatolij Gustschin
3e4fcfa4bc power-domain: fix hang in endless loop on i.MX8
Currently when booting the kernel on i.MX8 U-Boot hangs in an
endless loop when switching off dma, connectivity or lsio power
domains during device removal. It hapens first when removing
gpio0 (gpio@5d080000) device, here its power domain device
'lsio_gpio0' is obtained for switching off power. Since the
obtained 'lsio_gpio0' device is removed afterwards, its power
domain is also switched off and here the parent power domain
device 'lsio_power_domain' is optained for switching off the
power. Thereafter, when the obtained 'lsio_power_domain' is
removed, device_remove() removes its first child 'lsio_gpio0'.
During this child removal the 'lsio_power_domain' device is
obtained again for switching and when removing it later,
the same child removal is repeated, so we are stuck in an
endless loop. Below is a snippet from dm tree on i.MX8QXP
for better illustration of the DM devices relationship:

 Class     Index  Probed  Driver                Name
-----------------------------------------------------------
 root          0  [ + ]   root_driver           root_driver
...
 simple_bus    0  [ + ]   generic_simple_bus    |-- imx8qx-pm
 power_doma    0  [ + ]   imx8_power_domain     |   |-- lsio_power_domain
 power_doma    1  [ + ]   imx8_power_domain     |   |   |-- lsio_gpio0
 power_doma    2  [ + ]   imx8_power_domain     |   |   |-- lsio_gpio1

Do not remove a power domain device if it is a parent of the
currently controlled device.

Fixes: 52edfed65d ("dm: core: device: switch off power domain after device removal")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Oliver Graute <oliver.graute@gmail.com>
Reported-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
2020-03-10 16:29:38 -04:00
Tom Rini
3a1cb95308 Fixes for 2020.04
-----------------
 
 - DM : mx6sabresd
 - mx6ul_14x14_evk: fix video
 - mx8qxp; fix console for booting
 - sync DTS with kernel (imx6sx)
 - drop obsolete woodburn (mx35)
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/660550811
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Merge tag 'u-boot-imx-20200310' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.04
-----------------

- DM : mx6sabresd
- mx6ul_14x14_evk: fix video
- mx8qxp; fix console for booting
- sync DTS with kernel (imx6sx)
- drop obsolete woodburn (mx35)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/660550811
2020-03-10 13:13:08 -04:00
Tom Rini
dd12b2f632 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net 2020-03-10 07:51:56 -04:00
Clemens Gruber
1c1f4f0a4b net: phy: marvell: Unify 88E151x series phy_driver
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).

Before commit 83cfbeb0df ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.

I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.

The uid and mask bits 3:0 are now again the same as in the Linux kernel.

Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2020-03-09 18:11:25 -05:00
Michal Simek
a7844953ac net: phy: dp83867: Add SGMII mode type switching
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.

Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09 18:11:25 -05:00
Andre Przywara
a44ee246c5 net: phy: Fix overlong PHY timeout
Commit 27c3f70f3b ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.

Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09 18:11:24 -05:00
Alex Marginean
2d5d5266e1 drivers: net: phy: aquantia: make it less verbose
The driver now unconditionally prints some information that's not
universally useful.  Replace printf with debug.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09 18:11:24 -05:00
Alex Marginean
0d8b0c917a drivers: net: phy: aquantia: drop XGMII as a valid system interface proto
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration.  The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09 18:11:24 -05:00
Samuel Mendoza-Jonas
e2ffeaa162 phy: Include NC-SI in phy setup
Add NC-SI to the usual phy handling. This makes two notable changes:
- Somewhat similar to a fixed phy, phy_connect() will create an NC-SI
phy if CONFIG_PHY_NCSI is defined.
- An early return is added to phy_read() and phy_write() to handle a
case like the NC-SI phy which does not define a bus.

Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09 18:11:23 -05:00
Samuel Mendoza-Jonas
f641a8ac93 phy: Add support for the NC-SI protocol
This introduces support for the NC-SI protocol, modelled as a phy driver
for other ethernet drivers to consume.

NC-SI (Network Controller Sideband Interface) is a protocol to manage a
sideband connection to a proper network interface, for example a BMC
(Baseboard Management Controller) sharing the NIC of the host system.
Probing and configuration occurs by communicating with the "remote" NIC
via NC-SI control frames (Ethernet header 0x88f8).

This implementation is roughly based on the upstream Linux
implementation[0], with a reduced feature set and an emphasis on getting
a link up as fast as possible rather than probing the full possible
topology of the bus.
The current phy model relies on the network being "up", sending NC-SI
command frames via net_send_packet() and receiving them from the
net_loop() loop (added in a following patch).

The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent
field definitions.

[0]: https://github.com/torvalds/linux/tree/master/net/ncsi
[1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h

Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-09 18:11:23 -05:00
Giulio Benetti
289dd9f072 serial_lpuart: make clock failure less verbose
Some device may enable CONFIG_CLK but not still support this clock in
CC, so better use debug() in place of dev_warn() otherwise a lot of
boards will throw useless dev_warn()s.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-09 15:06:23 +01:00
Faiz Abbas
a851213920 mmc: am654_sdhci: Implement workaround for card detect
The 4 bit MMC controllers have an internal debounce for the SDCD line
with a debounce delay of 1 second. Therefore, after clocks to the IP are
enabled, software has to wait for this time before it can power on the
controller.

Add a deferred_probe() callback which polls on sdcd for a maximum of 2 seconds
before switching on power to the controller or (in the case of no card)
returning a ENOMEDIUM. This pushes the 1 second wait time to when the
card is actually needed rather than at every probe() making sure that
users who don't insert an SD card in the slot don't have to wait such a
long time.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09 08:33:16 +08:00
Faiz Abbas
c7d106b4eb mmc: am654_sdhci: Update output tap delay writes
With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09 08:33:16 +08:00
Faiz Abbas
e8d5dde447 mmc: Merge SD_LEGACY and MMC_LEGACY bus modes
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09 08:33:16 +08:00
Faiz Abbas
cb884347f4 sdhci: Add sdhci_deferred_probe() API
Add the sdhci_deferred_probe() function to register as the
deferred_probe() callback to the mmc core. It will in turn call the
deferred_probe() callback of the platform drivers as declared in the
sdhci_ops.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09 08:33:16 +08:00
Faiz Abbas
32860bdbc1 mmc: Add a deferred_probe() API
Add a deferred_probe() API for platforms that want to do some
configurations just before starting to enumerate the device.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09 08:33:15 +08:00
Arthur Li
d55e4e74ce mmc: ca_dw_mmc: add DesignWare based DM support for CAxxxx SoCs
Initial DesignWare based DM support for Cortina Access CAxxxx SoCs.

Signed-off-by: Arthur Li <arthur.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-03-09 08:33:13 +08:00
Wolfgang Wallner
720f9e1fdb serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()
Currently the ofdata_to_platdata() method calls dev_read_addr_pci(),
which potentially accesses the parent PCI bus. If this happens before
the parent PCI bus is probed the resulting address will be wrong.

This behavior was triggered by commit 82de42fa14 ("dm: core:
Allocate parent data separate from probing parent").

According to a comment in drivers/pci/pci-uclass.c [1] accessing
the PCI parent bus in ofdata_to_platdata() is not allowed, and the
access should be moved to the probe() function.

Move the call to dev_read_addr_pci() and the related handling of the
'addr' value from the ofdata_to_platdata() to its own function,
which is then called from the probe() method.

While moving the code, the comment /* try Processor Local Bus device
first */ was dropped. It was initially added with commit 3db886a5bf
("serial: ns16550: Support ns16550 compatible pci uart devices") and
later made obsolete with commit 33c215af4b ("dm: pci: Add a function
to read a PCI BAR").

[1] Comment in drivers/pci/pci-uclass.c:
"A common cause of this problem is that this function is called in the
ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
method is not allowed, since it has not yet been probed. To fix this,
move that access to the probe() method of @dev instead."

Fixes: 82de42fa14 ("dm: core: Allocate parent data separate from probing parent")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # Tested on Intel Galileo
2020-03-05 18:25:10 +08:00
Heinrich Schuchardt
38a2a48cd9 x86: remove dead code in intel_clk_get_rate()
If all branches of a switch statement have a return instruction, all
subsequent lines are unreachable.

Identified with cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-05 18:19:40 +08:00
Tom Rini
c12ee850d6 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- ABB SECU board
- Assorted minor fixes
2020-03-04 10:41:41 -05:00
Tom Rini
3e106f11b2 Merge branch 'master' of git://git.denx.de/u-boot-usb
- DFU / Thor fixes
2020-03-04 10:41:27 -05:00
Lokesh Vutla
57b2712b2b dma: ti: k3-udma: Mark flow id as valid parameter for RX channel config
When flow id is not marked as valid, sysfw reads the register value to
get the range of flow ids that are supported. Then compares the flow range
with the U-Boot's host id. This will definitely fail as board
configuration doesn't assign the full range to U-Boot's host id. In order
to work around this, mark the flow id as valid and pass range as 0.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-03 13:08:14 +05:30
Lokesh Vutla
11e47de3c9 firmware: tisci: Drop all deprecated messages
SYSFW v2020.01 and later versions no longer supports the below messages:
- TI_SCI_MSG_RM_RING_GET_CFG
- TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG   0x1206
- TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG   0x1216
- TISCI_MSG_RM_UDMAP_FLOW_GET_CFG        0x1232
- TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG    0x1233

There are no users in U-Boot for any of the above messages, So drop the
support for all the corresponding messages.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-03 13:08:14 +05:30
Dario Binacchi
0aff8e2615 video: omap: fix pixel-per-line bitfield setting
Fix the macro to set the pplmsb field (bit 3) of the RASTER_TIMING_0
register. It is used in order to support up to 2048 pixels per line.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
96b109ba74 video: omap: add support for DM/DTS
Update the driver to support the device tree and the driver model.
Timings and panel parameters are now loaded from the device tree.

The DM code replaces the am335x_lcdpanel structure with
tilcdc_panel_info taken from the linux kernel, as well the management
of additional parameters not covered in the legacy code. In addition,
the am335x_lcdpanel structure contains parameters and operations that
were probably a requirement of the board for which this driver was
developed and which, however, were not developed in the linux kernel.
All this led to rewrite th DM controller initialization code, except
for the pixel clock setting that is executed in a function created in a
previous patch with code taken from the legacy am335xfb_init.

The patch has been tested on a custom board with u-boot 2018.11-rc2 and
the following device-tree configuration:

	panel {
		compatible = "ti,tilcdc,panel";
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_enable_pins>;
		enable-gpios = <&gpio0 31 0>;
		backlight = <&backlight>;
		status = "okay";
		u-boot,dm-pre-reloc;
		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <16>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};
		display-timings {
			native-mode = <&timing0>;
			timing0: 800x480 {
				hactive         = <800>;
				vactive         = <480>;
				hback-porch     = <46>;
				hfront-porch    = <210>;
				hsync-len       = <20>;
				vback-porch     = <23>;
				vfront-porch    = <22>;
				vsync-len       = <10>;
				clock-frequency = <33000000>;
				hsync-active    = <0>;
				vsync-active    = <0>;
			};
		};
	};

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Tested-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
a9df3c50ed video: omap: create two routines to set the pixel clock rate
Created in preparation to support driver-model, they can also be called
from legacy code. In this way, code duplication is avoided.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
9d7f53c1e5 video: omap: add loop exit conditions to the dpll setup
In case of null error, round rate is equal to target rate, so it is
useless to continue to search the DPLL setup parameters to get the
desidered pixel clock rate.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-03 13:08:14 +05:30
Dario Binacchi
9aead9ae09 video: omap: fix debug message
"DISP" -> "DIV"

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-03 13:08:14 +05:30
Dario Binacchi
41f76a01f3 video: omap: rename LCD controller registers
Add more clarity by prefixing the name of the register to the bitfields.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
017295f31d video: omap: fix bitfields order
Arrange the bitfields of each register in the ascending order.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
3af43750df video: omap: fix coding style on use of spaces
Use one space around (on each side of) the binary '-' operator.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
e3f82b80cd video: omap: add missing bitfield masks
Add, if missing, the bitfield masks in the setting macros of the LCD
controller registers.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Dario Binacchi
a2f4706479 video: omap: use BIT() and GENMASK() macros
Use the standard BIT() and GENMASK() macros for bitfield definitions.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-03-03 13:08:14 +05:30
Tero Kristo
3e7b0aa1fd power: mfd: k3_avs: update am65xx MPU_VDD voltage values
The latest data manual SPRSP08I –NOVEMBER 2017–REVISED DECEMBER 2019[1]
for am65xx SoC states the new MPU nominal voltages to be 1.1V (OPP_NOM),
1.2V (OPP_OD) and 1.24V (OPP_TURBO). Update the nominal voltages in the
K3 AVS driver to reflect this.

[1] http://www.ti.com/lit/gpn/am6528

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Tero Kristo
3b36b38f50 misc: pmic_esm: Add support for PMIC ESM driver
The ESM (Error Signal Monitor) is used on certain PMIC versions to
handle error signals propagating from rest of the system. If these
reach the PMIC, it is typically a last resort fatal error which
requires a system reset. The ESM driver does the proper configuration
for the ESM module to reach this end goal. Initially, only TPS65941
PMIC is supported for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Tero Kristo
344eb6d572 misc: k3_esm: Add support for Texas Instruments K3 ESM driver
The ESM (Error Signaling Module) is used to route error signals within
the K3 SoCs somewhat similar to interrupts. The handling for these is
different though, and can be routed for hardware error handling, to
be handled by safety processor or just as error interrupts handled
by the main processor. The u-boot level ESM driver is just used to
configure the ESM signals so that they get routed to proper destination.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Tero Kristo
8cd10a494f power: pmic: tps65941: Add support for probing the child devices
TPS65941 can have child devices under it (like the ESM support), so
probe these once the master pmic node completes probe.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-03 13:08:14 +05:30
Vignesh Raghavendra
28ff144662 drivers: Descend to drivers/soc unconditionally
Descend to drivers/soc directory unconditionally for SPL and U-Boot
builds. Individual drivers can have their own config to check what needs
to be built for SPL. There should be no increase in SPL code size
due to this change.

This is required on K3 SoCs to support DMA in SPL.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-03-03 13:08:13 +05:30
Anatolij Gustschin
9aa886cc0b video: meson: keep power domain up after booting
Add driver flag to skip power domain disabling on device removal.

Fixes: 52edfed65d ("dm: core: device: switch off power domain after device removal")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Guillaume La Roque <glaroque@baylibre.com>
2020-03-02 19:47:38 -07:00
Anatolij Gustschin
5349e255ff dm: core: Add a flag for power domain control on device removal
In various cases a power domain must stay enabled after device
removal when booting OS (i.e. serial debug console or display).
Add a flag to selectively skip switching off a power domain.

Fixes: 52edfed65d ("dm: core: device: switch off power domain after device removal")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-03-02 19:47:38 -07:00
Tom Rini
8aad16916d - convert stm32mp1 board documentation to rst format
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Merge tag 'u-boot-stm32-20200203' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- convert stm32mp1 board documentation to rst format
2020-03-02 09:20:30 -05:00
Tom Rini
bd7bb38699 Xilinx fixes for v2020.04-rc4
- Fix link good bit handling in dp83867
 - Rename generic Zynq defconfig
 - Fix zybo z7 low leve setup
 - Fix error path in zynq_gem driver and fix 64bit usage
 - Fix invalid clock name quieries for Versal
 - Fix zynq/zynqmp SPL low level configuration via DT selection
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Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx fixes for v2020.04-rc4

- Fix link good bit handling in dp83867
- Rename generic Zynq defconfig
- Fix zybo z7 low leve setup
- Fix error path in zynq_gem driver and fix 64bit usage
- Fix invalid clock name quieries for Versal
- Fix zynq/zynqmp SPL low level configuration via DT selection
2020-03-02 09:20:12 -05:00
Heinrich Schuchardt
250b303de8 stm32mp1: rng: remove superfluous assignment
We should not assign a value that is overwritten before use.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-03-02 09:41:31 +01:00
Marek Vasut
b371acccad rtc: m41t62: add compatible for m41st87
This adds a compatible string for m41st87. This ensures that this driver
can be used for m41st87.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-03-01 22:07:32 +01:00
Seung-Woo Kim
491cabf067 gadget: f_thor: add missing line breaks for pr_err()
After the commit 9b643e312d ("treewide: replace with error()
with pr_err()"), there are pr_err() usages without line break. Add
missing line breaks for pr_err() used in f_thor.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2020-03-01 21:58:54 +01:00
Andy Shevchenko
53d9bd4a56 dfu: Reset timeout in case of DFU request
In case dfu command is being executed with timeout option,
the timer may expire in the middle of DFU operation. If there
is DFU request coming, we may simple reset timeout value
to prevent aborting of ongoing DFU operation.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Ferry Toth <ftoth@exalondelft.nl>
2020-03-01 21:58:54 +01:00
Christophe Leroy
7e00e907f5 watchdog: Don't select CONFIG_WATCHDOG and CONFIG_HW_WATCHDOG at the same time
Commit 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") introduced an automatic selection of CONFIG_WATCHDOG by
CONFIG_WDT. But for boards selecting CONFIG_HW_WATCHDOG, like
boards have a powerpc 8xx, CONFIG_WATCHDOG shall not be selected
as they are mutually exclusive.

Make CONFIG_WATCHDOG dependent on !CONFIG_HW_WATCHDOG

Fixes: 06985289d4 ("watchdog: Implement generic watchdog_reset() version")
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-02-28 10:53:55 -05:00
Christophe Leroy
a68256074f watchdog: mpc8xx: Revert the 8xx watchdog back to CONFIG_HW_WATCHDOG
Commit f3729ba6e7 ("watchdog: mpc8xx_wdt: Watchdog driver and macros
cleanup") switched the watchdog to CONFIG_WATCHDOG. But this is not
compatible with the 8xx because it starts the watchdog HW timer at
reset and must be serviced from the very beginning including while
U-boot is executed in the firmware before relocation in RAM.

Select CONFIG_HW_WATCHDOG and make hw_watchdog_reset() visible.

Meanwhile, finalise the cleanup of arch/powerpc/cpu/mpc8xx/Kconfig by
removing the lines put in comment in that commit, and also remove
again the selection of CONFIG_MPC8xx_WATCHDOG which was removed by
that commit and brought back by mistake by commit b3134ffbd9
("watchdog: Kconfig: Sort entry alphabetically")

Note that there was an 'imply WATCHDOG' in the original commit but
it disappeared in the Kconfig alphabetical sorting, so no need to
remove it here.

Fixes: f3729ba6e7 ("watchdog: mpc8xx_wdt: Watchdog driver and macros cleanup")
Fixes: b3134ffbd9 ("watchdog: Kconfig: Sort entry alphabetically")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Stefan Roese <sr@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-02-28 10:53:55 -05:00
Michal Simek
58ecd9ad0b net: zynq: Free allocated buffers in case of error
Driver probe function is called again and again in case of error.
Malloc space is getting full which is is reported by:
 Insufficient RAM for page table: 0x15000 > 0x14000.
 Please increase the size in get_page_table_size()
 ### ERROR ### Please RESET the board ###

The patch is freeing allocated buffers on error path to avoid panic.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28 12:04:10 +01:00
Michal Simek
380376520f net: phy: dp83867: Clean force link good bit
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.

Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.

Fixes: 37d6265f2b ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-02-28 12:04:10 +01:00
T Karthik Reddy
4c2c28a465 mtd: nand: Fix on-die ecc issues in arasan_nfc driver
Fixed wrong enumeration of nand_config structure. Added chip select
function before reading the nand chip for maf/dev id's, without this
unable to access id's from some of the micron chips. Also added a
print statement to identify if a nand flash is using on-die ecc.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28 12:04:10 +01:00
Rajan Vaja
65bcca9f52 versal: drivers: clk: Fix invalid clock name queries
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling versal_pm_clock_get_name() in versal_get_clock_info() function.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28 12:04:10 +01:00
T Karthik Reddy
b6779274f2 net: zynq_gem: Use ulong instead of u32 data type
flush_dcache_range() expects unsigned long in the arguments. Here u32
variable is unable to hold the higher address value when ddr mapped
to higher addresses & flushing lower address dchache range instead
which is unmapped causing to crash.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-28 12:04:10 +01:00
Vignesh Raghavendra
7a8d03f88e misc: k3_avs: Fix possible NULL pointer deference
Its possible that k3_avs_priv is NULL because the driver may not have
been probed yet. Therefore check if pointer is valid before
dereferencing it.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-02-26 18:35:29 +05:30
Peng Ma
5ff78d11e5 Revert "ata: fsl_ahci: Add sata DM support for Freescale powerpc socs"
This reverts commit 1ee4942918.

Commit 1ee4942918 ("ata: fsl_ahci: Add sata DM support for Freescale
powerpc socs") introduced SCSI layer to call AHCI private API in order
to support sata operations, In DM mode, This is not necessary for
non-AHCI sata. So revert it and have already updated the driver itself
to operate sata directly.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-25 10:16:05 +05:30
Tom Rini
4246fae418 Merge tag 'mmc-2-20-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- sdhci: code clean-up and fix cache coherency problem
- enable cache snooping on mpc830x
- Fix build error when MMC_WRITE disabled
2020-02-20 07:27:31 -05:00
Masahiro Yamada
4155ad9aac mmc: sdhci: fix missing cache invalidation after reading by DMA
This driver currently performs cache operation before the DMA start,
but does nothing after the DMA completion.

When reading data by DMA, the cache invalidation is needed also after
finishing the DMA transfer. Otherwise, the CPU might read data from
the cache instead of from the main memory when speculative memory read
or memory prefetch occurs.

Instead of calling the cache operation directly, this commit adds
dma_unmap_single(), which performs cache invalidation internally,
but drivers do not need which operation is being run.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-20 15:09:57 +08:00
Masahiro Yamada
58d8ace12b mmc: sdhci: use dma_map_single() instead of flush_cache() before DMA
Currently, sdhci_prepare_dma() calls flush_cache() regardless of the
DMA direction.

Actually, cache invalidation is enough when reading data from the device.

This is correctly handled by dma_map_single(), which mimics the DMA-API
in Linux kernel. Drivers can be agnostic which cache operation occurs
behind the scene.

This commit also sanitizes the difference between the virtual address
and the dma address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-20 15:09:57 +08:00
Masahiro Yamada
fdd84c8be4 mmc: sdhci: remove unneeded casts
host->mmc is already (struct mmc *).

memalign() returns an opaque pointer, so there is no need for casting.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20 15:09:56 +08:00
Masahiro Yamada
a2b0221c9c mmc: sdhci: use lower_32_bit2() and upper_32_bits() for setting adma_addr
Use {lower,upper}_32_bits() instead of the combination of cast
and shift.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20 15:09:55 +08:00
Masahiro Yamada
f5df6aa1e6 mmc: sdhci: reduce code duplication for aligned buffer
The same code is run for both SDHCI_QUIRK_32BIT_DMA_ADDR and
define(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER).

Unify the code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20 15:09:55 +08:00
Masahiro Yamada
c8cc18b7a7 mmc: sdhci: put the aligned buffer pointer to struct sdhci_host
Using the global variable does not look nice.

Add a new field sthci::align_buffer to point to the bounce buffer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-20 15:09:54 +08:00
Masahiro Yamada
9d86b89c59 dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>
The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.

Factor them out to <linux/dma-mapping.h>, and make all drivers to
include <linux/dma-mapping.h> instead of <asm/dma-mapping.h>.

If we need to differentiate them for some architectures, we can
move the generic definitions to <asm-generic/dma-mapping.h>.

Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Masahiro Yamada
950c596867 dma-mapping: fix the prototype of dma_unmap_single()
dma_unmap_single() takes the dma address, not virtual address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-19 21:27:30 +08:00
Rasmus Villemoes
ede2822864 mmc: fsl_esdhc: actually enable cache snooping on mpc830x
The reference manuals for MPC8308 and MPC8309 both say that the
esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the
System configuration registers. Unfortunately, that doesn't mean that
the registers are just mirrors of each other - any write to esdhcctl
is simply ignored. So to actually enable cache snooping, we
unfortunately have to add a little ifdeffery.

There is, naturally, no description of the bit fields of esdhcctl in
the MPC8309 manual, but comparing the description of esdhcctl from the
LS1021A reference manual to the description of the sdhccr in MPC8309,
one also finds that the fields are bit-reversed, so the bit to set is
0x02000000 rather than 0x00000040 - this is also what board_mmc_init()
uses in the two gdsys/mpc8308/ boards.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-02-19 21:21:42 +08:00
Simon Glass
64d44c4e9f i2c: designware_i2c: Correct the selection of speed mode
Unfortunately a recent change adjusted the order of the checks here such
that 400MHz now shows up as fast-plus speed (1Mbps). Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d96440d1e3 ("i2c: designware_i2c: Add support for fast-plus speed")
2020-02-18 08:16:45 +01:00
Masahiro Yamada
76ca2d1303 mmc: remove unneeded forward declarations
These functions are defined before the callers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-02-17 14:55:04 +08:00
Masahiro Yamada
8adf50effe mmc: check the return value of mmc_select_mode_and_width()
Since commit 01298da31d ("mmc: Change mode when switching to a boot
partition"), errors in mmc_select_mode_and_width() are ignored.
The return value should be checked.

Fixes: 01298da31d ("mmc: Change mode when switching to a boot partition")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-02-17 14:55:04 +08:00
Masahiro Yamada
54a78cbdbe mmc: sdhci-cadence: send tune request twice to work around errata
Cadence sent out an errata report to their customers of this IP.
This errata is not so severe, but the tune request should be sent
twice to avoid the potential issue.

Quote from the report:

Problem Summary
---------------
The IP6116 SD/eMMC PHY design has a timing issue on receive data path.
This issue may lead to an incorrect values of read/write pointers of
the synchronization FIFO. Such a situation can happen at the SDR104
and HS200 tuning procedure when the PHY is requested to change a phase
of sampling clock when moving to the next tuning iteration.

Workarounds
-----------
The following are valid workarounds to resolve the issue:

1. In eMMC mode, software sends tune request twice instead of once at
   each iteration. This means that the clock phase is not changed on
   the second request so there is no potential for clock instability.
2. In SD mode, software must not use the hardware tuning and instead
   perform an almost identical procedure to eMMC, using the HRS34 Tune
   Force register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-17 14:55:04 +08:00
Jaehoon Chung
4af6659605 mmc: fix the build error when MMC_WRITE is disabled
erase_grp_size is used, when MMC_WRITE is enabled.
- error: ‘struct mmc’ has no member named ‘erase_grp_size’

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-02-17 14:55:04 +08:00
Bharat Kumar Reddy Gooty
ae93d8106b drivers: mmc: rpmb: Use R1 response
If the host has Broken R1B, use only R1 response type.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
2020-02-17 14:55:04 +08:00
Tom Rini
f2a73d6867 - add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
 - fix STM32 image format for big endian hosts in mkimage
 - solve warnings in device tree and code for stm32mp1 boards
 - remove fdt_high and initrd_high for stm32 and stih boards
 - add support of STM32MP15x Rev.Z
 - update stm32mp1 readme
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Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
2020-02-14 07:31:47 -05:00
Patrick Delaunay
eb49dce0d8 clk: stm32mp1: solve type issue in stm32mp1_lse_enable and stm32mp1_clktree
Solve type issue in stm32mp1_lse_enable and stm32mp1_clktree.

This patch solves the warnings when compiling with W=1
on stm32mp1 board:

clk_stm32mp1.c: In function ‘stm32mp1_lse_enable’:
clk_stm32mp1.c:1238:15: warning: comparison of integer expressions
  of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
  [-Wsign-compare]
clk_stm32mp1.c:1239:13: warning: comparison of integer expressions
  of different signedness: ‘u32’ {aka ‘unsigned int’} and ‘int’
  [-Wsign-compare]

clk_stm32mp1.c: In function ‘stm32mp1_clktree’:
clk_stm32mp1.c:1814:17: warning: comparison of integer expressions
  of different signedness: ‘int’ and ‘unsigned int’
  [-Wsign-compare]

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13 18:47:00 +01:00
Patrick Delaunay
b10089233e pinctrl: stmfx: update the result type of dm_i2c_reg_read
Use int as result of dm_i2c_reg_read to avoid warning with
W=1 (warning: comparison is always false due to limited range
of data type [-Wtype-limits])

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13 18:47:00 +01:00
Michal Simek
e3dc5924ca ram: rockchip: Fix Kconfig dependency for RAM_ROCKCHIP_DEBUG
There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files
as I see it for Xilinx ZynqMP.

\# CONFIG_U_QE is not set
\# CONFIG_RAM is not set
CONFIG_RAM_ROCKCHIP_DEBUG=y

Add missing dependency on RAM_ROCKCHIP driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-13 10:10:50 -05:00
Eugeniy Paltsev
defd1e71d0 CLK: HSDK: fix HDMI clock calculation
HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-02-12 20:47:39 +03:00
Eugeniy Paltsev
b8f3ce0137 CLK: HSDK: Check for PLL bypass firstly
Pll bypass has priority over enable/disable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-02-12 20:47:14 +03:00
Tom Rini
9a8942b53d sandbox conversion to SDL2
TPM TEE driver
 Various minor sandbox video enhancements
 New driver model core utility functions
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Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
2020-02-11 10:58:41 -05:00
Lukasz Majewski
b7adcdd073 regulator: fix: Move code to enable gpio regulator to pre_probe from ofdata_to_platdata
The commit e8e9715df2 ("regulator: fixed: Modify enable-active-high behavior")
fixed the regulator driver behavior when 'enable-active-high' is defined.
Unfortunately, this patch used dm_regulator_platdata()'s "boot_on" member
to set GPIOD_IS_OUT_ACTIVE flag and enable the regulator.

The issue here is that regulator_common_ofdata_to_platdata() is called
_before_ regulator_pre_probe() function in which the 'regulator-boot-on'
property is asserted.

As a result the GPIOD_IS_OUT_ACTIVE flag is not set and gpio_request_by_name()
called in the former function is not enabling the regulator.
This is problematic for e.g. i.MX ethernet driver, which then tries to
perform initialization without power (and fails).

The solution here is to explicitly enable regulator in regulator_pre_probe()
callback only when 'regulator-boot-on' property is present in device tree.
The GPIOD_IS_OUT_ACTIVE flag is not set at all, but relevant gpio is
requested.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-10 18:00:38 -05:00
Tom Rini
4e5c4683b7 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Move P2SB from Apollo Lake to a more generic location
- Add a function to find a device by drvdata in DM core
- Enhancement of DM IRQ uclass driver
- Add a clock driver for Intel devices
- Add support for ACPI general-purpose events
- Add a TPM driver for H1/Cr50
- Enable TPM on Google Chromebook Coral
2020-02-10 12:27:31 -05:00
Tom Rini
5f2fe7d461 - fix Coverity CID 280902 issue in vid_console_color()
- fix vid_console_color() build warning
 - fix for mxsfb to ensure correct Linux logo position
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Merge tag 'fixes-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- fix Coverity CID 280902 issue in vid_console_color()
- fix vid_console_color() build warning
- fix for mxsfb to ensure correct Linux logo position
2020-02-10 12:08:51 -05:00
Robert Beckett
821c982e35 misc: i2c_eeprom: set offset len and chip addr offset mask
Set the correct offset length and chip address offset mask for each
device to allow correct access to total capacity of the devices.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-02-09 21:47:20 +01:00
Fabio Estevam
c0a179a7a5 gpio: Let DM_74X164 be built without CONFIG_SPL_GPIO
Since commit bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
CONFIG_DM_74X164 is no longer built for mx7dsabresd_defconfig, as
this target does not use CONFIG_SPL_GPIO.

Remove such dependency and let the the 74X164 GPIO driver be built
again.

This restores Ethernet functionality on the imx7-sdb board as the
Ethernet reset PHY comes from a GPIO driven by a 74LV595PW I/O
expander.

Fixes: bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Alifer Moraes <alifer.wsdm@gmail.com>
2020-02-09 14:52:39 +01:00
Jason Li
0de653d8cf serial: serial_cortina: add UART DM driver for CAxxxx SoCs
Add serial UART driver support for all Cortina Access
CAxxxx family of SoCs.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-02-07 16:16:01 -05:00
Jason Li
7f54b83870 watchdog: cortina_wdt: add support for HW WDT on CAxxxx SoCs
Add support for hardware watchdog timer on all Cortina Access
CAxxxx family of SoCs.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-02-07 16:15:57 -05:00
Jason Li
2ccacf3c7f gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs
DM_GPIO based GPIO controller driver for CAxxxx SoCs.
This driver support multiple CPU architectures and
Cortina Access SoC platforms.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-02-07 14:01:21 -05:00
Frank Wunderlich
47b1431d50 eth: mtk-eth: aarch64: fix build warnings on ethernet-driver
building mtk ethernet driver for aarch64 (mt7622) results
in warnings/errors

  "error: cast from pointer to integer of different size"

Fixes: 23f17164d9 ("ethernet: MediaTek: add ethernet driver for MediaTek ARM-based SoCs")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-02-07 13:59:58 -05:00
MarkLee
e395717ca9 eth: mtk-eth: add mt7622 support in mediatek eth driver
This patch add mt7622 support in mediatek eth driver

Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
2020-02-07 13:59:58 -05:00
MarkLee
b4ef49a905 eth: mtk-eth: add sgmii mode support in mediatek eth driver
This patch add sgmii init part for the mediatek SoC that
support sgmii mode. It is a must for mt7622.

Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
2020-02-07 13:59:58 -05:00
Simon Glass
d36856a385 tpm: Add a driver for H1/Cr50
H1 is a Google security chip present in recent Chromebooks, Pixel phones
and other devices. Cr50 is the name of the software that runs on H1 in
Chromebooks.

This chip is used to handle TPM-like functionality and also has quite a
few additional features.

Add a driver for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-07 22:46:35 +08:00
Simon Glass
025543554c dm: irq: Add support for requesting interrupts
At present driver model supports the IRQ uclass but there is no way to
request a particular interrupt for a driver.

Add a mechanism, similar to clock and reset, to read the interrupts
required by a device from the device tree and to request those interrupts.

U-Boot itself does not have interrupt-driven handlers, so just provide a
means to read and clear an interrupt. This can be useful to handle
peripherals which must use an interrupt to determine when data is
available, for example.

Bring over the basic binding file as well, from Linux v5.4. Note that the
older binding is not supported in U-Boot; the newer 'special form' must be
used.

Add a simple test of the new functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:46:32 +08:00
Simon Glass
69c2dc937a x86: Give each driver an IRQ type
Add an IRQ type to each driver and use irq_first_device_type() to find
and probe the correct one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:45:35 +08:00
Simon Glass
ba87607971 dm: irq: Add support for interrupt controller types
There can be different types of interrupt controllers in a system and some
drivers may need to distinguish between these. In general this can be
handled using the device tree by adding the interrupt information to
device nodes.

However on x86 devices we have interrupt controllers which are not tied
to any particular device and not really used in U-Boot. These still need
to be inited, so a convenient method is to give each controller a type
and allow a particular controller type to be probed.

Add support for this in sandbox along with a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove the new bland line at EOF of test/dm/irq.c]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:44:59 +08:00
Simon Glass
b4d00b256e x86: Add a clock driver for Intel devices
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.

This driver can be expanded later as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:41:24 +08:00
Simon Glass
fdec36f248 tegra: i2c: Change driver to use helper function
Now that we have uclass_first_device_drvdata(), use it from the I2C driver
to reduce code duplication.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:41:24 +08:00
Simon Glass
ae44cafcb3 dm: core: Change syscon to use helper function
Now that we have uclass_first_device_drvdata(), use it from syscon to
reduce code duplication.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:41:24 +08:00
Simon Glass
50162348f0 dm: core: Add a function to find a device by drvdata
It is sometimes useful to find a device in a uclass using only its driver
data. The driver data often indicates the 'subtype' of the device, e,g,
via its compatible string.

Add a function to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-07 22:41:24 +08:00
Tom Rini
457faef262 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Gen 5 and Watchdog fixes
2020-02-06 23:18:42 -05:00
Anatolij Gustschin
8a6ffeda97 video: enable VIDEO_ANSI and all VIDEO_BBP options
This partially reverts changes by commit 2cc393f32f
("video: make BPP and ANSI configs optional") since it
caused issues with other boards (missing LCD console
output on pinebook, x86 platform or sandbox). Enable
all disabled options again and opt out of not supported
color depth in board defconfigs.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Vagrant Cascadian <vagrant@debian.org>
2020-02-06 16:11:47 -05:00
Simon Glass
21d651fb29 sandbox: Complete migration away from os_malloc()
Now that we can use direct access to the system malloc() in sandbox, drop
the remaining uses of os_malloc().

The only one remaining now is for the RAM buffer, which we do want to be
at a known address, so this is intended.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 21:48:23 -07:00
Simon Glass
f217651575 dm: core: Drop the inclusion of linux/compat.h in dm.h
Most files don't need this header and it pulls in quite of lots of stuff,
malloc() in particular. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 21:48:22 -07:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
61b29b8268 dm: core: Require users of devres to include the header
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
a466db5adb sandbox: Support changing the LCD colour depth
Add a new device-tree property to control the colour depth. At present we
support 16bpp and 32bpp.

While we are here, update the code to use livetree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
6be88c7282 sandbox: sdl: Add an option to double the screen size
On high-DPI displays U-Boot's LCD window can look very small. Add a
-K flag to expand it to make things easier to read, while still using
the existing resolution internally.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
02662480a8 sandbox: sound: Handle errors better in sound_beep()
At present an error does not stop the sound-output loop. This is incorrect
since nothing can be gained by trying to continue. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
3062cd17af sound: Add a new stop_play() method
At present there is no positive indication that U-Boot has finished
sending sound data. This means that it is not possible to power down an
audio codec, for example. Add a new method that is called once all sound
data has been sent.

Add a new method for this, called when the sound_play() call is done.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
8d38a8459b mtd: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
aae9588223 dma: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
fb8c0d595f clk: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
093152f275 gpio: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
94474b25c3 reset: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
4f51188e47 power-domain: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
cc92c3cc68 mailbox: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
3b85ce8ec3 video: sandbox: Enable all colour depths
For sandbox we want to have the maximum possible build coverage, so enable
all colour depths for video.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
51973ccc41 video: Support truetype fonts on a 32-bit display
At present only a 16bpp display is supported for Truetype fonts. Add
support for 32bpp also since this is quite common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Sean Anderson
7b9d60fc1f cmd: Add command to dump drivers and compatible strings
This adds a subcommand to dm to dump out what drivers are installed, and their
compatible strings. I have found this useful in ensuring that I have the correct
drivers compiled, and that I have put in the correct compatible strings.

Signed-off-by Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Thirupathaiah Annapureddy
8d73be7a8e tpm2: ftpm: A driver for firmware TPM running inside TEE
Add a driver for a firmware TPM running inside TEE.

Documentation of the firmware TPM:
https://www.microsoft.com/en-us/research/publication/ftpm-software-implementation-tpm-chip/

Implementation of the firmware TPM:
https://github.com/Microsoft/ms-tpm-20-ref/tree/master/Samples/ARM32-FirmwareTPM

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
2020-02-05 19:33:46 -07:00
Simon Glass
eb7387ae14 sandbox: pmic: Correct i2c pmic emulator platdata method
This currently reads the uclass's private data in the ofdata_to_platdata
method which is not allowed, since the uclass has not read it from the
device tree. This happens in the probe method.

Fix it by adding a probe() method and moving the code there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
9ff5e0495d dm: core: Drop uclass_find_next_free_req_seq() conditions
These conditions are not needed and just reduce build coverage. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
903e83ee84 dm: core: Add a way to iterate through children, probing each
It is sometimes useful to process all children, making sure they are
probed first. Add functions to help with this and a macro to make it more
convenient.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
f262d4ca4b dm: core: Add a way to read platdata for all child devices
When generating ACPI tables we need to make sure that all devices have
read their platform data, so that they can generate the tables correctly.

Rather than adding this code in ACPI, create a core function to handle it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
bd933bfd83 dm: core: Add ofnode_get_chosen_prop()
Add a function to read a property from the chosen node, providing access
to its length. Update ofnode_get_chosen_string() to make use of it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
1aada6313c dm: core: Reimplement ofnode_read_size()
Now that we have ofnode_read_prop() we can rewrite this function using
that one, reducing the amount of duplicated code.

Update ofnode_read_size() and move it up next to the other similar
functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
a8167d8ee2 dm: core: Add ofnode_read_prop()
Add a new function to read a property that supports reading the length as
well.

Reimplement ofnode_read_string() using it and fix its comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
14ca9f7f5a dm: core: Rename ofnode_get_chosen_prop()
This function is actually intended to read a string rather than a
property. All of its current callers use it that way. Also there is no way
to return the length of the property from this function.

Rename it to better indicate its purpose, using ofnode_read as the prefix
since this matches most other functions.

Also add some tests which are missing for these functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
88b3a37eaa dm: core: Use const device for the dev_read_...() interface
These functions do not modify the device so should use a const pointer to
it. Update the code accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
d975ce21ce dm: core: Use const device for the devfdt...() interface
These functions do not modify the device so should use a const pointer to
it. Update the code accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
194fca9130 dm: pci: Update a few more interfaces for const udevice *
Tidy up a few places where const * should be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
c4e72c4ad8 dm: pci: Update the PCI read_config() method to const dev *
At present this method uses a non-const udevice pointer, but the call
should not modify the device. Use a const pointer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Simon Glass
fc347fbdd4 dm: core: Use const where possible in device.h
Update this header file to use const devices where possible, to permit
callers to also use const.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:45 -07:00
Tom Rini
f5cc89a82a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes on ls1012a, ls1021a, ls1028ardb platforms Integrate fspi for
  ls1028a, add DM-I2C support, update secure boot header offset
2020-02-05 07:19:52 -05:00
Tom Rini
c95215a6ca - DFU support file operations lager then the default max size
- add dfu support to dwc2 for bcm2835
 - enable DFU for RPi4
 - Fix RPi4 memory map to include the genet device
 - add driver for the genet ethernet device
 - enable network support in RPi4 config
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Merge tag 'rpi-next-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi

- DFU support file operations lager then the default max size
- add dfu support to dwc2 for bcm2835
- enable DFU for RPi4
- Fix RPi4 memory map to include the genet device
- add driver for the genet ethernet device
- enable network support in RPi4 config
2020-02-05 07:18:12 -05:00
Marek Vasut
9a5a90ad9b ddr: altera: Add DDR2 support to Gen5 driver
Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated
by Quartus are named differently than the DDR3 ones, use anon unions to
store them in the same structures, without growing their size.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-05 03:01:57 +01:00
Marek Vasut
cf89ef8d10 watchdog: designware: Optionally fetch clock and reset from DT
Add optional support for fetching watchdog clock rate from DT
and ungating reset via reset framework. This is optional as not
all platforms using DW WDT support the clock and reset frameworks
yet.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
2020-02-05 03:01:57 +01:00
Marek Vasut
cf8c836788 watchdog: designware: Convert to DM and DT probing
Convert the designware watchdog timer driver to DM and add DT probing
support. Perform minor coding style clean up, like drop superfluous
braces. These ought to be no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
2020-02-05 03:01:57 +01:00
Anatolij Gustschin
8382b10192 video: mxsfb: call remove() when booting OS
Add DM_FLAG_OS_PREPARE flag to ensure that the driver's
remove() callback is invoked before booting the kernel.
This is required to stop the LCDIF controller. This was
the behaviour with old driver without DM_VIDEO support.
Without stopping the LCDIF we sometimes observe incorrect
Linux logo position.

Fixes: ae0760584b ("imx: mx6ul_14x14_evk: convert to DM_VIDEO")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reported-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-02-04 23:04:28 +01:00
Anatolij Gustschin
ab6ea931de video: fix Coverity missing break issue
Fix:
>>>  CID 280902:  Control flow issues  (MISSING_BREAK)
>>>  The case for value "VIDEO_BPP32" is not terminated
>>>  by a 'break' statement.

Also fix
error: control reaches end of non-void function [-Werror=return-type]

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-02-04 23:02:56 +01:00
Tom Rini
d4827fcd4c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Various minor fixes for x86
- Switch to ACPI mode on Intel edison
- Support run-time configuration for NS16550 driver
- Update coreboot and slimbootloader serial drivers to use NS16550
run-time configuration
- ICH SPI driver fixes to hardware sequencing erase case
- Move ITSS from Apollo Lake to a more generic location
- Intel GPIO driver bug fixes
- Move to vs2017-win2016 platform build host for Azure pipelines
2020-02-04 11:36:49 -05:00
Biwen Li
c69103218e i2c: mxc_i2c: add DM_FLAG_PRE_RELOC flag
This adds DM_FLAG_PRE_RELOC flag to probe i2c driver
before relocation

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-04 16:20:25 +05:30
Biwen Li
42cd5cbce4 rtc: pcf8563: Add driver model support
Add support of driver model of pcf8563

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-02-04 16:20:25 +05:30
Wolfgang Wallner
ea86e725d4 gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()
Fix the following in intel_gpio_get_value():

 * The value of the register is contained in the variable 'reg', not in
   'mode'. The variable 'mode' contains only the configuration whether
   the gpio is currently an input or an output.

 * The correct bitmasks for the input and output value are
   PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE.
   Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and
   PAD_CFG0_TX_STATE_BIT.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 12:54:55 +08:00
Wolfgang Wallner
28c626804d gpio: intel_gpio: Clear tx state bit when setting output
Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32().
Otherwise this bit cannot be cleared again after it has been set once.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 12:54:55 +08:00
Wolfgang Wallner
b840c395c6 gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()
The function pcr_clrsetbits32() expects a device with a P2SB parent
device. In intel_gpio_direction_output() and intel_gpio_set_value()
the device 'dev' is passed to pcr_clrsetbits32(), which is a
gpio-controller with a device 'pinctrl' as parent. This does not match
the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a
P2SB as parent.

Pass the 'pinctrl' device instead of the 'dev' device to
pcr_clrsetbits32().

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 12:54:54 +08:00
Marek Vasut
4dd0593398 watchdog: omap_wdt: Fix WDT coding style
Fix obvious coding style problems, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:25 +05:30
Marek Vasut
11c1af60b5 watchdog: omap_wdt: Fix WDT reloading
The watchdog timer value was never updated in the hardware by this
driver, so the watchdog triggered on some random stale value that
was left in the hardware. The TI SPRUH37C says, quote:

  20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting
  ...
  After a write access, the load register value and prescaler ratio
  registers are updated immediately, but new values are considered
  only after the next consecutive counter overflow or after a new
  trigger command (the WDT_WTGR register).

This means at least one trigger must happen. The driver probably
depended on someone calling it's .reset() callback, however that
is not guaranteed e.g. if the WDT operates without servicing.

Add this missing trigger.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Marek Vasut
8a9ec4dd5f watchdog: omap_wdt: Fix WDT timeout configuration
The timeout parameter of omap3_wdt_start() is in miliseconds, while
GET_WLDR_VAL() expects parameter in seconds. Fix this so the WDT
driver is actually usable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Suniel Mahesh <sunil.m@techveda.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
25216d68fa gpio: da8xx_gpio: Add "ti,keystone-gpio" compatible
Add "ti,keystone-gpio" compatible so as be able to use Linux DT files as
is.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
94f992d57a gpio: da8xx_gpio: Fix compiler warning
Fix below compiler warning for 64bit builds

drivers/gpio/da8xx_gpio.c: In function ‘davinci_get_gpio_bank’:
drivers/gpio/da8xx_gpio.c:446:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  return (struct davinci_gpio *)addr;

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
dd6638a018 gpio: pca953x_gpio: Add support for 24 bit IO expander
J721e EVM has a TCA6424 IO expander that has 24 GPIOs. Add support for
the same

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Wolfgang Wallner
142c9751a6 x86: Move itss.h from Apollo Lake to the generic x86 include directory
The code in this file is not specific to Apollo Lake. According to
coreboot sources (where this code comes from), it is common to at least:
  * Apollo Lake
  * Cannon Lake
  * Ice Lake
  * Skylake

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 01:19:28 +08:00
Wolfgang Wallner
5e579cc004 spi: ich: Drop while loop in hardware sequencing erase case
When ich_spi_exec_op_hwseq() is called to erase a 4k block
(opcode = SPINOR_OP_BE_4K), it expects to find a length value in
op->data.nbytes, but that value is always 0. As a result, the while loop
is never executed and no erase is carried out.

Fix this by dropping the loop code entirely, only keeping the relevant
parts of the loop body.

See http://patchwork.ozlabs.org/patch/1222779/ for more detailed
background information and discussion.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 01:19:28 +08:00
Simon Glass
44482e8a2a x86: serial: Add a coreboot serial driver
Coreboot can provide information about the serial device in use on a
platform. Add a driver that uses this information to produce a working
UART.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 01:19:25 +08:00
Simon Glass
62cbde4c4e serial: ns16550: Support run-time configuration
At present this driver uses an assortment of CONFIG options to control
how it accesses the hardware. This is painful for platforms that are
supposed to be controlled by a device tree or a previous-stage bootloader.

Add a new CONFIG option to enable fully dynamic configuration. This
controls register spacing, size, offset and endianness.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 01:19:13 +08:00
Marek Vasut
8941f8414d watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2020-02-03 09:26:14 +01:00
Ley Foon Tan
9e6082198a reset: socfpga: Poll for reset status after deassert reset
In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.

Retry with this fix more than 10 times without issue.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-02-03 09:26:14 +01:00
Tom Rini
31a790bee9 Merge branch 'master' of git://git.denx.de/u-boot-usb
- DFU and Cadence USB 3 fixes
2020-02-02 15:26:53 -05:00
Guillermo Rodríguez
13cb7cc9e8 dfu: Add option to skip empty pages when flashing UBI images to NAND
Add a new option to enable the DROP_FFS flag when flashing UBI images to
NAND in order to drop trailing all-0xff pages.

This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option.

Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
2020-02-02 18:19:52 +01:00
Vignesh Raghavendra
bf16a7be90 usb: cdns3: ep0: Invalidate cache before reading Setup Packet
Invalidate dcache line before accessing Setup Packet contents. Otherwise
driver will see stale content on non coherent architecture.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-02-02 18:19:52 +01:00
Tom Rini
427da6f028 Merge tag 'u-boot-rockchip-20200130' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Support redundant boot for rk3399
- Support binman for rockchip platform
- Update ram driver and add ddr4 support for rk3328
2020-02-01 15:31:04 -05:00
Tom Rini
80e99adbe4 UniPhier SoC updates for v2020.04 (2nd)
Denali NAND driver changes:
  - Set up more registers in denali-spl for SOCFPGA
  - Make clocks optional
  - Do not assert reset signals in the remove hook
  - associate SPARE_AREA_SKIP_BYTES with DT compatible
  - switch to UCLASS_MTD
 
 UniPhier platform changes:
  - fix a bug in dram_init()
  - specify loadaddr for "source" command
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Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.04 (2nd)

Denali NAND driver changes:
 - Set up more registers in denali-spl for SOCFPGA
 - Make clocks optional
 - Do not assert reset signals in the remove hook
 - associate SPARE_AREA_SKIP_BYTES with DT compatible
 - switch to UCLASS_MTD

UniPhier platform changes:
 - fix a bug in dram_init()
 - specify loadaddr for "source" command
2020-01-31 13:26:28 -05:00
Masahiro Yamada
407b01b3b3 mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISC
UCLASS_MTD is a better fit for NAND drivers.

Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile
drivers/mtd/mtd-uclass.c

Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig
of this platform enables NAND_DENALI_DT.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-02-01 01:14:32 +09:00
Masahiro Yamada
80924cc164 mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatible
Currently, the denali NAND driver in U-Boot configures the
SPARE_AREA_SKIP_BYTES based on the CONFIG option.

Recently, Linux kernel merged a patch that associates the proper
value for this register with the DT compatible string.

Do likewise in U-Boot too.

The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01 01:14:32 +09:00
Masahiro Yamada
21d4a3ca54 mtd: rawnand: denali_dt: insert udelay() after reset deassert
When the reset signal is de-asserted, the HW-controlled bootstrap
starts running unless it is disabled in the SoC integration.
It issues some commands to detect a NAND chip, and sets up registers
automatically. Until this process finishes, software should avoid
any register access.

Without this delay function, some of UniPhier boards hangs up while
executing nand_scan_ident(). (denali_read_byte() is blocked)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01 01:14:32 +09:00
Marek Vasut
9925df051a mtd: rawnand: denali: Do not reset the block before booting the kernel
The Denali NAND driver in mainline Linux currently cannot deassert the
reset. The upcoming Linux 5.6 will support the reset controlling, and
also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in
the future kernel will work without relying on any bootloader or firmware.
However, we still need to take care of stable kernel versions for a while.
U-boot should not assert the reset of this controller.

Fixes: ed784ac382 ("mtd: rawnand: denali: add reset handling")
Signed-off-by: Marek Vasut <marex@denx.de>
[yamada.masahiro: reword the commit description]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01 01:14:32 +09:00
Masahiro Yamada
11bcc5841a mtd: rawnand: denali_dt: make the core clock optional
The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
2020-02-01 01:14:32 +09:00
Marek Vasut
33672c970b mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA
On Altera SoCFPGA, upon either cold-boot or power-on reset, the
Denali NAND IP is initialized by the BootROM ; upon warm-reset,
the Denali NAND IP is NOT initialized by BootROM. In fact, upon
warm-reset, the SoCFPGA BootROM checks whether the SPL image in
on-chip RAM is valid and if so, completely skips re-loading the
SPL from the boot media.

This does sometimes lead to problems where the software left
the boot media in inconsistent state before warm-reset, and
because the BootROM does not reset the boot media, the boot
media is left in this inconsistent state, often until another
component attempts to access the boot media and fails with an
difficult to debug failure. To mitigate this problem, the SPL
on Altera SoCFPGA always resets all the IPs on the SoC early
on boot.

This results in a couple of register values, pre-programmed by
the BootROM, to be lost during this reset. To restore correct
operation of the IP on SoCFPGA, these values must be programmed
back into the controller by the driver. Note that on other SoCs
which do not use the HW-controlled bootstrap, more registers
may have to be programmed.

This also aligns the SPL behavior with the full Denali NAND
driver, which sets these values in denali_hw_init().

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-01 01:14:32 +09:00
Flavio Suligoi
dad9af590a net: fix typo
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
2020-01-30 13:30:35 -05:00
Kever Yang
31531f6fdb ram: rk3328: only do data traning for cs0
No need to do twice data training for rk3328 ddr sdram, we re-use the
setting for both channel. And adjust the sdram_init properly for correct
init flow.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-01-30 11:44:01 +08:00
Jagan Teki
b52a199e32 arm: rockchip: Add common cru.h
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.

So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.

The rest of rockchip cru files will add it in future.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30 11:44:01 +08:00
Thomas Hebb
95052b4b40 ram: rk3399: don't assume phy_io_config() uses real regs
In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.

However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.

This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):

Before:

  sdram_init() Starting SDRAM initialization...
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 0
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

After:

  sdram_init() Starting SDRAM initialization...
  sdram_init() sdram_init: data trained for rank 2, ch 0
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-30 11:44:01 +08:00
Amit Singh Tomar
d53e3fa385 net: Add support for Broadcom GENETv5 Ethernet controller
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs
and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4.
There is no publicly available documentation, so this driver is based
on the Linux driver. Compared to that the queue management is
drastically simplified, also we only support version 5 of the IP and
RGMII connections between MAC and PHY, as used on the RPi4.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: heavy cleanup and a few fixes]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29 18:30:33 +01:00
Marek Szyprowski
c4d08cb9b1 usb: dwc2_udc_otg: add bcm2835 SoC (Raspberry Pi4) support
Broadcom 2835 SoC requires special conversion of physical memory addresses
for DMA purpose, so add needed wrappers to dwc2_udc_otg driver. Also extend
the list of compatible devices with 'brcm,bcm2835-usb' entry. This allows
to use USB gadget drivers (i.e. DFU) on Raspberry Pi4 boards.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29 18:30:33 +01:00
Marek Szyprowski
c2a1e3dbf8 dfu: mmc: remove file size limit for io operations
Add support for operations on files larger than
CONFIG_SYS_DFU_MAX_FILE_SIZE. The buffered io mechanism is still used for
aggregating io requests, so for files up to CONFIG_SYS_DFU_MAX_FILE_SIZE
nothing is changed and they will be handled in a single filesystem call.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29 18:30:33 +01:00
Marek Szyprowski
774f8b00b6 dfu: mmc: rearrange the code
Rename functions for bufferred file io operations to make them easier to
understand. Also add missing file offset argument to them (currently
unused). All this is a preparation to remove predefined file size limit
(CONFIG_SYS_DFU_MAX_FILE_SIZE) for DFU read/write operations.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-01-29 18:30:33 +01:00
Tom Rini
e7ab1cb3f0 Merge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for 2020.04
- updates the Designware I2C driver
  - get timings from device tree
  - handle units in nanoseconds
  - make sure that the requested bus speed is not exceeded
  - few smaller clean-ups
- adds enums for i2c speed and update drivers which use them
- global_data: remove unused mxc_i2c specific field
2020-01-29 09:34:13 -05:00
Tom Rini
3e12744a90 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung
- Various exynos fixes
2020-01-28 21:10:32 -05:00
Tom Rini
86e42b3629 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- spi cs accessing slaves (Bin Meng)
- spi prevent overriding established bus (Marcin Wojtas)
- support speed in spi command (Marek Vasut)
- add W25N01GV spinand (Robert Marko)
- move cadence_qspi to use spi-mem (Vignesh Raghavendra)
- add octal mode (Vignesh Raghavendra)
2020-01-27 19:57:13 -05:00
Martin Fuzzey
7ae22d8479 power: regulator: add driver for Dialog DA9063 PMIC
Add a driver for the regulators in the the DA9063 PMIC.

Robert Beckett: move regulator modes to header so board code can set
modes. Correct mode mask used in ldo_set_mode.
Add an option CONFIG_SPL_DM_REGULATOR_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27 19:54:20 -05:00
Martin Fuzzey
483880c490 power: pmic: add driver for Dialog DA9063 PMIC
This adds the basic register access operations and child regulator
binding (if a regulator driver exists).

Robert Beckett: simplify accesses by using bottom bit of address as
offset overflow. This avoids the need to track which page we are on.
Add an option CONFIG_SPL_DM_PMIC_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27 19:54:20 -05:00
Ian Ray
e1d26a7642 rtc: s35392a: encode command correctly
The 3-bit "command", or register, is encoded within the device address.
Configure the device accordingly, and pass command in DM I2C read/write
calls correctly.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-27 19:54:20 -05:00
Vignesh Raghavendra
daa9405d7c spi: cadence-qspi: Add compatible for TI AM654
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
0f247848b6 spi: cadence-qspi: Add support for Cadence Octal SPI controller
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
658df8bd94 mtd: spi-nor-core: Add octal mode support
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
ffab212123 spi: cadence-qspi: Add direct mode support
Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.

For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
d640772021 spi: cadence_qspi: Move to spi-mem framework
Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.

Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Robert Marko
370d33bc8c mtd: spinand: winbond: Add support for W25N01GV
Linux has supported W25N01GV for a long time, so lets import it.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Vignesh Raghavendra
5502c88e67 spi: ti_qspi: Add support for CS other than CS0
Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0

Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Marcin Wojtas
f7dd537098 spi: prevent overriding established bus settings
The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.

The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.

This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-27 22:27:22 +05:30
Bin Meng
7bacce524d dm: spi: Check cs number before accessing slaves
Add chip select number check in spi_find_chip_select().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
2020-01-27 22:27:21 +05:30
Michael Walle
383fded70c spi: nxp_fspi: new driver for the FlexSPI controller
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.

The port was straightforward:
 - remove the interrupt handling and the completion by busy polling the
   controller
 - remove locks
 - move the setup of the memory windows into claim_bus()
 - move the setup of the speed into set_speed()
 - port the device tree bindings from the original fspi_probe() to
   ofdata_to_platdata()

There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.

This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-01-27 22:27:21 +05:30
Tom Rini
051e03c0d7 Merge tag 'u-boot-clk-26Jan2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Various clock fixes and enhancements
2020-01-27 07:19:26 -05:00
Simon Glass
2034f6c27f i2c: designware_i2c: Do more in the probe() method
Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:25:00 +01:00
Simon Glass
23ad52ebb1 i2c: designware_i2c: Separate out the speed calculation
We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.

Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:24:44 +01:00
Simon Glass
a8d2b515f9 i2c: designware_i2c: Move dw_i2c_speed_config to header
This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:24:29 +01:00
Simon Glass
d96440d1e3 i2c: designware_i2c: Add support for fast-plus speed
Fast-plus runs at 1MHz and is used by some devices. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:24:17 +01:00
Simon Glass
f3d461521a i2c: Update drivers to use enum for speed
Convert the obvious uses of i2c bus speeds to use the enum.

Use livetree access for code changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:24:02 +01:00
Simon Glass
b0a22d0fa9 i2c: stm32: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:23:42 +01:00
Simon Glass
4bef53684f i2c: omap: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:23:26 +01:00
Simon Glass
ab723b7781 i2c: kona_i2c: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:23:10 +01:00
Simon Glass
54290c666e i2c: designware_i2c: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:53 +01:00
Simon Glass
642400ced6 i2c: ast_i2c: Update to use standard enums for speed
Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:41 +01:00
Simon Glass
96fe11c3da i2c: designware_i2c: Add spike supression
Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:22:01 +01:00
Simon Glass
e71b6f6622 i2c: designware_i2c: Rewrite timing calculation
At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.

Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than writing it in code.

The function works by calculating the 'period' of each bit on the bus in
terms of the input clock to the controller (IC_CLK). It makes sure that
the constraints are met and that the different components of that period
add up correctly.

This code was taken from coreboot which has ended up with this same
driver, but now in a much-different form.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:21:51 +01:00
Simon Glass
31adb873e7 i2c: designware_i2c: Put hold config in a struct
Create a struct to hold the three timing parameters. This will make it
easier to move these calculations into a separate function in a later
patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:21:36 +01:00
Simon Glass
d22409e2dc i2c: designware_i2c: Drop scl_sda_cfg parameter
Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in
the driver's private data, from which the function can obtain that
information. This allows the function to have access to the full state of
the driver.

Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-27 07:21:20 +01:00
Simon Glass
80a03db4f3 i2c: designware_i2c: Read device-tree properties
The i2c controller defines a few timing properties. Read these in and
store them for use by the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:21:05 +01:00
Simon Glass
dd3c1602cf i2c: designware_i2c: Use an accurate bus clock instead of MHz
At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.

This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.

Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.

Update the bus speed code to work in KHz instead of MHz, which removes
most of the error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:20:27 +01:00
Simon Glass
65190d15ef i2c: designware_i2c: Use an enum for selected speed mode
Group these #defines into an enum to make it easier to understand the
relationship between them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:19:13 +01:00
Simon Glass
6db7943b92 i2c: designware_i2c: Rename 'max' speed to 'high' speed
Some SoCs support a higher speed than what is currently called 'max' in
this driver. Rename it to 'high' speed, which is the official name of the
3.4MHz speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:19:00 +01:00
Simon Glass
afb88651a6 i2c: designware_i2c: Include clk.h in the header file
We use struct clk here so really should include this header file to avoid
build errors. Also switch the order of clk.h in the C file to match the
required code style.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:18:46 +01:00
Simon Glass
25eb0fb667 i2c: designware_i2c: Don't allow changing IC_CLK
If a different input clock is required then the correct way to do this is
with a clock driver. Don't allow boards to override IC_CLK.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:18:32 +01:00
Simon Glass
0fd05c9dcf i2c: designware_i2c: Add more registers
Some versions of this peripherals provide more control of the bus
behaviour. Add definitions for these registers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Jun Chen <ptchentw@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-01-27 07:18:17 +01:00
Giulio Benetti
041b06a7c3 clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 21:57:08 +01:00
Giulio Benetti
d37ecaba88 clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()
Guard 'mfd==0' to prevent 'divide by zero' issue in
clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd
should never be 0 at all.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 21:57:08 +01:00
Giulio Benetti
3391e77729 clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()
Guard 'parent_rate==0' to prevent 'divide by zero' issue in
clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 21:57:08 +01:00
Angelo Durgehello
c05b38df47 common: fix regression on block cache init
m68k needs block cache list initialized after relocation.
Other architectures must not be involved.

Fixing regression related to:

commit 1526bcce0f
	("common: add blkcache init")

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-26 13:36:14 -05:00
Joel Johnson
080dbc64fc arm: mvebu: fix A38x breakage from commit bb872dd930
This function parameter usage of load_addr was incorrectly caught in
the clarifying renames of commit bb872dd930, which results in boot
failures on Marvell A38x.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Patch-to: Simon Glass <sjg@chromium.org>
2020-01-26 13:36:07 -05:00
Tom Rini
0b23b0d9f9 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Libre Computer ALL-H3-IT/ALL-H5-CC board (Chen-Yu Tsai)
- Allwinner R40 Ethernet, usb phy enablement (Andre Przywara)
- Sunxi auto load from 128KB MMC offset (Andre Przywara)
- Orange Pi Win Ethernet phy enablement (Jernej Skrabec)
2020-01-26 12:05:11 -05:00
Sean Anderson
90cbfa50c2 clk: Fix error checking of dev_read_addr_ptr
dev_read_addr_ptr returns NULL on error, not FDT_ADDR_T_NONE.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-26 12:03:06 +01:00
Giulio Benetti
efbdad3838 clk: uclass: clk_get_by_name() must not be available if CONFIG_OF_PLATDATA is enabled
clk_get_by_name() requires clk_get_by_id() that is not available if
CONFIG_OF_PLATDATA is defined, so move clk_get_by_name() into #else
condition of #if CONFIG_IS_ENABLED(OF_PLATDATA).

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-26 12:03:06 +01:00
Peng Fan
5dcac2b9b3 clk: show more error info when uclass_get_device_by_name
It will ease debug when uclass_get_device_by_name failed with
more error info printed out.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-26 12:03:06 +01:00
Fabien Parent
832685f07c clk: mediatek: use unsigned type for returning the clk rate
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.

This commit change the return type of mtk_clk_find_parent_rate to
ulong.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2020-01-26 12:03:06 +01:00
Tom Rini
40521a6c90 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a,
ls1088a platforms:
- lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes
2020-01-25 12:20:51 -05:00
Angelo Durgehello
1526bcce0f common: add blkcache init
On m68k, block_cache list is relocated, but next and prev list
pointers are not adjusted to the relocated struct list_head address,
so the first iteration over the block_cache list hangs.

This patch initializes the block_cache list after relocation.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2020-01-25 12:04:36 -05:00
Vignesh Raghavendra
5cde44e12a net: macb: Drop local cache flush
Now that arch specific dma mapping APIs take care of cache
flush/invalidate, drop local cache flush operation.
While at that fix dma_unmap_single() call to match new prototype

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-01-25 12:04:36 -05:00
Vignesh Raghavendra
6fff562baf mtd: denali: Drop custom dma mapping functions
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-25 12:04:36 -05:00
Vignesh Raghavendra
eaa8b04da3 mmc: tmio-common: Drop custom dma mapping functions
Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementation

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-25 12:04:36 -05:00
mingming lee
1fdbad021f fastboot: mt85xx: add command to flash/erase emmc hwpart
This patch includes the following:
1. Add fastboot command to erase the whole EMMC_USER
2. Add fastboot command to flash image at EMMC_BOOT1
3. Add fastboot command to erase the whole EMMC_BOOT1
4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-25 12:04:36 -05:00
mingming lee
7d017d607e usb: musb-new: mt85xx: add musb-new gadget driver.
Using musb-new structure for mt85xx gadget driver.
Add gadget driver dts for mt8518 SoCs.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-25 12:04:36 -05:00
Heinrich Schuchardt
94a8e83a60 crypto: make mod_exp_sw() static
Function mod_exp_sw() is only used via the operators of the uclass.
It is not defined in any include.

Make mod_exp_sw() static.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-01-25 12:04:36 -05:00
Heinrich Schuchardt
1611235b85 lib: Kconfig dependencies for pseudo-random library
drivers/rng/sandbox_rng.c requires rand() to be defined but configuration
option CONFIG_CONFIG_LIB_RAND selected in drivers/rng/Kconfig does not
exist.

test/lib/test_aes.c requires rand() to be defined.

Fix the selection criteria for choice "Pseudo-random library support type".

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-01-25 12:04:36 -05:00
Andre Przywara
a2f729f49b phy: sun4i-usb: Add Allwinner R40 support
Since every Allwinner USB PHY seems to be slightly different from each
other, we need to add the compatible string and the respective data
structure to make it work on the R40/V40 SoC.
Nothing spectacular this time, just one less USB controller than the H3.
Copied from the Linux kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-24 23:06:50 +05:30
Simon Glass
29a4a9f105 common: Move hang() to the same header as panic()
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-24 23:06:49 +05:30
Simon Glass
91527c9a30 common: Move RAM-sizing functions to init.h
These functions relate to memory init so move them into the init
header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:49 +05:30
Simon Glass
f32934916c common: Rename and move source()
This function has a very generic name which does not adequately describe
its purpose. Rename it and move it to image.h, since it relates to reading
a script from an image.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:49 +05:30
Simon Glass
ea188950af common: Move the image globals into image.h
These three globals relate to image handling. Move them to the image
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:49 +05:30
Simon Glass
e7f0ec09a0 image: Rename load_addr, save_addr, save_size
These global variables are quite short and generic. In fact the same name
is more often used locally for struct members and function arguments.

Add a image_ prefix to make them easier to distinguish.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:49 +05:30
Simon Glass
657afb14a0 common: Move reset_cpu() to the CPU header
Move this function out of common.h and into a relevant header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:49 +05:30
Simon Glass
98c338bcb6 common: Move get_tbclk() to time.h
This function related to timer and most of the timer functions are in
time.h, so move this function there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:49 +05:30
Simon Glass
b63ff2ae54 common: Move clock functions into a new file
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:48 +05:30
Simon Glass
cc3ac11d81 common: Move ll_boot_init() to init.h
This is an init-related function so belongs in that file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:48 +05:30
Simon Glass
f9aaf98451 common: Drop floppy disk support
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-24 23:06:48 +05:30
Patrik Dahlström
1c16606aac serial: ns16550: Use old baud rate divisor for flushing if not given
If baud_divisor is not set (i.e. == -1), we should use the baud divisor
already in use for flushing the xmit register. If we don't flush the
xmit register, then SPL will hang.

Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
2020-01-24 11:19:52 -05:00
Fabien Dessenne
83b539cfd4 remoteproc: elf_loader: fix program header parsing
Fix an issue where some sections are never loaded : if p_type is
different from PT_LOAD the phdr pointer must be incremented.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Suman Anna <s-anna@ti.com>
2020-01-24 11:19:52 -05:00
Alex Marginean
b8e4eec79c drivers: net: fsl_enetc: fix SXGMII MAC configuration
Separate MAC and serdes configuration, MAC configuration must be applied
at each enetc_start() as FLR clears it.
This restores traffic for ENETC interfaces in USXGMII mode.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Wasim Khan
9c2969e92c pci: layerscape: device tree fixup based on SoC and
lx2160a rev1 requires layerscape_gen4 device tree fixup and
lx2160a rev2 requires layerscape device tree fixup.
Add device tree fixup for lx2160a based on SoC and Version.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Wasim Khan
d20eb7a6db pci: layerscape: Move streamId allocation to common device tree fixup
Move streamId allocation to layerscape common device tree fixup.
Calculate streamId based on SoC variant.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Wasim Khan
1185b229cc pci: layerscape: Common device tree fixup for NXP SoCs
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Michael Walle
42c66f057f drivers: net: fsl_enetc: add write_hwaddr() for LS1028A
The LS1028A SoC is special in the handling of the MAC addresses. We need
to write to the IERB version of the PSIPMAR0/1 register. This value will
be sampled into the corresponding port PSIPMAR0/1 register if the PCI
memory access is enabled.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Michael Walle
ee5c70b8f7 drivers: net: fsl_enetc: use write_hwaddr()
Intead of setting the MAC address in enetc_start() use the proper
write_hwaddr(). U-Boot takes care of the random MAC address, too.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Hou Zhiqiang
282d992e1a pci: layerscape: Fix the BARs disable function
There is not any difference for disabling BARs in RC mode
between PCIe controllers with and without SRIOV.

Fixes: 80afc63fc3 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Hou Zhiqiang
f8203e3bb5 pci: layerscape: Fix the disabling of Expansion ROM BAR
The software will still get non-zero Expansion ROM BAR size
even when the BAR_EN bit is cleared. The BAR_EN bit of
register EXP_ROM_BAR_MASK_RC is not working as expected,
so this patch changes to mask all the bits.

Fixes: 80afc63fc3 ("pci: layerscape: add pci driver based on DM")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Alex Marginean
9c2aee1b19 drivers: net: fsl_enetc: Pass on primary MAC address to Linux
Passes on the primary address used by u-boot to Linux. The code does a DT
fix-up for ENETC PFs and sets the primary MAC address in IERB. The address
in IERB is restored on ENETC PCI functions at FLR.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-24 14:28:26 +05:30
Philippe Reynes
17f34ca803 gpio: bcm6345: allow to use this driver on arm bcm68360
This IP is also used on some arm SoC, so we allow to
use it on arm bcm68360 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-23 07:29:58 -05:00
Philippe Reynes
5602e21ca7 led: bcm6858: allow to use this driver on arm bcm68360
This IP is also used on some arm SoC, so we allow to
use it on arm bcm68360 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-23 07:29:58 -05:00
Philippe Reynes
1453301122 nand: brcmnand: add bcm68360 support
This adds the nand support for chipset bcm68360.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-23 07:29:58 -05:00
Philippe Reynes
34fdacb07b spi: bcm63xx-hsspi: allow to use this driver on arm bcm68360
This IP is also used on some arm SoC, so we allow to
use it on arm bcm68360 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-23 07:29:58 -05:00
Philippe Reynes
d0edec667f watchdog: bcm6345: allow to use this driver on arm bcm68360
This IP is also used on some arm SoC, so we allow to
use it on arm bcm68360 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-23 07:29:58 -05:00
Marek Szyprowski
e27108c433 mmc: s5p_sdhci: Read generic MMC properties from DT
Read generic MMC properties from device-tree. This allows to specify for
example cd-inverted property and let MMC core to properly handle such
case.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2020-01-23 11:43:10 +09:00
Stephan Gerhold
057b613990 timer: Add driver for Nomadik Multi Timer Unit (MTU)
The Nomadik Multi Timer Unit (MTU) provides 4 decrementing
free-running timers. It is used in ST-Ericsson Ux500 SoCs.

The driver uses the first timer to implement UCLASS_TIMER.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-22 17:47:56 -05:00
Tom Rini
75dd53055a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Clearfog: Add run-time board detection with TLV EEPROM support
  (Baruch)
2020-01-21 18:10:28 -05:00
Baruch Siach
d67b98ed47 ddr: marvell: a38x: allow board specific clock out setup
DDR clock out might be unrelated to the number of active chip-select.
For example, the board might have two DDR components, but only one
chip-select. The clk_enable mask allows the board to enable DDR clocks
regardless of active chip-selects.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-01-21 08:31:49 +01:00
Tom Rini
07add22cab Merge tag '2020-01-20-ti-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodes

K3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA support

DRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/ti

AM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
2020-01-20 14:54:55 -05:00
Lokesh Vutla
ea67b26e3f clk: sci-clk: add slack to clk-set-rate passed to firmware
Add slack to the clock frequency parameters passed to firmware within
clk_set_rate. min-freq is changed to 0 and max-rate is changed to
ULONG_MAX. This fixes certain issues with pll clock rounding when the
firmware is not able to set the frequency exactly to the target, the
current implementation fails if the available frequency is even 1Hz off
the target. With the change, the firmware still tries its best to set
the frequency as close as possible to the target.

Reported-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:29 +05:30
Vignesh Raghavendra
779f40bf52 phy: omap-usb2-phy: Add support for AM654 USB2 PHY
AM654 SoC has USB2 PHY which is similar to existing USB2 PHYs on OMAP
SoCs. Add support for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:29 +05:30
Vignesh Raghavendra
d35f2cfa5b phy: omap-usb2-phy: Fix warnings when built for ARM64
Below warning is seen when this driver is built for devices with 64 bit
physical address space.

drivers/phy/omap-usb2-phy.c: In function ‘omap_usb2_phy_probe’:
drivers/phy/omap-usb2-phy.c:187:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
   priv->phy_base = (void *)base;
                    ^
Fix this by using dev_read_addr_ptr() instead of dev_read_addr().

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:29 +05:30
Vignesh Raghavendra
cab4e275dd dwc3-generic: Add support for AM654 USB controller
AM654 has DWC3 USB controller that is very similar to other TI SoCs. Add
a new compatible to enable the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:29 +05:30
Keerthy
17aaa42e76 power: regulator: tps62360_regulator: Convert ofdata_to_platdata to the missing probe
commit 29f7d05a34 ("dm: core: Move ofdata_to_platdata() call earlier")
introduces changes in the order of device_probe execution.
ofdata_to_platdata now comes before the probe function which resulted in
a deadlock and caused boot hang on AM6 devices.

Deadlock sequence: tps62360_regulator_ofdata_to_platdata --> i2c_get_chip
--> device_probe(tps62360) --> tps62360_regulator_ofdata_to_platdata

Hence convert ofdata_to_platdata to the missing probe function to fix the
hang.

Fixes: 22e8f18980 ("power: regulator: tps6236x: add support for tps6236x regulators")
Signed-off-by: Keerthy <j-keerthy@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Faiz Abbas
a20008eabd mmc: am654_sdhci: Add Support for configuring PHY in J721e
Add Support for writing to PHY registers for J721e. There are number of
differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY.
Create a driver_data structure with an ops and flags field and use the
flags field to indicate these differences. The differences are as
follows:

1. The J721e 4 bit instance PHY does not have a DLL. Introduce a
DLL_PRESENT flag to make sure that DLL related registers are accessed
only where they are present. Also add a separate set_ios_post()
callback.

2. The J721e 8 bit instance is not muxed with anything else inside the
SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is
used to indicate the presence of this field.

3. The register field used to select DLL frequency is 3 bit wide in
J721e as compared to 2 bits in AM65x. Add another flag that
distinguishes these fields.

4. The strobe select field is 8 bit wide as compared to 4 bit wide for
AM65x. Add yet another flag to indicate this difference. Strobe select
is used only for HS400 speed mode, support for which has not been added
in AM65x.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Faiz Abbas
fe0e30c7ba mmc: am654_sdhci: Get Xin clock by name
Get clk_xin by name instead of by index to avoid having to put clocks in
the same order in all devices.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
f03cb5c9e5 dma: ti: k3-udma: Fix build warnings when building for 32 bit platforms
Cast pointers properly so as to avoid warnings when driver is built for
32 bit platforms

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
b0ab00839f dma: ti: k3-udma: Fix ring push operation for 32 bit cores
UDMA always expects 64 bit address pointer of the transfer descriptor in
the Ring. But on 32 bit cores like R5, pointer is always 32 bit in size.
Therefore copy over 32 bit pointer value to 64 bit variable before
pushing it over to the ring, so that upper 32 bits are 0s.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
ce1a307358 dma: ti: k3-udma: Switch to exposed ring mode
Exposed ring mode works well with 32 bit and 64 bit cores without need
for Proxies for 32 bit cores. Therefore switch to exposed ring mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
c16cdd4247 dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfers
Fix up the debug prints that were dumping state of TCHAN RT registers to
use tchan for MEM_TO_DEV transfers.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
c0b9490304 dma: ti: k3-udma: Remove coherency check for cache ops
Remove redundant coherency checks before calling cache ops in UDMA
driver. This is now handled in arch specific cache operation
implementation based on Kconfig option

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
ec0aeacf0b soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle
Instead of looking getting reference to SYSFW device using name which
is not guaranteed to be constant, use phandle supplied in the DT node to
get reference to SYSFW

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
9d32a94bce soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop
Flush caches when pushing an element to ring and invalidate caches when
popping an element from ring in Exposed Ring mode. Otherwise DMA
transfers don't work properly in R5 SPL (with caches enabled) where the
core is not in coherency domain.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Vignesh Raghavendra
a8837cf438 dma: ti: k3-udma: Query DMA channels allocated from Resource Manager
On K3 SoCs, DMA channels are shared across multiple entities, therefore
U-Boot DMA driver needs to query resource range from centralised
resource management controller i.e SystemFirmware and use DMA channels
allocated for A72 host. Add support for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Faiz Abbas
2695584a5c thermal: ti-bandgap: Fix adc value datatype
The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to
be indexed into a lookup table to get the actual temperature. Fix the
naming and datatype of the adc value variable.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Simon Glass
db41d65a97 common: Move hang() to the same header as panic()
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17 17:53:40 -05:00
Simon Glass
9b4a205f45 common: Move RAM-sizing functions to init.h
These functions relate to memory init so move them into the init
header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:35 -05:00
Simon Glass
220a3a44a3 common: Rename and move source()
This function has a very generic name which does not adequately describe
its purpose. Rename it and move it to image.h, since it relates to reading
a script from an image.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:35 -05:00
Simon Glass
8e8ccfe1aa common: Move the image globals into image.h
These three globals relate to image handling. Move them to the image
header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:35 -05:00
Simon Glass
bb872dd930 image: Rename load_addr, save_addr, save_size
These global variables are quite short and generic. In fact the same name
is more often used locally for struct members and function arguments.

Add a image_ prefix to make them easier to distinguish.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:35 -05:00
Simon Glass
9a3b4ceb37 common: Move reset_cpu() to the CPU header
Move this function out of common.h and into a relevant header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:31 -05:00
Simon Glass
049f8d6f4a common: Move get_tbclk() to time.h
This function related to timer and most of the timer functions are in
time.h, so move this function there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:30 -05:00
Simon Glass
d96c26040e common: Move clock functions into a new file
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:29 -05:00
Simon Glass
35a3f871fc common: Move ll_boot_init() to init.h
This is an init-related function so belongs in that file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:28 -05:00
Simon Glass
015e3348fc common: Drop floppy disk support
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:26:50 -05:00
Tom Rini
d7bb6aceb2 Merge tag 'mmc-1-16-2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- Cleanup of fsl_esdhc driver together with arch/defconfig change
- Add quirk for APP_CMD retry
2020-01-16 13:20:51 -05:00
Tom Rini
92329e2413 Xilinx/FPGA changes for v2020.04
ARM64:
 - Add INIT_SPL_RELATIVE dependency
 
 SPL:
 - FIT image fix
 - Enable customization of bl2_plat_get_bl31_params()
 
 Pytest:
 - Add test for octal/hex conversions
 
 Microblaze:
 - Fix manual relocation for one SPI instance
 
 Nand:
 - Convert zynq/zynqmp drivers to DM
 
 Xilinx:
 - Enable boot script location via Kconfig
 - Support OF_SEPARATE in board FDT selection
 - Remove low level uart setup it is done later by code
 - Add support for DEVICE_TREE variable passing for SPL
 
 Zynq:
 - Enable jtag boot mode via distro boot
 - Removing unused baseaddresses from hardware.h
 - DT fixups
 
 ZynqMP:
 - Fix emmc boot sequence
 - Simplify spl logic around bss and board_init_r()
 - Support psu_post_config_data() calling
 - Tune mini-nand DTS
 - Fix psu wiring for a2197 boards
 - Add runtime MMC device boot order filling in spl
 - Clear ATF handoff handling with custom bl2_plat_get_bl31_params()
 - Add support u-boot.its generation
 - Use single image configuration for all platforms
 - Enable PANIC_HANG via Kconfig
 - DT fixups
 - Firmware fixes
 - Add support for zcu208 and zcu1285
 
 Versal:
 - Fix emmc boot sequence
 - Enable board_late_init() by default
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 IX3VAJ41GJXBwP7Z9hX9RFhsqOu0M+NdegCdFvMUaCQ1bSvgAMOnDL+JeB21+Qo=
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Merge tag 'xilinx-for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.04

ARM64:
- Add INIT_SPL_RELATIVE dependency

SPL:
- FIT image fix
- Enable customization of bl2_plat_get_bl31_params()

Pytest:
- Add test for octal/hex conversions

Microblaze:
- Fix manual relocation for one SPI instance

Nand:
- Convert zynq/zynqmp drivers to DM

Xilinx:
- Enable boot script location via Kconfig
- Support OF_SEPARATE in board FDT selection
- Remove low level uart setup it is done later by code
- Add support for DEVICE_TREE variable passing for SPL

Zynq:
- Enable jtag boot mode via distro boot
- Removing unused baseaddresses from hardware.h
- DT fixups

ZynqMP:
- Fix emmc boot sequence
- Simplify spl logic around bss and board_init_r()
- Support psu_post_config_data() calling
- Tune mini-nand DTS
- Fix psu wiring for a2197 boards
- Add runtime MMC device boot order filling in spl
- Clear ATF handoff handling with custom bl2_plat_get_bl31_params()
- Add support u-boot.its generation
- Use single image configuration for all platforms
- Enable PANIC_HANG via Kconfig
- DT fixups
- Firmware fixes
- Add support for zcu208 and zcu1285

Versal:
- Fix emmc boot sequence
- Enable board_late_init() by default
2020-01-16 09:45:40 -05:00
Sam Shih
25273dbd57 mmc: add mmc and sd support for MT7622
This patch add mmc and sd support for Mediatek MT7622 SoCs

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
abb65f123c power: domain: add power domain support for MT7622
This patch add power domain support for Mediatek MT7622 SoCs

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
d8588ba55f clk: mediatek: fix clock-rate overflow problem
This patch fix clock-rate overflow problem in mediatek
clock driver common part.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
72ab603b20 clk: mediatek: add driver for MT7622
This patch add clock driver for MediaTek MT7622 SoC.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
cf400b63b4 pinctrl: mediatek: add support for different pinctrl
Due to the pinctrl hardware of MT7622 is difference from others
SoC which using the common part of mediatek pinctrl.
So we need to modify the common part of mediatek pinctrl.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Sam Shih
a430149c99 pinctrl: mediatek: add driver for MT7622
This patch add Pinctrl driver for MediaTek MT7622 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
ce0069ed95 phy: phy-mtk-tphy: make ref clock optional
If make the ref clock optional, no need refer to fixed-clock when
the ref clock is always on or comes from oscillator directly.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
3b6351a475 phy: phy-mtk-tphy: remove the check of -ENOSYS
No need check -ENOSYS anymore after add dummy_enable() for
fixed-clock.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
6bf6d81c11 clk: fixed_rate: add dummy enable() function
This is used to avoid clk_enable() return -ENOSYS.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
d646420e29 clk: add APIs to get (optional) clock by name without a device
Sometimes we may need get (optional) clock without a device,
that means use ofnode.
e.g. when the phy node has subnode, and there is no device created
for subnode, in this case, we need these new APIs to get subnode's
clock.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
bd7c798605 clk: check valid clock by clk_valid()
Add valid check for clk->dev, it's useful when get optional
clock even when the clk point is valid, but its dev will be
NULL.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
0f9b2b3ddf clk: fix error check for devm_clk_get_optional()
If skip all return error number, it may skip some real error cases,
so only skip the error when the clock is not provided in DTS

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Chunfeng Yun
5f82a940a0 clk: mediatek: mt7629: add support for ssusbsys
The SSUSB IP's clocks come from ssusbsys module on mt7629,
so add its driver

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
fb80eaa9d8 mmc: mtk-sd: fix hang when data read quickly
For CMD21 tuning data, the 128/64 bytes data may coming in very
short time, before msdc_start_data(), the read data has already
come, in this case, clear MSDC_INT will cause the interrupt disappear
and lead to the thread hang.

the solution is just clear all interrupts before command was sent.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
3b0397d48b mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
51fcd56c0d pinctrl: mediatek: add driver for MT8512
Add Pinctrl driver for MediaTek MT8512 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
mingming lee
0670adb27a clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
2020-01-16 09:39:45 -05:00
mingming lee
f62168d3c3 clk: mediatek: add set_clr_upd mux type flow
Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
2020-01-16 09:39:45 -05:00
mingming lee
c196110777 clk: mediatek: add driver support for MT8512
Add clock driver for MediaTek MT8512 SoC, include topckgen,
apmixedsys and infracfg support.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2020-01-16 09:39:45 -05:00
Joel Johnson
26632b7541 mmc: config help typo fix
Fix typo in description of MMC_QUIRKS config option.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
2020-01-16 13:21:01 +08:00
Joel Johnson
d4a5fa314d mmc: add additional quirk for APP_CMD retry
It was observed (on ClearFog Base) that sending MMC APP_CMD returned
an error on the first attempt. The issue appears to be timing related
since even inserting a puts() short debug entry before the execution
added sufficient delay to receive success on first attempt.

Follow the existing quirks pattern to retry if initial issuance
failed so as to not introduce any delay unless needed.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
2020-01-16 13:21:01 +08:00
Yangbo Lu
f1bce08426 Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage
The eSDHC reference clocks should be provided by speed.c in arch/.
And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to
select which clock to use. Because we can make the driver to select
the periperhal clock which is better (provides higher frequency)
automatically if its value is provided by speed.c.

This patch is to drop this option and make driver to select clock
automatically. Also fix peripheral clock calculation issue in
fsl_lsch2_speed.c/fsl_lsch3_speed.c.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:20:33 +08:00
Yangbo Lu
7fdcbac5d6 mmc: fsl_esdhc: drop useless fdt fixup
The fdt fixup for properties "peripheral-frequency" and "adapter-type"
was once for a Freescale SDK release. The properties haven't been existed
in linux mainline. Drop these useless code.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:16:24 +08:00
Yangbo Lu
6982315adf mmc: fsl_esdhc_imx: drop QorIQ eSDHC specific peripheral clock code
Drop QorIQ eSDHC specific peripheral clock code.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:16:23 +08:00
Sean Anderson
327bb3bc1e Add dependencies for MALLOC_F and OF_LIBFDT
Some features implicitly depended on MALLOC_F and OF_LIBFDT and would
fail at link-time if these features were not enabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-01-15 19:50:31 -05:00
Vignesh Raghavendra
74326a320a Kconfig: Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA
Rename CONFIG_SPL_DMA_SUPPORT to CONFIG_SPL_DMA. This allows to use
macros such as CONFIG_IS_ENABLED() that allow conditional compilation of
code for SPL and U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-15 19:50:27 -05:00
Giulio Benetti
6a63a873b7 mmc: fsl_esdhc: add compatible for fsl, imxrt-usdhc
Add compatible "fsl,imxrt-usdhc" to make mmc working on i.MXRT platforms
with CONFIG_DM_MMC=y.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:54:00 +01:00
Giulio Benetti
a820bedc45 mmc: fsl_esdhc: make if(CONFIG_IS_ENABLED(CLK)) an #if statement
Not all architectures(i.e. i.MXRT) support mxc_get_clock() and use DM_CLK
instead. So building could result in failure due to missing
mxc_get_clock().

Make if(CONFIG_IS_ENABLED(CLK)) an #if statement.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:54:00 +01:00
Giulio Benetti
cd647fc4fb ram: add SDRAM driver for i.MXRT SoCs
Add SDRAM driver for i.MXRT SoCs.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:54:00 +01:00
Giulio Benetti
c32449a161 serial_lpuart: add support for i.MXRT
Add i.MXRT compatible string and cpu type support to lpuart driver,
to use little endian 32 bits configurations.

Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART
FIFO register is bit 3, so this definition should change to 0x08 as done
for i.MX8. It needs also to set baudrate the same way as i.MX8 does.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:54:00 +01:00
Giulio Benetti
55631db8bd serial_lpuart: add clock enable if CONFIG_CLK is defined
This driver assumes that lpuart clock is already enabled before probing
but using DM only lpuart won't be automatically enabled so add
clk_enable() when probing if CONFIG_CLK is defined. If clock is not
found, because DM is not used, let's emit a warning and proceed, because
serial clock could also be already enabled by non DM code. If clock is
found but cna't be enabled then return with error.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:54:00 +01:00
Giulio Benetti
abd98e05a2 gpio: mxc_gpio: add support for i.MXRT1050
Add i.MXRT1050 support, there are 5 GPIO banks.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
916ce98127 pinctrl: add i.MXRT driver
Add i.MXRT pinctrl driver.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
4ca28e98ac clk: imx: add i.IMXRT1050 clk driver
Add i.MXRT1050 clk driver support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
824c371f9b clk: imx: pfd: add set_rate()
Implement set_rate() for pfd.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
efadf790f3 clk: imx: pllv3: add support for PLLV3_AV type
Add support for PLLV3 AV type.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
d0ceb93547 clk: imx: pllv3: add PLLV3_SYS support
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping
generic enable()/disable(). Add a different driver because ops are
different respect to GENERIC/USB.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
9841fee581 clk: imx: pllv3: add set_rate() support
Add generic set_rate() support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
cbb20014a3 clk: imx: pllv3: add disable() support
Add disable() support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
f4b7094250 clk: imx: pllv3: add enable() support
Before set_rate() pllv3 needs enable() to power the pll up.
Add enable() taking into account different power_bit and
different powerup_set, because some pll needs its power_bit to be
set or reset to be powered on.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Giulio Benetti
4abd8076c8 clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB
div_mask is different for GENERIC and USB pll, so set it according.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Giulio Benetti
16faa599e6 clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks
Better to register the 2 clock as 2 different drivers because they work
slightly differently depending on power_bit and powerup_set bits coming
on next patches.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-01-14 22:53:59 +01:00
Anatolij Gustschin
f35237e1e4 clk: imx8qxp: extend to support getting I2C IPG clock
Since commit d02be21d30 ("i2c: imx_lpi2c: add ipg clk") getting
I2C clocks doesn't work. Add I2C IPG clock IDs to related switch
statements to fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-01-14 22:48:37 +01:00
Fabio Estevam
29230f389d mmc: fsl_esdhc_imx: Handle the "broken-cd" property
When no GPIO is used to read the card detect status the following
error is seen:

MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment

Fix it by handling the "broken-cd" property in the same way
that drivers/mmc/sdhci.c does, which considers that the SD card
is present when the "broken-cd" property is passed.

Tested on a imx6ul-evk board.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-01-14 22:47:15 +01:00
Michal Simek
8af4c4dcbb net: zynq: Add a note about RX_BUF macro
Record note about reducing number of BDs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:55 +01:00
Ashok Reddy Soma
3f9c23905c firmware: Remove probe which is causing extra bind
Remove probe function dm_scan_fdt_dev from zynqmp-firmware driver.
It is just binding its subnode zynqmp-clk.
As a result one extra node is showing up in dm tree.

This is not required, it is anyway bound from it's own zynqmp-clk driver.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:55 +01:00
Ashok Reddy Soma
2507ecf18b zynq: mtd: nand: Remove hardcoded base addresses
Remove hardcoded base addresses of smc controller and nand controller.
Get those addresses from dt and replace wherever they are used.
Remove smc and nand base address from header file too.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:54 +01:00
Ashok Reddy Soma
45397a6ea3 zynq: mtd: nand: Move zynq nand driver to driver model
Move the zynq nand driver to driver model. Select DM_MTD if
zynq nand controller (NAND_ZYNQ) is selected.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:54 +01:00
Ashok Reddy Soma
4d9b1afa41 spi: Fix manual relocation calling more times
When two instances of AXI QSPI with flash are added and tested
simultaneously the spi driver operations are relocated twice.
As a result code is accessing addresses outside of RAM when
relocated second time which is causing a crash.

Tested on Microblaze.

Similar change was done in past by:
commit f238b3f0fb ("watchdog: dm: Support manual relocation for watchdogs")
commit 2588f2ddfd ("dm: sf: Add support for all targets which requires MANUAL_RELOC")
commit 1b4c2aa25b ("gpio: dm: Support manual relocation for gpio")

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:54 +01:00
Ashok Reddy Soma
3dd0f8cccd mtd: nand: Remove hardcoded base address of nand
Remove hardcoded base address of nand and replace it with the
value taken from device tree. Remove base address from header
file too.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:52 +01:00
Ashok Reddy Soma
b014b833bd mtd: nand: Move arasan nand driver to driver model
Make changes to arasan nand driver to move it to driver model.
Select DM_MTD if arasan nand driver is selected.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:52 +01:00
Heinrich Schuchardt
27a38a6e71 virtio: fix typo devicd
%s/devicd/device

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-10 14:18:26 -05:00
Frank Wunderlich
36b8b5d3ad poweroff: add poweroff for mt6323 pmic
this adds poweroff to bananapi r2 / mt7623 / mt6323 pmic

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2020-01-10 10:25:13 -05:00
Han Nandor
0b326fc296 rtc: add support for DS3232 device
DS3232 is an i2c RTC with 236 bytes of battery-backed SRAM.

Add an RTC driver for DS3232 device, which provides time and
date support. Also read and write functions are provided,
which can be used to access the SRAM memory.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
2020-01-10 10:25:13 -05:00
Robert Beckett
ae3d38f318 bootcount: add a DM i2c eeprom backing store for bootcount
This driver allows the use of i2c eeprom device or partition as backing
store for boot counter values with DM enabled.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2020-01-10 10:25:13 -05:00
Angelo Durgehello
48f885ae40 drivers: mcfmii: add dm support
Add specific dm code, but maintaining this driver as is, so more in the
shape of a mii library. Can be moved to dm in a further step.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10 10:25:13 -05:00
Angelo Durgehello
05ffdc85ca drivers: fsl_mcdmafec: conversion to dm
Full conversion to dm for all boards, legacy code removed.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10 10:25:13 -05:00
Angelo Durgehello
a7bcace28a drivers: mcffec: conversion to dm
Full conversion to dm for all boards, legacy code removed.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10 10:25:13 -05:00
Angelo Durgehello
080bcc5cc1 drivers: net: add mcf fec dm Kconfig support
Add ColdFire fec to Kconfig.

Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
2020-01-10 10:25:13 -05:00
Tom Rini
c00bd81ae0 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx
- A small PR with MC8309 fixes from Rasmus.
2020-01-09 13:42:43 -05:00
Tom Rini
d6b92b9742 dm: Increased separation of ofdata_to_platdata() and probe methods
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Merge tag 'dm-pull-8jan20' of git://git.denx.de/u-boot-dm

dm: Increased separation of ofdata_to_platdata() and probe methods
2020-01-09 08:52:21 -05:00
Tom Rini
a74a2134b2 Merge branch 'master' of git://git.denx.de/u-boot-usb
- DFU updates
2020-01-09 08:51:57 -05:00
Tom Rini
7086de4948 Pull request for UEFI sub-system for efi-2020-04-rc1
This pull request provides:
 
 * support for FIT images for UEFI binaries
 * drivers for hardware random number generators
 * an implementation of the EFI_RNG_PROTOCOL
 * a sub-command for efidebug to display configuration tables
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Merge tag 'efi-2020-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-04-rc1

This pull request provides:

* support for FIT images for UEFI binaries
* drivers for hardware random number generators
* an implementation of the EFI_RNG_PROTOCOL
* a sub-command for efidebug to display configuration tables
2020-01-08 18:57:11 -05:00
Tom Rini
deb287b561 ---------------------------------------------------------------------
Add i.MX8MP SoC and EVK board
 Update README for i.MX8MN EVK and fix mmc env
 Add pca9450 driver
 --------------------------------------------------------------------
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
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Merge tag 'u-boot-imx-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

---------------------------------------------------------------------
Add i.MX8MP SoC and EVK board
Update README for i.MX8MN EVK and fix mmc env
Add pca9450 driver
--------------------------------------------------------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/634211885
2020-01-08 15:24:50 -05:00
Tom Rini
ce022f2857 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2020-01-08 15:23:49 -05:00
Tom Rini
9af51fb3a5 - Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
 - Unnecessary header includes drop into video/meson
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Merge tag 'u-boot-amlogic-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
2020-01-08 15:23:37 -05:00
Peng Ma
964b90f61d ata: fsl_sata: Continue probing other sata port when failed current port.
In the initialization of sata driver, we want to initialize all port
 probes, Therefore, any detection failure between of them should continue
 initialization by skipping the current port instead of exit.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
2020-01-08 09:27:44 -05:00
Peng Ma
40cdf26eeb ata: sata_sil: Continue probing other sata port when failed current port.
In the initialization of sata driver, we want to initialize all port
 probes, Therefore, any detection failure between of them should continue
 initialization by skipping the current port instead of exit.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
2020-01-08 09:27:44 -05:00
Peng Fan
c4cc283498 clk: imx: add i.MX8MP clk driver
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:09 +01:00
Peng Fan
6ddde48b49 clk: imx: add imx_clk_mux2_flags
Add imx_clk_mux2_flags which will be used by i.MX8MP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:09 +01:00
Ye Li
22172f6b7f power: Add new PMIC PCA9450 driver
PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:08 +01:00
Peng Fan
4a41a1a6f0 ddr: imx8m: Add DRAM PLL to generate 1000Mhz output
We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:08 +01:00
Peng Fan
67f3f32c6a mxc_ocotp: support i.MX8MP
i.MX8MP use similar ocotp as i.MX8MN, but has changed fuse banks
and ctrl register bit definitions, so update to reflect that.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:08 +01:00
Peng Fan
d8293e984b pinctrl: imx8m: support i.MX8MP
Add i.MX8MP compatible to let the pinctrl driver could support
i.MX8MP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-08 13:20:08 +01:00
Rasmus Villemoes
fddf876a8f mpc83xx_clk: always treat MPC83XX_CLK_PCI as invalid
The current mpc83xx_clk driver is broken for any board for which
mpc83xx_has_pci() is true, i.e. anything not MPC8308:

When is_clk_valid() reports that MPC83XX_CLK_PCI is valid,
init_all_clks() proceeds to call init_single_clk(), but that doesn't
know about either MPC83XX_CLK_PCI or has any handling of the
TYPE_SCCR_ONOFF mode correctly returned by retrieve_mode(). Hence
init_single_clk() ends up returning -EINVAL, and the whole board hangs
in serial_init().

The quickest fix is to simply pretend that clock is invalid for
all, since nobody can have been relying on it. Adding proper support
seems to be a bit more involved than just handling TYPE_SCCR_ONOFF:

- The power-on-reset value of SCCR[PCICM] is 0, so
  mpc83xx_clk_enable() would probably need to be tought to enable the
  clock.

- The frequency of PCI_SYNC_OUT is either SYS_CLK_IN or SYS_CLK_IN/2
  depending on the CFG_CLKIN_DIV configuration input, but that can't
  be read from software, so to properly fill out
  ->speed[MPC83XX_CLK_PCI] I think one would need guidance from
  Kconfig or dtb.

Partially fixes: 07d538d281 clk: Add MPC83xx clock driver

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
2020-01-08 08:14:36 +01:00
Sean Anderson
7fc0c2b187 dm: Add a debug message when devices are skipped pre-reloc
This adds a message to lists_bind_fdt when it skips initializing a device
pre-relocation. I've had a couple errors where a device didn't initialize
properly because one of its dependencies was missing.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-01-07 16:03:01 -07:00
Simon Glass
42a0ce576f dm: devres: Add a new OFDATA phase
Since the ofdata_to_platdata() method can allocate resources, add it as a
new devres phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:39 -07:00
Simon Glass
af68411dd1 dm: devres: Use an enum for the allocation phase
At present we only support two phases where devres can be used:
bind and probe. This is handled with a boolean. We want to add a new
phase (platdata), so change this to an enum.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:39 -07:00
Simon Glass
8d6320cc4d dm: devres: Add tests
The devres functionality has very few users in U-Boot, but it still should
have tests. Add a few basic tests of the main functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:39 -07:00
Simon Glass
cce61fc428 dm: devres: Convert to use logging
At present when CONFIG_DEBUG_DEVRES is enabled, U-Boot prints log messages
to the console with every devres allocation/free event. This causes most
tests to fail since the console output is not as expected.

In particular this prevents us from adding a device to sandbox which uses
devres in its bind method.

Move devres over to use U-Boot's logging feature instead, and add a new
category for devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
153851ddfa dm: core: Add a new flag to track platform data
We want to avoid allocating platform data twice. This could happen if
device_probe() is called after device_ofdata_to_platdata() for the same
device.

Add a flag to track whether device_ofdata_to_platdata() has been called on
a device. Check the flag to make sure it doesn't happen twice, and clear
the flag when the data is freed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
bcd90cb692 dm: core: Export a new function to read platdata
Add a new internal function, device_ofdata_to_platdata() to handle
allocating private space associated with each device and reading the
platform data from the device tree.

Call this new function from device_probe().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
82de42fa14 dm: core: Allocate parent data separate from probing parent
At present the parent is probed before the child's ofdata_to_platdata()
method is called. Adjust the logic slightly so that probing parents is
not done until afterwards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
29f7d05a34 dm: core: Move ofdata_to_platdata() call earlier
This method is supposed to extract platform data from the device tree. It
should be done before the device itself is probed. Move it earlier in the
device_probe() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
a41e6daf05 dm: core: Don't clear active flag twice when probe() fails
Remove this duplicated code, since the 'fail' label does this immediately.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
b2b1100a3b aspeed: ast2500: Read clock ofdata in the correct method
At present the clock driver reads its ofdata in the probe() method. This
is not correct although it is often harmless.

However in this case it causes a problem, something like this:

- ast_get_scu() is called (from somewhere) to get the SCI address
- this probes the clock
   - first sets up ofdata (which does nothing at present)
   - DM marks clock device as active
   - DM calls pinctrl
      - pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
      - ast_get_scu() probes the clock, but sees it already marked as
           probed
      - ast_get_scu() accesses the clock's private data, with scu as NULL
   - DM calls clock probe function ast2500_clk_probe() which reads scu

By putting the read of scu into the correct method, scu is read as part of
ofdata setup, and everything is OK.

Note: This problem did not matter until now since DM always probed all
parents before reading a child's ofdata. The fact that pinctrl is a child
of clock seems to trigger this strange bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-01-07 16:02:38 -07:00
Simon Glass
4886287ee4 pci: Print a warning if the bus is accessed before probing
It is not possible to access a device on a PCI bus that has not yet been
probed, since the bus number is not known. Add a warning to catch this
error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
1058eec0f4 usb: Drop use of BUG_ON() and WARN_ON()
These macros use __FILE__ which inserts the full path of the object file
into U-Boot, thus increasing file size. Drop these usages.

An older version of this patch was submitted here:

http://patchwork.ozlabs.org/patch/1205784/

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Simon Glass
6de16dbe44 dm: core: Use assert_noisy() in devres
Use this macros instead of the linux ones, as the output is smaller.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07 16:02:38 -07:00
Sughosh Ganu
03018ea8fd virtio: rng: Add a random number generator(rng) driver
Add a driver for the virtio-rng device on the qemu platform. The
device uses pci as a transport medium. The driver can be enabled with
the following configs

CONFIG_VIRTIO
CONFIG_DM_RNG
CONFIG_VIRTIO_PCI
CONFIG_VIRTIO_RNG

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-01-07 18:08:21 +01:00
Sughosh Ganu
ff0dada9b8 sandbox: rng: Add a random number generator(rng) driver
Add a sandbox driver for random number generation. Mostly aimed at
providing a unit test for rng uclass.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07 18:08:21 +01:00
Sughosh Ganu
231ec90583 stm32mp1: rng: Add a driver for random number generator(rng) device
Add a driver for the rng device found on stm32mp1 platforms. The
driver provides a routine for reading the random number seed from the
hardware device.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove a superfluous blank line
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-01-07 18:08:21 +01:00
Sughosh Ganu
82ebf0f6a0 clk: stm32mp1: Add a clock entry for RNG1 device
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07 18:08:21 +01:00
Sughosh Ganu
a248768400 dm: rng: Add random number generator(rng) uclass
Add a uclass for reading a random number seed from a random number
generator device.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07 18:08:21 +01:00
Peng Fan
5677fe9d6b power: regulator: support off-on-delay-us
off-on-delay-us has been supported by Linux, so let's use it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-07 11:13:25 -05:00
Fabien Dessenne
33fd41951a remoteproc: stm32: load resource table from firmware
Load the optional resource table from the firmware, and write its
address in the dedicated backup register.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07 11:13:25 -05:00
Fabien Dessenne
4a4deb870f remoteproc: stm32: track the coprocessor state in a backup register
Update the dedicated backup register to track the coprocessor state and
rely on that register to compute the .is_running() value (which expects
a return value of 0 -not 1- if the processor is running).

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07 11:13:25 -05:00
Fabien Dessenne
ffcb880de8 remoteproc: elf_loader: Add elf resource table load support
Add rproc_elf_load_rsc_table(), which searches for a resource table in
an elf64/elf32 image, and if found, copies it to device memory.
Add also the elf32 and elf64 variants of this API.
Add a test for this.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-07 11:13:25 -05:00
Jean-Jacques Hiblot
d42730e8c6 drivers: board: Add get_fit_loadable()
This function will be used by the SPL to get the names of images to load
from the FIT. This allows to load different images based on runtime HW
detection.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07 11:13:24 -05:00
Jean-Jacques Hiblot
8c86f96d20 drivers: board: Make the board drivers available in SPL
Make the board driver available in the SPL too. The board driver is a way
to provide useful information about the board and that can be useful in
the SPL too.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07 11:13:24 -05:00
Tom Rini
d8a3f5259a New for 2020.04
---------------
 
 - New boards
 	Embedded Artists COM board
 	Xea Board
 - Switch to DM:
 	Aristainetos boards
 	Toradex colibri (DM_ETH)
 	iCubox
 	GE bx50v3
 	mx7dsabre (DM_ETH)
 	cx9020
 - New features:
 	Bootaux with elf files
 	Default SYS_THUMB_BUILD for i.MX6/7
 - Fixes:
 	DHCOM i.MX6 PDK
 	Engicam
 	i.MX8M tools (imx8m_image)
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
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Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
2020-01-07 08:45:43 -05:00
Tom Rini
ac0f978afd First set of u-boot-atmel features for 2020.04 cycle
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Merge tag 'u-boot-atmel-2020.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features for 2020.04 cycle

This feature set is a patch series from Tudor Ambarus which includes
parsing of the spi flash SFDP parser for SST flashes, and using those
tables to retrieve unique saved per device MAC address. This is then
used as base mac address on the SAMA5D2 Wireless SOM EK board.
2020-01-07 08:44:56 -05:00
Thor Thayer
8097aee3ab ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access
The ECC registers in the SDRAM HMC Adapter should always
be accessible (both when ECC is enabled and disabled).
Currently, the registers are accessible only when ECC is enabled.

The ECC Enabled bit is used to determine the status of
ECC by later OSes so always allow access.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07 14:38:34 +01:00
Thor Thayer
62079b2211 arm: socfpga: stratix10: Enable SMMU access
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07 14:38:34 +01:00
Ley Foon Tan
6a48c34c25 ddr: altera: agilex: Add SDRAM driver for Agilex
Add SDRAM driver for Agilex SoC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
733cc6cbcc ddr: altera: Restructure Stratix 10 SDRAM driver
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
fec7ddc190 cache: Add Arteris Ncore cache coherent unit driver
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.

Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
c168fc71a3 clk: agilex: Add clock driver for Agilex
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
2fd1dc5593 arm: socfpga: Move Stratix10 and Agilex system manager common code
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
8b7962a349 arm: socfpga: Move firewall code to firewall file
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.

SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
94172c7961 arm: socfpga: Convert clock manager from struct to defines
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get clock manager base address from DT node instead of using
#define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
db5741f7a8 arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
bb25aca134 arm: socfpga: Convert reset manager from struct to defines
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Ley Foon Tan
5c9c71b660 spl: Allow cache drivers to be used in SPL
Add an option for building cache drivers in SPL.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07 14:38:33 +01:00
Andy Shevchenko
98a8f445fd dfu: Add optional timeout parameter
When the `dfu` command is called from the U-Boot environment,
it now accepts an optional parameter that specifies a timeout (in seconds).
If a DFU connection is not made within that time the `dfu` command exits
(as it would if Ctrl+C was pressed). If the timeout is left empty or being
zero the `dfu` command behaves as it does now.

This is useful for allowing U-Boot to check to see if anything wants to
upload new firmware before continuing to boot.

The patch is based on the commit
5e966ccc3c
by Sebastien Colleur, which has been heavily reworked due to U-Boot changes
in the past.

Signed-off-by: Brad Campbell <bradjc5@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-07 14:37:50 +01:00
Simon Glass
b9dea62b6b video: meson: Drop unnecessary header includes
These files should not be included in meson header files. Drop them and
tidy up the affected C files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07 11:15:24 +01:00
Frieder Schrempf
83083febf5 ddr: imx8m: Return error values from LPDDR4 training
In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.

Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2020-01-07 10:26:57 +01:00
Marek Vasut
c5773ccdca pci: imx: Add iMX6SX compatible
The driver works fine with iMX6SX, add the missing compatible string.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-01-07 10:26:56 +01:00
Heiko Schocher
79db1b4665 video: lg4573: convert to DM
convert this driver to support DM.

Signed-off-by: Heiko Schocher <hs@denx.de>
2020-01-07 10:26:55 +01:00
Tom Rini
5a8fa095cb Merge branch 'next'
Bring in the following merges:

commit 8fbbec12f7
Merge: 87f69f467a 63618e71e8
Author: Tom Rini <trini@konsulko.com>
Date:   Fri Jan 3 09:48:47 2020 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

    - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support

commit 87f69f467a
Merge: c0912f9bbf 4466b99703
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 24 08:18:19 2019 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next

    - Enable DM driver on ppc/km boards
    - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
      T104x, P4080, P2041, P2020, P1020, P3041
    - Some updates in mpc85xx-ddr driver, km boards

commit c0912f9bbf
Merge: 533c9f5714 a1d6dc3f84
Author: Tom Rini <trini@konsulko.com>
Date:   Wed Dec 18 07:20:19 2019 -0500

    Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

    - Various x86 common codes updated for TPL/SPL
    - I2C designware driver updated for PCI
    - ICH SPI driver updated to support Apollo Lake
    - Add Intel FSP2 base support
    - Intel Apollo Lake platform specific drivers support
    - Add a new board Google Chromebook Coral

commit 533c9f5714
Merge: 553cb06887 033e18b47b
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 17 07:53:08 2019 -0500

    Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

    i2c: for next
    - misc: i2c_eeprom:
      Add partition support and add ability to query size
      of eeprom device and partitions
    - i2c common:
      add support for offset overflow in to address and add
      sandbox tests for it.

commit 553cb06887
Merge: f39abbbc53 b4f98b3b16
Author: Tom Rini <trini@konsulko.com>
Date:   Thu Dec 12 08:18:59 2019 -0500

    Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next

    buildman improvements including toolchain environment feature
    sandbox unicode support in serial
2020-01-06 17:07:49 -05:00
Tom Rini
797eee36a1 Revert "mmc: davinci: drop struct davinci_mmc_plat"
Adam Ford reports that this change breaks booting on da850-evm and
Bartosz Golaszewski agrees that with the impending release we should
revert the change for now.  With that noted:

This reverts commit 21a4d80a71.

Cc: Bartosz Golaszewski <brgl@bgdev.pl>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-04 09:33:33 -05:00
Dario Binacchi
bf8363931f video: add wrappers for ttf type files to .gitignore
The scripts/Makefile.lib generates an assembler file (*.S) to wrap the
font data for each file of type ttf defined in Kconfig.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-01-02 17:45:42 +01:00
Simon Glass
0c20aafe0b video: Avoid using #ifdef in video-uclass.c
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.

Change the #ifdefs to use IS_ENABLED(), etc., instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02 16:25:25 +01:00
Simon Glass
775d33229f video: Avoid using #ifdef in vidconsole-uclass.c
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.

Change the #ifdefs to use CONFIG_IS_ENABLED() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02 16:25:25 +01:00
Simon Glass
c656731901 video: Avoid using #ifdef in console_rotate.c
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.

Change the #ifdefs to use IS_ENABLED() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02 16:25:25 +01:00
Simon Glass
46421197d5 video: Avoid using #ifdef in video blitting code
This code does not really need to use #ifdef. We can use if() instead and
gain build coverage without impacting code size.

Change the #ifdefs to use IS_ENABLED() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02 16:25:25 +01:00
Simon Glass
512563ba0b video: x86: Enable 32-bit graphics by default
Most x86 boards that use video make use of 32bpp graphics. Enable this by
default. This fixes missing graphics output on some x86 boards.

Also remove the unnecessary 'default n' while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02 16:25:25 +01:00
Pankaj Bansal
63618e71e8 pci: layerscape: Manage PCIe EP compatible string via Kconfig
The ep node device tree name is governed by these bindings:
https://github.com/torvalds/linux/blob/master/Documentation/
devicetree/bindings/pci/layerscape-pci.txt#L24

As per above the ep compatible node contains platform name.
Therefore, define the ep node compatible as CONFIG to find the
pcie ep node in device tree during device tree fixup.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02 14:36:57 +05:30
Pankaj Bansal
ba7c966c0f pci: layerscape: move PCIE related CONFIG to PCI Kconfig
move the PCIE related config from arch Kconfig to PCI Kconfig.
As the PCI_LAYERSCAPE driver is being used in platform other than
fsl-layerscape platforms like ls102xa.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02 14:36:57 +05:30
Tom Rini
6cb87cbb14 Fixes for 2020.01
-----------------
 - Fixes for Nitrogen6x
 - Fix corruption for mx51evk
 - colibri i.MX6: fix broken ESDHC conversion
 - mx6sxsabresd: fix broken mmcdev
 - imx6q_logic: cleanup boot sequence
 - update ATF for imx8mq_evk
 - pfuze: fix pmic_get()
 
 Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
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Merge tag 'u-boot-imx-20191228' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------
- Fixes for Nitrogen6x
- Fix corruption for mx51evk
- colibri i.MX6: fix broken ESDHC conversion
- mx6sxsabresd: fix broken mmcdev
- imx6q_logic: cleanup boot sequence
- update ATF for imx8mq_evk
- pfuze: fix pmic_get()

Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
2019-12-28 08:07:16 -05:00
Tom Rini
1058bc5ccc Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- rk spi transfer limit fix
- Gigadevice, gd25q128 support
- spi-nor-core warnings
2019-12-27 16:46:15 -05:00
Robert Beckett
fff7b33ce5 rtc: rx8010js: add compatible string
Add compatible string used by Linux.
Allows for simpler syncing of device trees.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27 14:34:29 +01:00
Robert Beckett
0ba121668c rtc: s35392a: add compatible strings
Add compatible strings used by Linux.
Allows for simpler syncing of device trees.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27 14:34:03 +01:00
Robert Beckett
a00b1f9d7a rtc: rx8010sj: fix DM initialization
pass the udevice by reference instead of double ref

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27 14:33:11 +01:00
Jagan Teki
dbbdc81c60 spi: rk: Limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.

Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.

Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.

This change fixed two different read issues,

1. sf read failure when with > 0x10000

2. Boot from SPI flash failed during spi_flash_read call in
   common/spl/spl_spi.c

Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27 17:47:26 +05:30
Vignesh Raghavendra
cb56caacf8 mtd: spi-nor-core: Fix static checker warnings
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.

Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-27 17:47:26 +05:30
Fabio Estevam
0d3bc81391 imx8m: ddr_init: Move ddr_init() messages to debug level
Currently inside ddr_init() there is a mix of printf() and debug()
level messages.

Since this type of information is useful for debug purposes,
convert all of them to debug level for consistency.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-27 12:14:25 +01:00
Roger Quadros
305a5d840e phy: ti-pipe3: Fix SATA & USB PHY power up sequence
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence"
in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX.

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26 09:06:54 -05:00
Roger Quadros
277d5d1f9b phy: ti-pipe3: improve DPLL stability for SATA & USB
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.

For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26 09:06:54 -05:00
Roger Quadros
53df65a9d2 phy: ti-pipe3: Introduce mode property in driver data
Introduce a mode property in the driver data so that
we don't have to keep using "of_device_is_compatible()"
throughtout the driver.

No functional change.

Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26 09:06:54 -05:00
Roger Quadros
b055e67f96 phy: ti-pipe3: Use TRM recommended settings for SATA DPLL
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.

Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.

[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf

Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26 09:06:54 -05:00
Wasim Khan
7cd4272821 armv8: lx2160a: Add FSL_PEX_STREAM_ID_END for LX2160A
Add FSL_PEX_STREAM_ID_END and remove FSL_PEX_STREAM_ID_NUM
for lx2160a.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
0b964b03b0 pci: layerscape_gen4: Suffix API names with _ls_gen4
Update API names for layerscape gen4 fixup.
Suffix layerscape_gen4 fixup API names with _ls_gen4.
This is required to organize device tree fixup in common, layerscape
and layerscape_gen4 specific code.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
485304af96 pci: layerscape: Suffix API names with _ls
Suffix layerscape fixup API names with _ls.
This is required to organize device tree fixup in common,
layerscape and layerscape_gen4 specific code.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
c81b1ea7b0 pci: layerscape: Add stream_id_cur field to ls_pcie structure
Add stream_id_cur field to ls_pcie structure and initialize
it with 0 for all pcie controllers. This field will be used
for streamId calculation.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Wasim Khan
5ff7b84084 drivers/pci : enable pcie_layerscape code for lx2160a rev2
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:21 +05:30
Florinel Iordache
1990cc7db7 drivers/fsl-mc: Support DPSPARSER object and apply spb command
Add support for DPSPARSER object (create/destroy, open/close, apply spb)
which is required to configure Soft Parser by using MC.
Also add uboot command to apply Soft Parser Blob with command:
fsl_mc apply spb <spb_load_addr>

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-26 16:00:20 +05:30
Joakim Tjernlund
2a5d5d27ed mpc85xx: ddr: Always start DDR RAM in Self Refresh mode
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-23 14:07:55 +05:30
Tom Rini
d792b63feb Merge branch 'master' of git://git.denx.de/u-boot-usb
- dwc3 and cdns3 bug fixes
2019-12-22 09:14:35 -05:00
Jagan Teki
5c207282f5 usb: dwc3: Fix UTMI/UTMIW phy interface initialization
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.

The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.

So, handle the phy masking bits accordingly on respective interface
type cases.

Fixes: 6b7ebff001 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-21 20:35:16 +01:00
Vignesh Raghavendra
bdf30e8490 usb: cdns3: ep0: Fix build warnings related to cache ops
Since, commit 62f9b65447 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-21 20:35:16 +01:00
Alex Marginean
1785d8c3a5 drivers: net: bcm-sf2: pass -1 to phy_connect()
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in
the meantime.  It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or
is scanning the bus, passing -1 here should keep it functional either way.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Cc: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20 10:02:23 -06:00
Marek Vasut
a9447c022d net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYs
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20 10:02:12 -06:00
Peter Robinson
864d66431a mtd: spi-nor: ids: Add GigaDevice gd25q128
Add gd25q128 128Mbit chip to spi-nor id table.

Tested on Pinebook Pro

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18 20:05:40 +05:30
Tom Rini
c0912f9bbf Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
2019-12-18 07:20:19 -05:00
Tudor Ambarus
a11c081da3 mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser
JESD216 allow vendors to define their own SFDP tables.

Add SST SFDP parser. The vendor table is allocated using resource-managed
kmalloc - the table will be freed on driver detach. It will be accessible
by getting the UCLASS_SPI_FLASH's private data.

The SST's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-17 09:49:05 +02:00
Robert Beckett
033e18b47b misc: i2c_eeprom: add size query
Add ability to query size of eeprom device and partitions

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:58:19 +01:00
Robert Beckett
1a59cb426d misc: i2c_eeprom: add fixed partitions support
Add ability to partition eeprom via devicetree bindings

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:58:16 +01:00
Robert Beckett
951674ac7e dm: i2c: EEPROM simulator add tests for addr offset mask
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:57:31 +01:00
Robert Beckett
22e93511be dm: i2c: EEPROM simulator allow tests visibility of addr and offset
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.

Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:57:22 +01:00
Robert Beckett
85968522b9 i2c: add support for offset overflow in to address
Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.

Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:57:12 +01:00
Simon Glass
070a946008 i2c: designware: Add Apollo Lake support
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:27 +08:00
Simon Glass
0a6f333e8d x86: apl: Add pinctrl driver
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:26 +08:00
Simon Glass
28eefefccf x86: apl: Add PMC driver
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:26 +08:00
Simon Glass
7e589bc19b x86: Add a generic Intel GPIO driver
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
74749f1e84 x86: Add a generic Intel pinctrl driver
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same
code.

Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
4806fcea1a mtd: spi: Export spi_flash_std_probe()
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.

To avoid duplicating the probing code, export this probe function for use
by these drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
3937df3d6c spi: ich: Add Apollo Lake support
Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
636555a4c4 spi: ich: Add TPL support
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
92842147c3 spi: ich: Add support for get_mmap() method
Add this method so that the memory-mapped location of the SPI flash can
be queried.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
1facebd18f spi: ich: Support hardware sequencing
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
0d3ee3e199 spi: ich: Support of-platdata for fast-spi
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
43c145b8b3 spi: ich: Correct max-size bug in ich_spi_adjust_size()
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
75214b051b spi: ich: Add mmio_base to struct ich_spi_platdata
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
a550662c27 spi: ich: Various small tidy-ups
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
b47aa26eb9 spi: ich: Fix header order
Move the header files into the right order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
702b28a163 spi: ich: Convert to livetree
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
17e754492f spi: ich: Move the protection/lockdown code into a function
Reduce the size of the probe function but putting this code into its own
function.

Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:21 +08:00
Simon Glass
674990c0dc spi: ich: Move init function just above probe()
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:21 +08:00
Simon Glass
e8ac6ffe04 x86: spi: Don't enable SPI_FLASH_BAR by default
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.

Drop the default enabling of this option on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:21 +08:00
Simon Glass
ccdabd8956 spi: Correct operations check in dm_spi_xfer()
At present we have to have an xfer() method even if it does nothing. This
is not correct, so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:21 +08:00
Simon Glass
26047f6029 x86: Allow removal of standard PCH drivers
These drivers are not needed on all platforms. While they are small, it
is useful in TPL to drop then. Add Kconfig control to allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:16 +08:00
Simon Glass
fbb0efdd27 sandbox: Add a test for IRQ
Add a simple sandbox test for this uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:12 +08:00
Simon Glass
79d66a6ac1 x86: Move UCLASS_IRQ into a separate file
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:12 +08:00
Simon Glass
3e17ffbb44 sandbox: Add PCI driver and test for p2sb
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:11 +08:00
Simon Glass
5bee27aa41 pci: Add support for p2sb uclass
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:11 +08:00
Simon Glass
3b65ee34b9 x86: sandbox: Add a PMC emulator and test
Add a simple PMC for sandbox to permit tests to run.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:11 +08:00
Simon Glass
6c6d88e142 x86: power: Add an ACPI PMC uclass
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:10 +08:00
Simon Glass
642e8487ec x86: timer: Reduce timer code size in TPL on Intel CPUs
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.

Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as

   39146a2e0b x86: Move CPU init to before spl_init()

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:10 +08:00
Simon Glass
77dd7c6854 x86: timer: use a timer base of 0
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.

When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.

Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:09 +08:00
Simon Glass
8aeafb5454 dm: pinctrl: Allow enabling full pinctrl in SPL/TPL
At present these options cannot be enabled for SPL/TPL, but this can be
useful in some cases. Add Kconfig options to allow it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:09 +08:00
Simon Glass
fa11fe1b03 i2c: designware: Support use in SPL
Allow this driver to set up an IO address in SPL using an 'early-regs'
property. This allows SPL to use the I2C driver without having to enable
the full PCI stack.

Also split out ofdata_to_platdata in designware driver since this is more
correct, and more convenient for the new logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:08 +08:00
Simon Glass
8d72d5bf08 i2c: designware: Avoid using static data
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.

It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:08 +08:00
Simon Glass
457df2337f i2c: designware: Tidy up PCI support
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.

Actually the Baytrail settings should really come from the device tree.

Note that 'has_max_speed' is added as well. This is currently always false
but since only Baytrail provides the config, it does not affect operation
for other devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:08 +08:00
Simon Glass
6dd4b01432 dm: pci: Move pci_get_devfn() into a common file
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.

To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.

Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Simon Glass
2206ac248a dm: pci: Allow delaying auto-config until after relocation
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.

This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Simon Glass
bcee8d6764 dm: gpio: Allow control of GPIO uclass in SPL
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
Rasmus Villemoes
875669da3b sysreset_mpc83xx: fix mcp83xx -> mpc83xx typo
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-12-13 13:01:53 -05:00
Tom Rini
553cb06887 buildman improvements including toolchain environment feature
sandbox unicode support in serial
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Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next

buildman improvements including toolchain environment feature
sandbox unicode support in serial
2019-12-12 08:18:59 -05:00
Tom Rini
3031cdede1 Merge tag 'fix-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c bugfixes for 2020.01
- i2c: i2c_cdns: fix write timeout on fifo boundary
  fixes timout issue when writting number of bytes is multiple
  of the FIFO depth.
2019-12-11 08:17:19 -05:00
Tom Rini
addb1d9f5d First set of u-boot-atmel fixes for 2020.01 cycle
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Merge tag 'u-boot-atmel-fixes-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

- First set of u-boot-atmel fixes for 2020.01 cycle:
  This set includes a small fix for gpio bank names, one for removing
  unused headers (also touches some other boards), and a fix for the QSPI
  env read on one of the boards.
2019-12-11 08:16:16 -05:00
Michael Auchter
3104162a8b i2c: i2c_cdns: fix write timeout on fifo boundary
This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).

Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.

In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.

Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.

Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-11 06:25:13 +01:00
Michael Auchter
b4f98b3b16 cros_ec: use uint instead of uint8_t for cmd param
Chromium EC commands can be up to 16-bits, so using a uint8_t here can
cause truncation. Update to use a uint instead.

It looks like this should likely have been done as a part of
9fea76f5d3, but this function was skipped
for some reason.

Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-10 21:11:31 -07:00
Tom Rini
fd4b8f813f - fix crash and board reset when drawing RLE8 bitmaps
bigger than the framebuffer resolution
 - reduce dead code in video and console uclass routines
   (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
    stm32f746-disco, stm32f769-disco and wandboard)
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Merge tag 'fixes-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- fix crash and board reset when drawing RLE8 bitmaps
  bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
  (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
   stm32f746-disco, stm32f769-disco and wandboard)
2019-12-10 15:41:15 -05:00
Heinrich Schuchardt
5e5c785e34 serial: sandbox: support Unicode
Due to a conversion error the sandbox does not accept byte values 0x80-0xff
from the keyboard. The UEFI extended text input unit test requires Unicode
support.

Use unsigned char for the serial buffer.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
2019-12-10 05:54:55 -07:00
Tom Rini
520f955902 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
2019-12-09 21:53:23 -05:00
Rick Chen
31dae22faa spl: cache: Allow cache drivers in SPL
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
2019-12-10 08:23:10 +08:00
Tom Rini
ac1ca99926 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net 2019-12-09 13:48:22 -05:00
Vignesh Raghavendra
382c0c629e net: ti: am65-cpsw-nuss: Add new compatible for J721e
Add new compatible to handle J721e SoC

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
461a290c5a net: ti: am65-cpsw-nuss: Rework RX flow ID handling
Get flow ID information for RX DMA channel using dma_get_cfg() interface
instead of reading from DT. This is required in order to avoid DT update
whenever there is change in the range of flow ID allocated to the host.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
5e6d9ccde9 dma: ti: k3-udma: Implement dma_get_cfg() interface
Implement dma_get_cfg() interface to pass flow id information for DMA
clients to use. This is needed because on K3 SoCs, CPSW (ethernet) and
UDMA (DMA provider) support "flows" within a given RX DMA channel. This
allows different network packets to be segregated while using same RX
DMA channel. In order for basic ethernet to work, CPSW slave must be
aware of the flow ID allocated for the RX channel by the DMA driver.
This interface allows CPSW to query flow ID from DMA provider and
configure it in CPSW HW.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Vignesh Raghavendra
b8a4dd28f3 dma: Introduce dma_get_cfg() interface
Sometimes, there would be a need to exchange data between DMA provider
and DMA client which are very specific to DMA driver of the SoC/platform
and are not generic enough to be put into struct dma. Therefore, introduce
dma_get_cfg() interface to get DMA provider specific data from client
device. Clients can use unique configuration ID flags to get different
configuration data from DMA driver.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-09 09:47:43 -06:00
Cédric Le Goater
08b3e90a01 net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN
Fixes: e766849713 ("net: ftgmac100: convert the RX/TX descriptor arrays")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
1e354cb393 drivers: net: fsl_enetc: register internal MDIO bus
This bus is used to access internal SoC PHYs.  These PHYs are configured
by the ENETC driver directly, but it's useful to have command line access
to this MDIO to debug the system especially when using new external PHYs.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
6c96446859 drivers: net: fsl_enetc_mdio: return with time-out if HW is stuck
On some boards MDIO may get stuck if it detects echo on the line.  This is
a know hardware issue, there is a board fix for it.  In case we're running
on a board that doesn't have the fix, we don't want to loop here forever
and freeze U-Boot.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
a931f78307 drivers: net: fsl_enetc: move PCS and PHY config to probe
This reduces the time needed to establish a link as we don't reset the link
each time the interface is used.  Our Link capabilities do not change at
run-time so there is no need to re-apply PHY configuration each time.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
307f8a6d1f drivers: net: fsl_enetc: Add 2.5Gbps to supported link speeds
The original code enabled link speeds up to 1Gbps, but the interface can
go up to 2.5G, enable that speed to in PHY AN mask.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
17bd7eae72 drivers: net: fsl_enetc: use the new MDIO DM helper functions
Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify
the code.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
e22e3aff92 drivers: net: fsl_enetc: use XFI, USXGMII interface type macros
Apply 10G PCS init for USXGMII, XFI interface types.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
6d9bc2043a drivers: net: aquantia: check system interface too when checking for link up
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface.  The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
05f86070c0 drivers: net: aquantia: set SMBus addr based on DT property
Aquantia PHYs have a SMBus interface mostly used for debug.  The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique.  Add an optional DT property used
to change SMBus address if needed.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
7552ee9a01 drivers: net: aquantia: set MDI reversal based on DT property
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:43 -06:00
Alex Marginean
a301ec7a5a drivers: net: aquantia: set up SI protocol based on interface type
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.

Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Alex Marginean
5fe861b8b2 drivers: net: aquantia: add PHY generation information
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Alex Marginean
8a141d6e9c drivers: net: aquantia: use XFI, USXGMII interface types
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII.  Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register.  Keep that functionality too, so we don't break existing drivers.

Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Anatolij Gustschin
389488df92 net: phy: fix switch vendor name
Fix vendor name in MV88E61xx option description.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Anatolij Gustschin
5bcb4b8ff6 net: phy: mv88e61xx: register phy_driver struct for 88E6071
Support probing and init for 88E6071 switch.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Anatolij Gustschin
41820c4baa net: phy: mv88E61xx: fix ENERGY_DET init for mv88E6071
On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Anatolij Gustschin
4aa05f6cf3 net: phy: mv88e61xx: add CPU port parameter init for 88E6071
On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Anatolij Gustschin
f41a722baa net: phy: mv88e61xx: rework to enable detection of 88E6071 devices
Extend the driver to init switch register offsets from variables
instead of compile time macros and enable detection of 88E6071 and
compatible devices. Ethernet transfer (e.g. tftp) does not work yet,
so enable the registration of the 'indirect mii' bus for easier PHY
register access by 'mii' command.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Nicolas Ferre
b2f2643b39 net: phy: micrel: make sure the factory test bit is cleared
The KSZ8081 PHY has a factory test mode which is set at the de-assertion
of the reset line based on the RXER (KSZ8081RNA/RND) or TXC
(KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a
pull-up, the factory test mode should be cleared by manually writing a 0
(according to the datasheet).
Create another ksz8081_config function to handle this case.

Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Florin Chiculita
bf58916373 net: phy: aquantia: wait for phy init sequence to finish
Aquantia quad-phys may take longer to initialize. This commit adds
a polling mechanism for a global alarm bit that tells if phy init
sequence is completed.

Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Josef Holzmayr
7c56408be6 net: macb: let miiphy_read/_write pass arbitrary addresses
This allows passing arbitrary addresses through macb_miiphy_read and
macb_miiphy_write, therefore enabling the mii command to access
all mdio bus devices instead of only the defined phy.

Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Josef Holzmayr
0d3044c210 net: macb: explicitly pass phy_adr to mdio read and write
To support accessing arbitrary addresses the mii/mdio bus it is
necessary that the macb_mdio_read and macb_mdio_write functions
do not implicitly use the address of the connected phy.

The function signature is extended according to the Linux kernel
equivalent.

Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Stefan Roese
27c3f70f3b net: phy: Increase link up delay in genphy_update_link()
I've noticed that in most cases when genphy_update_link() is called, the
ethernet driver (mt7628-eth in this case) fails with the first ethernet
packets. Resulting in a timeout of the first tftp command. Increasing
the delay in the link check look from 1 to 50 ms and moving it below the
BMSR register read fixes this issue, resulting in a stable ethernet
traffic, even after initial link autonogotiation.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Thierry Reding
945dd965dd net: rtl8169: Support RTL-8168c/8111c
This version of the RTL-8168 chip can be found on some add-in cards sold
by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it
needs to have the ChipCmd register programmed after the DMA descriptors
have been set up, so make sure that happens by adding an entry to the
chip information table.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Nevo Hed
17caaf8a9d net: mvpp2: MVPP2 now needs MVMDIO
Changes to mvpp2.c require the MVMDIO module which in turn uses
DM_MDIO.

Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Nevo Hed
2a42870778 net: mvpp2: use new MVMDIO driver
This commit ports mvpp2 to use the recently introduced Marvell MDIO
(MVMDIO) driver.  It removes direct interaction with the SMI & XSMI
busses.  This commit is based in part on earlier work by
Ken Ma <make@marvell.com> in Marvell's own downstream repo:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c81dc39.

The above refrenced work was based on an MVMDIO implementation that
never made it into U-Boot.  With this patch the mvpp2 driver switches
to use the new MVMDIO driver that is based on a more universal
mdio-uclass implementation.

Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grzegorz Jaszczyk
623948377a net: mvpp2: mark phy as invalid in case of missing appropriate driver
If the phy doesn't match with any existing u-boot drivers, the phy
framework will connect it to the generic one which uid ==
0xffffffff. In this case, act as if the phy wouldn't be declared in
dts. Otherwise, in case of 3310 (for which the driver doesn't exist)
the link is marked as always down. Removing phy entry from dts in case
of 3310 is not a good option because it is required for the
phy_fw_down procedure.

This patch fixes the issue with the link always down on MCBIN board.

nhed: added NULL deref test.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nevo Hed <nhed+github@starry.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Stefan Chulski
13b725fd24 net: mvpp2x: fix traffic stuck after PHY start error
Issue:
- Network stuck if autonegotion fails.

Issue root cause:

- When autonegotiation fails during port open procedure, the packet
  processor configuration does not finish and open procedure exits
  with error.
- However, this doesn't prevent u-boot network framework from
  calling send and receive procedures.
- Using transmit and receive functions of misconfigured packet
  processor will cause traffic to get stuck.

Fix:

- Continue packet processor configuration even if autonegotiation
  fails.  Only error message is triggered in this case.
- Exit transmit and receive functions if there is no PHY link
  indication.
- U-boot network framework now calls open procedure again during next
  transmit initiation.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
37d6265f2b net: phy: dp83867: refactor rgmii configuration
Refactor SGMII configuration to group all settings together and reduce
number of MDIO transactions.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
253a5ff871 net: phy: dp83867: io impedance is not dependent on RGMII delay
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not
dependent on RGMII delay") of mainline linux kernel.

The driver would only set the IO impedance value when RGMII internal delays
were enabled.  There is no reason for this.  Move the IO impedance block
out of the RGMII delay block.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
20f7ea4c35 net: phy: dp83867: rework delay rgmii delay handling
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay
handling") of mainline linux kernel.

The current code is assuming the reset default of the delay control
register was to have delay disabled.  This is what the datasheet shows as
the register's initial value.  However, that's not actually true: the
default is controlled by the PHY's pin strapping.

This patch:
- insures the other direction's delay is disabled If the interface mode is
selected as RX or TX delay only
- validates the delay values and fail if they are not in range
- checks if the board is strapped to have a delay and is configured to use
"rgmii" mode and warning is generated that "rgmii-id" should have been
used.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
b3b9b128d5 net: phy: dp83867: Add ability to disable output clock
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable
output clock") of mainline linux kernel.

Generally, the output clock pin is only used for testing and only serves as
a source of RF noise after this.  It could be used to daisy-chain PHYs, but
this is uncommon.  Since the PHY can disable the output, make doing so an
option.  I do this by adding another enumeration to the allowed values of
ti,clk-output-sel.

The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
expect: to select the REF_CLK as the output.  Rather it meant "keep clock
output setting as is", which, depending on PHY strapping, might not be
outputting REF_CLK.

Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
Omitting the property will leave the setting as is (which was the previous
behavior in this case).

Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK.
Change this so they generate an error.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
ee622f03cc net: phy: dp83867: move static initialization to .probe()
Move static, one-time initialization to .probe() callback.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Grygorii Strashko
5ee989c5aa net: phy: ti: rename ti.c to dp83867.c
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it
accordingly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Priyanka Jain
1f60789602 net/phy: Fix phy_connect() for phy addr 0
Fix 'mask' calculation in phy_connect() for phy addr '0'.
'mask' is getting set to '0xffffffff' for phy addr '0'
in phy_connect() whereas expected value is '0'.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reported-by: tetsu-aoki via github
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-09 09:47:42 -06:00
Tom Rini
2f02845817 Fixes for 2020.01
-----------------
 
 - imx8qxp_mek: increase buffer sizes and args number
 - Fixes for imx7ulp
 - imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
 - colibri_imx7: reserve DDR memory for Cortex-M4
 - vining2000: fixes and convert to ethernet DM
 - imx8m: fix rom version check to unbreak some B0 chips
 - tbs2910: Disable VxWorks image booting support
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Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------

- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
2019-12-09 10:32:08 -05:00
AKASHI Takahiro
05429b6cf5 rtc: move date.c from drivers/rtc/ to lib/
In the next commit, rtc_mktime(), for compatibility with linux, will be
implemented using rtc_mktime(), which is no longer drivers/rtc specific.
So move this file under lib/.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2019-12-06 16:44:19 -05:00
Anatolij Gustschin
2cc393f32f video: make BPP and ANSI configs optional
Many boards do not use all selected framebuffer depth
configurations, for such boards there is some unused
code in video and console uclass routines. Make depth
specific code optional to avoid dead code and slightly
reduce binary size. Also make ANSI code optional for
the same reason. When i.e. using only VIDEO_BPP16 the
code size shrinks (below values when using gcc-7.3.0):

  $ ./tools/buildman/buildman -b video-wip -sS wandboard
  ...
  01: Merge git://git.denx.de/u-boot-sh
  02: video: add guards around 16bpp/32bbp code
  03: video: make BPP and ANSI configs optional
         arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
2019-12-06 16:38:51 +01:00
Anatolij Gustschin
ca5655d800 video: add guards around 16bpp/32bbp code
Many boards use only single depth configuration, for such boards
there is some unused code in video and console uclass routines.
Add guards to avoid dead code.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
2019-12-06 16:37:45 +01:00
Tom Rini
bead4f2f2c Merge tag 'u-boot-rockchip-20191206' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rockchip pwm driver update to support all the SoCs
- RK3308 GMAC and pinctrl support
- More UART interface support on PX30 and pmugrf reg fix
- Fixup on misc for eth_addr/serial#
- Other updates on variant SoCs
2019-12-06 10:35:18 -05:00
Frieder Schrempf
f5edb0d86d clk: imx: imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
The 24MHz oscillator clock is referenced by "clock-osc-24m" and not
"osc_24m".

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-06 13:57:42 +01:00
Patrice Chotard
ca2c6945b9 video: bmp: Fix video_display_rle8_bitmap()
In case the BMP size is bigger than the frame buffer, don't use
the BMP's width and height in video_display_rle8_bitmap, but the
one's checked in video_bmp_display() as parameters to
video_display_rle8_bitmap().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
CC: Yannick Fertré <yannick.fertre@st.com>
2019-12-06 09:07:45 +01:00
Patrice Chotard
1ebf2855b4 video: bmp: Fix video_splash_align_axis()
Convert panel_picture_delta and axis_alignment from unsigned long
to long to insure to store correctly the difference between
panel_size and picture_size in case the panel_size is smaller
than picture_size.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
CC: Yannick Fertré <yannick.fertre@st.com>
[agust: change axis_alignment to long]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-12-06 09:07:45 +01:00
David Wu
41eee945ce pinctrl: rockchip: Add pinctrl support for rk3308
An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.

For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.

So add a type IOMUX_8WIDTH_2BIT to calculate offset.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
4ee6d51c5a pwm: rk_pwm: Make PWM driver to support all Rockchip Socs
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.

The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.

The RK3288 keep the current functions.

RK3328 and the chips after it, which can support hardware lock,
configure duty, period and polarity at next same period, to
prevent the intermediate temporary state.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
David Wu
0ed8f1e5f4 net: gmac_rockchip: Add support for rk3308
Add the glue code to allow the rk3308 variant of the Rockchip gmac
to provide network functionality.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-06 00:06:23 +08:00
Thomas Hebb
9f67b56772 Fix typo in macros, "FIRMEWARE" -> "FIRMWARE"
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-05 10:28:39 -05:00
Jorge Ramirez-Ortiz
2464b229b5 drivers: optee: rpmb: fix returning CID to TEE
The mmc CID value is one of the input parameters used to provision the
RPMB key. The trusted execution environment expects this value to be
specified in big endian format.

Before this fix, on little endian systems, the value returned by the
linux kernel mmc driver differed from the one returned by u-boot.
This meant that if linux provisioned the RPMB key, u-boot would not
have access to the partition (and the other way around).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2019-12-05 10:28:38 -05:00
Michael Walle
a6cd597a78 drivers: pci: ignore disabled devices
PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-05 10:28:38 -05:00
Miquel Raynal
fb4384490d mtd: Makefile: deep cleanup
Move MTD-related lines out of the root Makefile. Put them in their
respective directories. Enclose some of these new lines to skip them
when building the SPL. MTD core files and some MTD device drivers are
compiled in a mtd.o object and included in the final object only if
MTD support is required (there are two different symbols for that, one
for U-Boot and one for the SPL).

Now that all defconfigs have been fixed, we can stop the logic where
enabling a command selects the core files to compile. This logic is
broken since selecting a symbol with a 'depends on' will not enforce
this secondary dependency.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
eb446ef625 cmd: nand/sf: isolate legacy code
The 'sf' command is not supposed to rely on the MTD stack, but both
'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite
their location, these functions do not depend at all on the MTD
stack.

This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is
selected, which is inconsistent with the current situation. Solve this
by moving these three functions (which are only used by the above two
commands) out of mtd_uboot.c and put them in a C file only compiled
with cmd/sf.c and cmd/nand.c.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Don't export get_part function now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
85f7e9d547 mtd: spi: SPI_FLASH_MTD depends on MTD
It is already the case that all defconfigs with SPI_FLASH_MTD also
declare using MTD, but let's make this consistent and enforce it in
Kconfig. Most of the time SPI_FLASH_MTD is used in conjunction with
UBI, which already depends on MTD.

Suggested-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
f3a02d29e8 dfu: add dependency on the raw NAND core
CONFIG_DFU_NAND needs the raw NAND core being compiled.

Also fix the colibri_vf defconfig to reflect this dependency.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
c8f555f102 mtd: nand: add includes in NAND core to avoid warnings
Because of the include's game, when some files are compiled for a SPI
NAND device, no warning appears. But when it is for a raw NAND device,
GCC complains. Fix these warning by including <common.h>.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2019-12-04 17:10:51 -05:00
Miquel Raynal
888f184abe mtd: rename CONFIG_MTD_DEVICE -> CONFIG_MTD
Like in Linux, just use CONFIG_MTD to compile the MTD stack.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2019-12-03 23:04:10 -05:00
Miquel Raynal
1de770d544 mtd: rename CONFIG_MTD -> CONFIG_DM_MTD
CONFIG_MTD must be reserved for the MTD core. Like any other
subsystem, prefix the symbol by DM when it comes to DM support.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
[trini: Add Kconfig files]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 23:04:10 -05:00
Miquel Raynal
88718be300 mtd: rename CONFIG_NAND -> CONFIG_MTD_RAW_NAND
Add more clarity by changing the Kconfig entry name.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Re-run migration, update a few more cases]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
2019-12-03 23:04:10 -05:00
Tom Rini
a7bbaf8c13 Fix stdout-path handling
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Merge tag 'dm-pull-3dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

Fix stdout-path handling
2019-12-03 18:12:04 -05:00
mingming lee
485627dd5f pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
mingming lee
69373bd44a mmc: mtk-sd: Adjust the mmc tuning flow
1.Support cmd response and data tuning together.
2.Support hs400 cmd responese tuning.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
mingming lee
9072400775 clk: mediatek: add driver for MT8518
Add clock driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
2019-12-03 08:44:14 -05:00
Faiz Abbas
42a4ee8a11 regmap: Fix potential memory leaks
Free allocated memory in case of an error in regmap_init_mem() and
regmap_init_mem_index().

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-12-03 08:44:14 -05:00
Faiz Abbas
ae3ef109c3 net: cpsw: Add NULL pointer check
Add null pointer check to take care of out of memory errors.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-12-03 08:44:14 -05:00
Bartosz Golaszewski
3ef94715cc mmc: davinci: fix mmc boot in SPL
The MMC boot is currently broken on omapl138-lcdk after enabling the
driver model in SPL. The main problem is the driver's bind callback not
being called after probe in SPL (even with the DM_FLAG_PRE_RELOC flag
specified).

While a proper fix is still being worked on, this hacky changeset at
least fixes the MMC boot on this platform by calling mmc_bind()
manually from probe().

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:14 -05:00
Bartosz Golaszewski
21a4d80a71 mmc: davinci: drop struct davinci_mmc_plat
struct mmc_config & struct mmc don't need to be exported over platform
data, but can instead be private in the driver.

Remove struct davinci_mmc_plat.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:13 -05:00
Bartosz Golaszewski
6a97153cbf mmc: davinci: drop support for ti,dm6441-mmc
The DM family of DaVinci SoCs is no longer supported. Drop the
irrelevant code from the driver.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-12-03 08:44:13 -05:00
Tom Rini
4df23e58a4 blk: Make use of CONFIG_HAVE_BLOCK_DEVICE more
When we do not have CONFIG_BLK (or SPL/TPL) enabled there are very few
cases where we need the blk_legacy code linked in. To catch these, build
when we have CONFIG_HAVE_BLOCK_DEVICE set.  In addition, we only need
cmd/blk_common.o to be linked in when we have CONFIG_HAVE_BLOCK_DEVICE
set, so make use of that directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 08:43:24 -05:00
Tom Rini
56e5a39346 mtd: mtdcore: Drop unused mtd_table
The array 'mtd_table' is unused in the code.  Remove this as gcc doesn't
always discard unused global variables.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 08:43:24 -05:00
Tom Rini
923e211f8d pci: Only link pci_rom.o in some cases
The content of pci_rom.c is only used in a few cases.  Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 08:43:24 -05:00
Tom Rini
e78f16b751 Convert CONFIG_SYS_CORTINA_FW_IN_MMC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_CORTINA_FW_IN_MMC
   CONFIG_SYS_CORTINA_FW_IN_NAND
   CONFIG_SYS_CORTINA_FW_IN_NOR
   CONFIG_SYS_CORTINA_FW_IN_REMOTE
   CONFIG_SYS_CORTINA_FW_IN_SPIFLASH

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-03 08:43:24 -05:00
Thomas Hebb
6920f00c2c Kconfig: make TPL_DM_SERIAL depend on TPL_DM
This missing dependency seems like an oversight, since all other
TPL_DM_* options have it.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
2019-12-03 08:43:23 -05:00
James Byrne
f3510e9754 gpio: at91_gpio: Add bank names
Make the at91_gpio driver set sensible GPIO bank names in the platform
data. This makes the 'gpio status' command a lot more useful.

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-12-03 10:17:25 +02:00
Simon Glass
cb3ef6810a common: Move old EEPROM functions into a new header
These functions do not use driver model but are still used. Move them to a
new eeprom.h header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:25 -05:00
Simon Glass
2cf431c228 common: Move pci_init_board() out of common.h
This function can be dropped when all boards use driver model for PCI. For
now, move it into init.h with a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:25 -05:00
Simon Glass
67c4e9f815 common: Move board_get_usable_ram_top() out of common.h
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:04 -05:00
Simon Glass
288b29e44d common: Move command functions out of common.h
Move these functions into the command.h header file which is a better fit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:02 -05:00
Simon Glass
36bf446b64 common: Move enable/disable_interrupts out of common.h
Move these two functions into the irq_funcs.h header file. Also move
interrupt_handler_t as this is used by the irq_install_handler() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:01 -05:00
Simon Glass
c30b7adbca common: Move interrupt functions into a new header
These functions do not use driver model but are fairly widely used in
U-Boot. But it is not clear that they will use driver model anytime soon,
so we don't want to label them as 'legacy'.

Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it
is widely used in U-Boot already.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:00 -05:00
Simon Glass
1eb69ae498 common: Move ARM cache operations out of common.h
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:24:58 -05:00
Simon Glass
9edefc2776 common: Move some cache and MMU functions out of common.h
These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.

Move them over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:55 -05:00
Simon Glass
68a6aa85ec common: Move mii_init() function out of common.h
This function belongs in mii.h so move it over.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
1045315df0 common: Move get_ticks() function out of common.h
This function belongs in time.h so move it over and add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Simon Glass
036a017f79 common: Move wait_ticks functions out of common.h
This function belongs in time.h so move it over and add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
6887c5bed9 common: Move some time functions out of common.h
These functions belong in time.h so move them over and add comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:11 -05:00
Simon Glass
f516fd99ec common: Move serial_printf() to the serial header
Move this function header to serial.h since this function is clearly
related to serial. The function itself stays in console.c since we don't
have a single serial file. DM and non-DM each has a separate file so we
would have to either create a new common serial file, or repeat the
function in both serial.c and serial-uclass.c, neither of which seem
worthwhile.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:10 -05:00
Simon Glass
2310c8ede3 serial: usb: Correct the usbtty_...() prototypes
The function declarations in serial.h are not in sync with what is
currently used in usbtty. Fix this by updating the header and including
it, to help catch future such problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:10 -05:00
Simon Glass
2189d5f1e8 Move strtomhz() to vsprintf.h
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.

Use the vsprintf.h include file explicitly where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:09 -05:00
Simon Glass
3db7110857 crc32: Use the crc.h header for crc functions
Drop inclusion of crc.h in common.h and use the correct header directly
instead.

With this we can drop the conflicting definition in fw_env.h and rely on
the crc.h header, which is already included.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:08 -05:00
Simon Glass
c3a4d1c3ee common: Drop linux/crc8.h
We have an existing U-Boot header for the one function that this defines.
Use that instead of the linux/ one. Move over the nice comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:07 -05:00
Simon Glass
c076e5c9b3 status_led: Tidy up the code style
There are a few whitespace problems with this code. Tidy them up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Simon Glass
c3e4430ef3 common: Drop global inclusion of status_led.h
This is only used by a few files so it should not be in the common header.
Move it out.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:06 -05:00
Simon Glass
9ce2aa1710 Drop CONFIG_SHOW_ACTIVITY
This feature is not enabled by any board. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-02 18:23:06 -05:00
Bin Meng
151f275e05 dm: serial: Handle "stdout-path" with ":options" correctly
With commit f0921f5098 ("fdt: Sync up to the latest libfdt"),
SiFive Unleashed board does not boot any more. This was due to
the U-Boot local changes commit 77d7fff8ce ("fdt: Fix handling
of paths with options in them") to libfdt/fdt_ro.c was dropped
during the libfdt upgrade.

>From the history [1] it was mentioned that the U-Boot changes
commit 77d7fff8ce ("fdt: Fix handling of paths with options in
them") was rejected by libfdt upstream, hence we need find another
way to fix the things.

This commit uses another method, by updating serial_check_stdout()
directly to handle the situation of "stdout-path" with ":options".
A simpler way is to change the logic in fdtdec_get_chosen_node()
to do similar thing, but I feel that not every property in chosen
node may have the option in them, hence it would make more sense
to do the special handling in serial_check_stdout() directly.

[1]: http://patchwork.ozlabs.org/patch/462756/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-02 16:18:05 -07:00
Tom Rini
c4f697b291 Merge git://git.denx.de/u-boot-usb
- USB keyboard improvements
2019-11-28 07:34:21 -05:00
Marek Vasut
56b0bb96be mmc: tmio: sdhi: Add calibration tables
Instead of using single fixed value for the calibration offset,
add tables which dynamically adjust this per calibration code
from the SCC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
1bdcb83d29 mmc: tmio: sdhi: Skip bad taps
Some of the tuning taps produce suboptimal results. Add code
which skips those "bad" taps.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
6900066cf6 mmc: tmio: sdhi: Add SCC error checking
Check SCC for errors after check command if applicable and
optionally adjust the bus skew settings accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
8f39b03022 mmc: tmio: sdhi: Disable auto-retuning in HS400
Disable the auto-retuning in HS400 mode in favor of manual calibration.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
e5d3f3d9e5 mmc: tmio: sdhi: Adjust HS400 calibration offsets
Adjust the TMPPORT3 offsets according to the latest information
from the chip vendor.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
dc419fc6e1 mmc: tmio: sdhi: Adjust DT2FF settings for HS400 mode
Adjust the DT2FF offsets in HS400 according to latest information
from the chip vendor.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
810998871a mmc: tmio: sdhi: Use 4 tuning taps on M3W up to ES1.2
The M3W up to ES1.2 uses 4 tuning taps for HS400, make it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
37c3990664 mmc: tmio: sdhi: Track SMPCMP valu in private data
Retain the SMPCMP value from last calibration in private data.
This will be later used for skipping bad taps.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Marek Vasut
0196a58a79 mmc: tmio: sdhi: Track current tap number in private data
Retain the tap number from last calibration in private data. This
will be later used for SCC error checking after each command.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-27 16:56:46 +08:00
Yangbo Lu
5e81cbff37 mmc: fsl_esdhc: get clock directly from global data
This patch is to get clock directly from global data.

- Remove uclass clk api method. This was what i.MX platforms were
  using, while QorIQ platforms weren't.
- Get clock only from global data, dropping mxc_get_clock().
  QorIQ eSDHC controllers on one silicon use same reference clock.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27 16:55:56 +08:00
Baruch Siach
1b71695228 mmc: sdhci: make sdhci_get_cd static
sdhci_get_cd() is not referenced anywhere else. Limit its scope to
sdhci.c.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2019-11-27 16:55:19 +08:00
Tom Rini
4b19b89ca4 - add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
 - add support for one binary on RPi3/4
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Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-boot

- add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
- add support for one binary on RPi3/4
2019-11-25 12:56:27 -05:00
Heinrich Schuchardt
12f1e7908a dm: test: usb: rework keyboard test
Allow the unit test to pass full 8 byte scan code sequences to the USB
keyboard emulation driver and to parse multi-byte escape sequences.

The following features are not yet tested:

* LED status
* caps-lock
* num-lock
* numerical pad keys

The following features are not yet implemented by the USB keyboard
driver and therefore not tested:

* modifiers for non-alpha-numeric keys, e.g. <SHIFT><TAB> and <ALT><F4>
* some special keys, e.g. <PRINT>
* some modifiers, e.g. <ALT> and <META>
* alternative keyboard layouts

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-11-25 13:28:53 +01:00
Heinrich Schuchardt
87e91bccae usb: kbd: implement special keys
Provide support for F1-F12, Insert, Delete, Home, End, Page Up, Page Down.

As this leads to a size increase provide a customizing setting
CONFIG_USB_KEYBOARD_FN_KEYS.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-11-25 13:28:53 +01:00
Fabio Estevam
beeb57f0a6 Revert "video: mxsfb: Configure the clock after eLCDIF reset"
Commit ec3dcea744 ("video: mxsfb: Configure the clock after eLCDIF reset")
causes boot regression on imx7d-pico/imx7d-sdb boards, so revert it
until a better solution is prepared.

This reverts commit ec3dcea744.

Reported-by: Joris Offouga <offougajoris@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-11-24 21:50:44 +01:00
Matthias Brugger
3f8b8e3036 drivers: bcm283x: Set pre-location flag for OF_BOARD
U-Boot support on Raspberry Pi 4 relies on the device-tree
provided by the firmware. The blob does not contain the
U-Boot specific pre-loc-rel properties. The result is, that
the U-Boot banner is not printed.

We fix this by setting the DM_FLAG_PRE_RELOC flag in the driver,
if we rely on a device-tree provided by the firmware.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Matthias Brugger
d2086d6633 pinctrl: bcm283x: Add compatible for RPi4
The Raspberry Pi 4 upstream kernel device tree instroduces
a new compatible for the pinctroller. Add this to the driver
so that we can boot with the upstream kernel DT.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24 10:46:27 +01:00
Tom Rini
9a0cbae22a Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Clean vid/pid in Kconfig and add fastboot for rk3399
- add 'u-boot, spl-fifo-mode' for mmc
- Use FIT generator for rk3229 optee and rk3368 ATF
- fan53555: add support for Silergy SYR82X and SYR83X
2019-11-23 20:50:11 -05:00
Heiko Stuebner
c8dd0e42d7 rockchip: dwmmc: add handling for u-boot, spl-fifo-mode
Rockchips dwmmc controllers can't do dma to non-ddr addresses,
like for example the soc-internal sram but during boot parts of
TrustedFirmware need to be placed there from the read FIT image.

So add handling for a u-boot,spl-fifo-mode to not put the mmc
controllers into fifo mode for all time.

The regular fifo-mode property still takes precedent and only
if not set do we check for the spl-specific property.

Suggested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-11-23 23:41:44 +08:00
Jagan Teki
3d3b83a573 gadget: rockchip: Add rk3399 USB_GADGET_PRODUCT_NUM
Add 0x330c for rk3399 gadget product number.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
6b7ebff001 usb: dwc3: Add phy interface for dwc3_uboot
U-Boot has two different variants of dwc3 initializations,
- with dm variant gadget, so the respective dm driver would
  call the dwc3_init in core.
- with non-dm variant gadget, so the usage board file would
  call dwc3_uboot_init in core.

The driver probe would handle all respective gadget properties
including phy interface via phy_type property and then trigger
dwc3_init for dm-variant gadgets.

So, to support the phy interface for non-dm variant gadgets,
the better option is dwc3_uboot_init since there is no
dedicated controller for non-dm variant gadgets.

This patch support for adding phy interface like 8/16-bit UTMI+
code for dwc3_uboot.

This change used Linux phy.h enum list, to make proper code
compatibility.

Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
35172ac02f fastboot: rockchip: Fix rk3328 default mmc device
Technically the default mmc device for fastboot would
use eMMC if the board support for it.

Rockchip platform access device 0 for eMMC so, use the
same device number for rk3328.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
a9af59a30a fastboot: rockchip: Select FASTBOOT_FLASH[_MMC_DEV]
Select CONFIG_FASTBOOT_FLASH, CONFIG_FASTBOOT_FLASH_MMC_DEV
for rockchip SoC plaforms in fastboot Kconfig file instead
of defined it in board defconfig.

This eventually drop the explicit configs defined in
supporting board defconfig files.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
b032061405 gadget: rockchip: Add rk3128 USB_GADGET_PRODUCT_NUM
Add 0x310c for rk3128 gadget product number.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
132b012ede gadget: rockchip: USB_GADGET_PRODUCT_NUM
Rockchip support differnet or common gadget product number
between Rockchip SoCs like,

0x310a - rk3036
0x320a - rk3229, rk3288
0x330a - rk3328

So, select them on Kconfig based on platform specific
config defined.
   
This eventually drop the explicit configs defined in
supporting board defconfig files.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
89cbceb388 gadget: Select USB_GADGET_VENDOR_NUM for rockchip
Gadget vendor number, 0x2207 is common across all platfroms
supported in Rockchip SoC.

So, select the same number globally, if ARCH_ROCKCHIP.

This eventually drop the explicit configs defined in supported
board defconfig files.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Jagan Teki
89e311d494 gadget: Select USB_GADGET_MANUFACTURER for rockchip
Select the gadget manufacturer as 'Rockchip' for
all rockchip platform SoC's.

This eventually drop the explicit defined added
on supported board defconfig files.

Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Vasily Khoruzhick
e82692ab32 power: fan53555: fix fan53555_regulator_set_value
fan53555_regulator_set_value() passes its own dev to pmic_clrsetbits()
instead of its parent (pmic). As result u-boot crashes when you try to
set voltage on fan53555 regulator

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Vasily Khoruzhick
c9fca5ec88 rockchip: i2c: don't sent stop bit after each message
That's not correct and it breaks SMBUS-style reads and and writes for
some chips (e.g. SYR82X/SYR83X).

Stop bit should be sent only after the last message.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Vasily Khoruzhick
5ef1e02e99 power: fan53555: add support for Silergy SYR82X and SYR83X
SYR82X and SYR83X are almost identical to FAN53555, the only difference
is different die ID and revision, voltage ranges and steps.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23 22:29:49 +08:00
Tom Rini
47b48fe186 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Assorted fixes
2019-11-22 10:41:46 -05:00
Tom Rini
c59afcff8a Merge branch 'master' of git://git.denx.de/u-boot-usb
- Fix some possible alignment issues
2019-11-22 10:20:56 -05:00
Simon Goldschmidt
7dc0ac6015 usb: dwc2: fix possible alignment issues
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"

Fix this by converting dwc2_fifo_read to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-22 01:25:40 +01:00
Simon Goldschmidt
616ebd8b9c usb: composite: fix possible alignment issues
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"

Fix this by converting two functions to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-22 01:25:36 +01:00
Simon Goldschmidt
64c7c8c91c spi: cadence_qspi: support DM_CLK
Support loading clk speed via DM instead of requiring ad-hoc code.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20 23:46:11 +01:00
Simon Goldschmidt
caaaf62ac8 timer: dw-apb: add reset handling
To use this DM timer on socfpga as system tick, it needs to take itself
out of reset.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20 22:32:00 +01:00
Simon Goldschmidt
aacd7b922f ddr: socfpga: gen5: constify altera_gen5_sdram_ops
Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-20 22:32:00 +01:00
Tom Rini
ad38de2093 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- Fix CONFIG_AHCI related build warning for P2041, P3041, P5040, T102x,
  T104x, T4240 platforms
2019-11-20 15:38:51 -05:00
Tom Rini
30b59dd8ba input: Move input.o to be built only in some cases
We only need to build and link input.o when we have any of
CONFIG_KEYBOARD, CONFIG_DM_KEYBOARD (and SPL/TPL variants) or
CONFIG_TEGRA_KEYBOARD set.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-19 17:43:04 -05:00
Vignesh Raghavendra
e5521b1c6f usb: cdns3: Fix include file path
xhci.h has now been moved to include/usb/ directory. Therefore, update the
path in the Cadence USB drivers.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-19 16:07:14 +01:00
Peng Ma
6b9d8a70af ata: sata_sil: Add DM support for Silicon sata driver
Add DM support for Silicon(SIL3131 / SIL3132 / SIL3124) sata driver as
few of the PowerPC platforms such as P series based boards need to
use SATA_SIL with DM,

Also fix below warning while PowerPC P series boards compilation,

===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Peng Ma
e08b5b1465 ata: fsl_sata: Add DM support for Freescale PowerPC SATA driver
Add DM support for Freescale PowerPC sata driver used for PowerPC T series
SoCs,

CONFIG_BLK needs to be enabled on these platforms. It adds the SATA
controller as AHCI device, which is strictly speaking not correct,
as the controller is not AHCI compatible, But the U-Boot AHCI uclass
interface enables the usage of this DM driver,

Also fix below warning while PowerPC T series boards compilation,

===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-19 14:11:44 +05:30
Tom Rini
fffb826ea0 - fix i.MX6ULL evk black screen observed while reboot stress tests
- remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree
   differences between Linux and U-Boot for stm32mp1 platform
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Merge tag 'video-for-v2020.01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- fix i.MX6ULL evk black screen observed while reboot stress tests
- remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree
  differences between Linux and U-Boot for stm32mp1 platform
2019-11-18 10:48:29 -05:00
Tom Rini
d64efd920e Merge tag 'u-boot-rockchip-20191118' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip SoC: PX30, RK3308
- Add and migrate to use common dram driver: PX30, RK3328, RK3399
- Add rk3399 board Tinker-s support
- Board config update for Rock960, Rockpro64
2019-11-17 21:15:57 -05:00
Andy Yan
54069939be rockchip: rk3308: Add sdram driver
A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Finley Xiao
fe9efbca7b rockchip: clk: Add clk driver for rk3308
Add clk controller driver for RK3308 SOC.

This patch depends on Elaine's pll patch[0].

[0]http://patchwork.ozlabs.org/patch/1183718/

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Elaine Zhang
bbda2ed584 rockchip: clk: pll: add common pll setting funcs
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
a5ada25e42 rockchip: clk: fix wrong CONFIG_IS_ENABLED handling
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so
without the leading CONFIG_. The clock drivers all wrongly check for
CONFIG_RESET_ROCKCHIP, fix that

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Heiko Stuebner
a04f6fd17f rockchip: clk: rv1108: remove duplicate reset init
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.

So we can get rid of the open-coded reset init and just fix
the correct cru reference.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Kever Yang
e76943ca6f rockchip: usb: Migrate to use ofnode
Migrate to use ofnode_* instead of fdt_* so that we may able to use live
dt for usb udc driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:22:53 +08:00
Finley Xiao
a907dc3f25 misc: add driver for the Rockchip otp controller
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:15 +08:00
Heiko Stuebner
b079118400 net: gmac_rockchip: add support for px30
Add the glue code to allow the px30 variant of the Rockchip gmac
to provide network functionality.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:10 +08:00
Kever Yang
d49a526750 rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:07 +08:00
David Wu
8fb3268586 pinctrl: rockchip: add px30 pinctrl driver
Add the necessary glue code to allow pinctrl setting on px30 socs.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 17:23:04 +08:00
YouMin Chen
bcfacab517 ram: rk3399: Fix dram setting to make dram more stable
There are some code different with rockchip vendor code which may lead
to different bugs, including:
1) Fix setting error about LPDDR3 dram size ODT.
2) Set phy io speed to 0x2.
3) Fix setting error about phy_pad_fdbk_drive.
4) Fix setting error about PI_WDQLVL_VREF_EN

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
c8863b8508 ram: rk3399: update calculate_stride
Update the calculation of the stride to support all the DRAM case.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
da53f0641b ram: rk3399: Sync the io setting from Rockchip vendor code
The io setting are updated after some bugfix in different rk3399 boards,
sync the code from vendor.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
7cf04ad1f6 ram: rockchip: update lpddr4 timing for rk3399
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
f2b58f0749 ram: rk3399: add support detect capacity
Add capacity detect for rk3399 so that the driver able to detect the
capacity automatically.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
0cacc27569 ram: rk3399: update the function of sdram_init
Clean up the sdram_init to keep sync with rockchip source code.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
410d7863bc ram: rk3399: fix error about get_ddrc0_con reg addr
Correct the register to its correct name.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
f8088bfc85 ram: rk3399: Clean up code
Clean up rk3399 dram driver source code for more readable.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
a922d0d102 ram: rk3399: migrate to use common code
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
ca93e32139 ram: rk3328: use common sdram driver
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
YouMin Chen
39edfaa758 ram: px30: add sdram driver
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.

For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
691368c7f7 ram: rockchip: add phy driver code for PX30
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
09d7872336 ram: rockchip: add controller code for PX30
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
fba7bd4c34 ram: rockchip: Default enable DRAM debug info
The debug info for dram is main about the capacity related info which is
very important the board init, so set this default enable.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
ec0d29aefa ram: rockchip: move sdram_debug function into sdram_common
The functions for dram info print are part of common code.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
d6647b08b2 ram: rockchip: add common code for sdram driver
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
5d19ddf0db ram: rockchip: rename sdram_common.c/h to sdram.c
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
2a2f0b177c ram: rockchip: rename sdram.h to sdram_rk3288.h
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Patrick Delaunay
1dd49f577b pinctrol: dm: remove the function pinctrl_decode_pin_config
Remove the pinctrl_decode_pin_config() API, because this
function is unused and not compatible with livetree
(it uses fdtdec_get_bool instead of ofnode API).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-11-14 07:09:34 -06:00
Patrick Delaunay
754815b854 video: stm32: remove the compatible "synopsys, dw-mipi-dsi" support
Remove the compatible "synopsys,dw-mipi-dsi" added in U-Boot
(it don't exist in Linux kernel binding); it is only used
to bind the generic synopsys UCLASS_DSI_HOST "dw_mipi_dsi" to
the driver "stm32-display-dsi" UCLASS_VIDEO_BRIDGE

This binding is done in Linux kernel drivers without compatible
(dw_mipi_dsi_bind() is called in bind of driver, for example in
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c).

This patch does the same in U-Boot driver, the STM32 driver
calls during its bind the function device_bind_driver_to_node
to bind the generic driver "dw_mipi_dsi" at the same address.

This patch reduces the device tree differences
between Linux kernel and U-Boot for stm32mp1 platform.

Tested with v2020.01-rc1 on STM32MP157C-EV1 and STM32MP157C-DK2.

The dependency of driver is clearer and the probe order is guaranteed.

STM32MP> dm tree
 Class     Index  Probed  Driver                Name
-----------------------------------------------------------
 root          0  [ + ]   root_driver           root_driver
 sysreset      0  [   ]   syscon_reboot         |-- reboot
 simple_bus    0  [ + ]   generic_simple_bus    |-- soc
 serial        0  [ + ]   serial_stm32          |   |-- serial@40010000
...
 video_brid    0  [ + ]   stm32-display-dsi     |   |-- dsi@5a000000
 dsi_host      0  [ + ]   dw_mipi_dsi           |   |   |-- dsihost
 panel         0  [ + ]   rm68200_panel         |   |   `-- panel-dsi@0
...

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-11-12 16:15:53 +01:00
Tom Rini
5f7ff6d63e u-boot-imx-20191105
-------------------
 i.MX8MN SoC support
 ROM API image download support
 i.MX8MM enet enabling
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Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
2019-11-12 07:18:23 -05:00
Fabio Estevam
ec3dcea744 video: mxsfb: Configure the clock after eLCDIF reset
Running stress reboot test on a i.MX6ULL evk board with a
custom LCD can lead to splash screen failure (black screen).

After comparing the eLCDIF initialization with the Linux kernel
driver, it was noticed that the eLCDIF reset is the first operation
that needs to be done.

So do like the eLCDIF Linux driver and move the eLCDIF clock
frequency configuration after the eLCDIF reset and just prior to
setting the RUN bit.

With this change applied, no more black screen issues has been
found during overnight reboot stress tests.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-11-12 10:32:37 +01:00
Tom Rini
086e391bc4 Merge tag 'u-boot-rockchip-20191110' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
2019-11-11 14:19:32 -05:00
Tom Rini
0b73ef0c02 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI
2019-11-11 14:19:04 -05:00
Simon South
c4b9d66f11 ram: rk3328: Fix loading of skew values
Fix a typo that caused incorrect values to be loaded into the DRAM
controller's deskew registers.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Simon South
18c24c1177 ram: rk3328: Use correct frequency units in function
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units
for the DDR frequency, causing the DRAM controller to be misconfigured
in most cases.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Simon South
2cbdb6e051 clk: rockchip: rk3328: Configure CPU clock
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Joseph Chen
ee30068fa5 power: pmic: rk809: support rk809 pmic
The RK809 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(5*BUCKs, 9*LDOs, 2*SWITCHes)
    - RTC
    - Clocking

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:34:10 +08:00
Joseph Chen
b4a35574b3 power: pmic: rk817: support rk817 pmic
The RK817 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH)
    - RTC
    - Clocking

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:33:52 +08:00
Elaine Zhang
b62280745e power: pmic: rk805: support rk805 pmic
The RK805 are a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(4*BUCKs, 3*LDOs)
    - RTC
    - Clocking

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:32:51 +08:00
Elaine Zhang
addd062bea power: pmic: rk816: support rk816 pmic
The RK816 is a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
    - Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH)
    - RTC
    - Clocking

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:32:41 +08:00
Elaine Zhang
94afc1cb46 power: regulator: rk8xx: update the driver for rk808 and rk818
In order to adapt the following pmics, make the interface more compatible.
Support buck and ldo suspend voltage setting and getting.
Supprot buck and ldo suspend enable/disable setting and getting.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:31:34 +08:00
Joseph Chen
11406b8f7e dm: regulator: support regulator more state
support parse regulator standard property:
regulator-off-in-suspend;
regulator-init-microvolt;
regulator-suspend-microvolt:
 regulator_get_suspend_enable
 regulator_set_suspend_enable
 regulator_get_suspend_value
 regulator_set_suspend_value

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:31:09 +08:00
Tom Rini
a4b7485e2f Merge branch 'master' of git://git.denx.de/u-boot-usb
- Assorted fixes
2019-11-08 14:05:07 -05:00
Tom Rini
ee1c499851 Merge branch '2019-11-07-master-imports'
- Add Phytium Durian Board
- Assorted bugfixes
- Allow for  make ERR_PTR/PTR_ERR architecture specific
2019-11-08 07:27:45 -05:00
Xiaowei Bao
56e6f810b0 configs: spi: Add the SPI_FLASH_BAR for ESPI
Add the SPI_FLASH_BAR for the ESPI controller of FSL, this entry
is missed by
commit 6d82517836 ("configs: Don't use SPI_FLASH_BAR as default")

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 16:32:08 +05:30
Chunfeng Yun
e0891bb679 usb: xhci: support 1.1 or later version
The xHCI 1.1 version also need set Transfer Type field

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-08 11:09:08 +01:00
Michael Walle
29a6617ada drivers: net: fsl_enetc: fix RGMII configuration
Add the missing RGMII PHY modes in which case the MAC has configure its
RGMII settings. The only difference between these modes is the RX and
TX delay configuration. A user might choose any RGMII mode in the device
tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:23:01 +05:30
Michael Walle
2efb147a0a drivers: net: fsl_enetc: set phydev->node
The saved ofnode is used by some PHY drivers to access the device tree
node of the PHY.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:23:01 +05:30
Pankaj Bansal
05c81d98e4 pci: layerscape: Only set EP CFG READY bit
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.

While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.

Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Keerthy
065a452ae6 power: regulator: tps65941: add regulator support
The driver provides regulator set/get voltage
enable/disable functions for tps65941 family of PMICs.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
6b86dd0c1e power: pmic: tps65941: Add support for tps65941 family of PMICs
Add support to bind the regulators/child nodes with the pmic.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Keerthy
9a03e50c5f misc: k3_avs: Add j721e support
j721e SoCs have different OPP tables. Add support for the same.

Note: DM Still has lot of voltages TBD hence the correct
values need to be programmed once they are published.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Tero Kristo
22e8f18980 power: regulator: tps6236x: add support for tps6236x regulators
TPS6236x is a family of step down DC-DC converters optimized for battery
powered portable applications for a small solution size. Add a regulator
driver for supporting these devices.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Keerthy
e0aa873bc7 clk: clk-ti-sci: Notify AVS driver upon setting clock rate
Notify AVS driver upon setting clock rate so that voltage
is changed accordingly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Tero Kristo
9d233b4e3e misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
liu hao
e3aafef4cf arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>

Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-07 18:01:13 -05:00
Tom Rini
d911087889 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- mpc85xx, socrates: Add dts, enable DM support, fix warnings, disable
  video
2019-11-07 07:25:14 -05:00
T Karthik Reddy
f69257baa8 usb: composite: add BOS descriptor support to composite framework
To add usb-3.0 support to peripheral device add BOS & SS capability
descriptors to gadget composite framework.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
d80effb184 usb: gadget: Add gadget_is_cdns3() macro
Add a new bcdDevice entry for Cadence USB gadget controller similar to
other controller and add gadget_is_cdns3() macro as well.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
a9ca4193bd usb: cdns3: Add TI wrapper driver for CDNS USB3 controller
Add driver to handle TI specific wrapper for Cadence USB3 controller
present on J721e SoC. Based on Linux driver for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
927c22b0da usb: cdns3: gadget: Implement udc_set_speed() callback
Implement udc_set_speed() callback to limit Controller's speed to
high-speed/full-speed when working with gadgets that are high-speed or
full-speed only

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
7e91f6ccdc usb: Add Cadence USB3 host and gadget driver
Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Sherry Sun
8d94e184ff usb: udc: Introduce ->udc_set_speed() method
This patch was copied from kernel commit: 67fdfda4a99ed.

Sometimes, the gadget driver we want to run has max_speed lower than
what the UDC supports. In such situations, UDC might want to make sure
we don't try to connect on speeds not supported by the gadget
driver because that will just fail.

So here introduce a new optional ->udc_set_speed() method which can be
implemented by interested UDC drivers to achieve this purpose.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
77dcbdf3c1 usb: gadget: Add match_ep() op to usb_gadget_ops
Add match_ep() op to usb_gadget_ops similar to Linux kernel which is
useful in finding a suitable ep match for the function driver. This will
avoid adding more gadget_is_xxx() handling code to usb_ep_autoconfig().

Also sync usb_ep_caps struct thats is usually used in the match_ep()
callback by the gadget controller driver

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Tom Rini
a8c1846633 Merge branch 'master' of git://git.denx.de/u-boot-usb
- DFU updates
- USB Storage updates
2019-11-06 07:11:02 -05:00
Heiko Schocher
b61cbbdcab pci: add DM based mpc85xx driver
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-06 16:30:19 +05:30
Peng Fan
673f659732 net: fec_mxc: support i.MX8M with CLK_CCF
Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1
drivers/net/ethernet/freescale/fec_main.c.

Since i.MX8MQ not support CLK_CCF, so add a check to restrict
the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined.

Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
81dc2ac557 net: Kconfig: FEC: Add dependency on i.MX8M
Make FEC driver could be used by i.MX8M when CONFIG_FEC_MXC defined
in defconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
ddf66d2159 clk: imx: imx8mm: add set_parent callback
Add set_parent callback, then assigned-clock-parents in dts could
be work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
3bdd558737 clk: imx8mm: add enet clk
Add enet ref/timer/PHY_REF/root clk which are required to make enet
function well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
a3aff5e5f3 clk: imx: add i.MX8MN ccf driver
Add i.MX8MM ccf driver support.
Modifed from Linux Kernel 5.3.0-rc1, drop some entries
that not used in U-Boot and adapt to U-Boot CCF style.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Lukasz Majewski <lukma@denx.de>
2019-11-05 10:27:18 +01:00
Peng Fan
b6f2945227 pinctrl: imx8m: support i.MX8MN
Support i.MX8MN in imx8m pinctrl driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
afd267af8d power: domain: add i.MX8 scu power domain driver
The power domain tree is not accepted by Linux Kernel upstream.
only a single pd node is used currently, as following:

		pd: imx8qx-pd {
			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <1>;
		};

So to migrate to use upstream linux dts, we also need a driver
to support this.

This patch is to support the new method, compared with legacy power
domain tree, it will be simpiler, because each device will
has resource id as power domain index, it will be directly passed
to scfw, and no need to let power domain build that tree. If multiple
power domain is needed, it is the dts node should has correctly power
domains entry added and sequence correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
954b9311ab power: domain: make imx8-power-domain.c legacy
The current i.MX8 power domain driver is based on i.MX vendor
power domain tree which will retire later.

The Linux upstream use a single pd node for power domain driver,
and U-Boot will adopt that. When U-Boot i.MX8 dts synced with
Linux Kernel upstream and related driver ready, the legacy
driver will be removed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
816d093c1a misc: imx8: scu: simplify code to make it extendable
clk and pinctrl will be get(probed) during each device probe,
we don't need to probe them in scu driver. Only need to bind the sub-nodes
(clk and iomuxc) of MU node with their drivers.

So drop the code to probe the clk/pinctrl, and this patch will make it
easy to add more subnodes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
f65d08411d mmc: fsl_esdhc_imx: Update compatible string for imx8m
To enable HS400(ES) and UHS for imx8m platforms, update the driver data
to share with imx8qm esdhc_soc_data.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 11:21:25 +08:00
Peng Fan
1d01c984b9 mmc: fsl_esdhc_imx: drop redundant clock settings
During mmc initialization, there are several calls to mmc_set_clock
and mmc_set_ios. When mmc_power_off, the mmc->clock will be set,
but the imx driver will use 400KHz. So the following calls
to mmc_set_ios will set the clock several times which is redundant
in fsl_esdhc_imx driver. So let's simplify to remove redundant
clock settings.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
618704753e mmc: fsl_esdhc: clean up DM and non-DM code
Make DM and non-DM code clear using below structure.
	#if !CONFIG_IS_ENABLED(DM_MMC)
		<non-DM_MMC code>
	#else
		<DM_MMC code>
	#endif

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
0cc127c424 mmc: fsl_esdhc: always check write protect state
The QorIQ eSDHC on all platforms supports checking write protect
state through register bit. So check it always.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
08197cb8df mmc: fsl_esdhc: drop redundant code for non-removable feature
Drop redundant code for non-removable feature. "non-removable" property
has been read in mmc_of_parse().

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
5705973b09 mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common()
The fsl_esdhc_init() was actually to get configuration of mmc_config.
So rename it to fsl_esdhc_get_cfg_common() and make it common for both
DM_MMC and non-DM_MMC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
07bae1de38 mmc: fsl_esdhc: clean up bus width configuration code
This patch is to clean up bus width setting code.

- For DM_MMC, remove getting "bus-width" from device tree.
  This has been done in mmc_of_parse().

- For non-DM_MMC, move bus width configuration from fsl_esdhc_init()
  to fsl_esdhc_initialize() which is non-DM_MMC specific.
  And fix up bus width configuration to support only 1-bit, 4-bit,
  or 8-bit. Keep using 8-bit if it's not set because many platforms
  use driver without providing max bus width.

- Remove bus_width member from fsl_esdhc_priv structure.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
5b05fc0310 mmc: fsl_esdhc: fix voltage validation
Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
531ccd407c mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init()
Controller initialization is not needed in fsl_esdhc_init().
It will be done in esdhc_init() for non-DM_MMC, and in
esdhc_init_common() in probe for DM_MMC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Tom Rini
73b6e6ad25 u-boot-imx-20191104
-------------------
 
 - i.MX NAND: nandbcb support for MX6UL / i.MX7
 - i.MX8: support for HAB
 - Convert to DM (opos6ul, mccmon6)
 - Toradex i.MX6ull colibri
 - sync DTS with kernel
 
 Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416
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Merge tag 'u-boot-imx-20191104' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191104
-------------------

- i.MX NAND: nandbcb support for MX6UL / i.MX7
- i.MX8: support for HAB
- Convert to DM (opos6ul, mccmon6)
- Toradex i.MX6ull colibri
- sync DTS with kernel

Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416
2019-11-04 12:57:41 -05:00
Tom Rini
3b02d614b4 Merge branch '2019-11-04-ti-imports'
- Various CPSW related improvements, DTS resync
2019-11-04 12:57:34 -05:00
Grygorii Strashko
62f8e846a7 net: ti: cpsw: convert to use dev/ofnode api
Conver TI CPSW driver to use dev/ofnode api.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
[trini: Add <dm/ofnode.h> to provide the prototype to ofnode]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-04 12:56:37 -05:00
Tom Rini
ee93ef0c4b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Add support for Intel FSP-S and FSP-T in binman
- Correct priority selection for image loaders for SPL
- Add a size check for TPL
- Various small SPL/TPL bug fixes and changes
- SPI: Add support for memory-mapped flash
2019-11-03 19:28:54 -05:00
Igor Opaniuk
9ab5f221a5 nand: mxs_nand: add API for switching different BCH layouts
On i.MX7 in a sake of reducing the disturbances caused by a neighboring
cells in the FCB page in the NAND chip, a randomizer is enabled when
reading the FCB page by ROM bootloader.

Add API for setting BCH to specific layout (and restoring it back) used by
ROM bootloader to be able to burn it in a proper way to NAND using
nandbcb command.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03 21:49:19 +01:00
Ye Li
264977d1c2 mach-imx: Adding new argument for SIP call interface
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.

Signed-off-by: Ye Li <ye.li@nxp.com>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Peng Fan
672fc540cd power: pmic: Kconfig: add CONFIG_SPL_DM_PMIC_BD71837
Add CONFIG_SPL_DM_PMIC_BD71837 to make this driver could be
used in SPL stage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Peng Fan
e0f724f718 pmic: bd71837: drop DEBUG macro
Drop DEBUG macro definition which is used for debug purpose.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Sébastien Szymanski
cde421cfc8 video: mxsfb: set gd->fb_base
Set gd->fb_base so it can be shown with bdinfo command.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Robert Hancock
f2929d11a6 watchdog: imx: Use immediate reset bits for expire_now
The expire_now function was previously setting the watchdog timeout to
minimum and waiting for the watchdog to expire. However, this watchdog
also has bits to trigger immediate reset. Use those instead, like the
Linux imx2_wdt driver does.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03 17:04:16 +01:00
Robert Hancock
ceea0c145d watchdog: imx: Add DT ext-reset handling
The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the
device tree to specify whether the board design should use the external
reset instead of the internal reset. Use this boolean to determine which
mode to use rather than using external reset unconditionally.

For the legacy non-DM mode, the external reset is always used in order
to maintain the previous behavior.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03 17:04:16 +01:00
Grygorii Strashko
da6a728ea4 net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode
Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY
interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping
default value (enabled) for MAC TX internal delay when "rgmii-rxid"
interface mode is selected.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
a3c867a217 net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode
Now TI CPSW driver will disable MAC TX internal delay for PHY interface
mode "rgmii-rxid" which is incorrect.

Hence, fix it by keeping default value (enabled) for MAC TX internal delay
when "rgmii-rxid" interface mode is selected.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
3c57b620db net: ti: cpsw: add support for standard eth "max-speed" dt property
This patch adds support for standard Ethernet "max-speed" DT property to
allow PHY link speed limitation.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
4040148b9e net: ti: cpsw: move parsing of dt port's parameters in separate func
Move parsing of dt port's parameters in separate func for better code
readability.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
60e81d0d28 net: ti: cpsw: enable 10Mbps link speed support in rgmii mode
According to TRMs the 10Mbps link speed is supported in RGMII only when
CPSW2G MAC SL is configured for External Control ("in band") mode
CPSW_SL_MACCTRL.EXT_EN(18) = 1.

Hence update cpsw_slave_update_link() to follow documentation.

[1] https://patchwork.kernel.org/patch/10285239/
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Simon Glass
a478a26cd0 x86: timer: Use a separate flag for whether timer is inited
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.

Update the code to use a separate flag instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:27 +08:00
Simon Glass
096c71e34b x86: timer: Set up the timer in timer_early_get_count()
This function can be called before the timer is set up. Make sure that the
init function is called so that it works correctly.

This is needed so that bootstage can work correctly in TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:27 +08:00
Simon Glass
c53b318e1b spi: Add support for memory-mapped flash
On x86 platforms the SPI flash can be mapped into memory so that the
contents can be read with normal memory accesses.

Add a new SPI method to find the location of the SPI flash in memory. This
differs from the existing device-tree "memory-map" mechanism in that the
location can be discovered at run-time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:26 +08:00
Tom Rini
61e8f2985b Merge tag 'arc-fixes-for-2020.01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
ARC fixes for v2020.01-rc2

The main change is move to DM_MMC of yet 2 another ARC boards:
AXS101 & IoTDK.

Among that we improve handling of stock-formatted SD-cards of high volume
on EM SDP as well as introduction of reset driver for HSDK which is required
for prepser reinitialization of some peripherals like USB etc.
2019-11-01 17:49:40 -04:00
Eugeniy Paltsev
c597e248d9 ARC: HSDK: introduce reset driver
Introduce reset driver for Synopsys ARC HSDK SoC

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-01 16:45:40 +03:00
Tom Rini
24b77393a5 Pull request for UEFI sub-system for efi-2020-01-rc2
Provide a better user interface for setting UEFI variables.
 
 Bug fixes:
 - ext4 file system not discovered on UEFI block device
 - 'make tests' build error on 32bit systems
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Merge tag 'efi-2020-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-01-rc2

Provide a better user interface for setting UEFI variables.

Bug fixes:
- ext4 file system not discovered on UEFI block device
- 'make tests' build error on 32bit systems
2019-11-01 09:37:02 -04:00
Tom Rini
bb1bb4bb5d Fix for patman with email addresses containing commas
Bootstage improvements for TPL, SPL
 Various sandbox and dm improvements and fixes
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Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dm

- Fix for patman with email addresses containing commas
- Bootstage improvements for TPL, SPL
- Various sandbox and dm improvements and fixes
2019-11-01 09:34:35 -04:00
Jean-Jacques Hiblot
4e18429883 drivers: phy: Handle gracefully NULL pointers
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-31 07:22:53 -04:00
Roman Kapl
6e7325533b ata: ahci allow 64-bit DMA for SATA
Allow 64-bit DMA on AHCI. If not supported by the host controller, at
least print a message and fail.

Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-10-31 07:22:53 -04:00
Patrick Wildt
2f83481dff nvme: use page-aligned buffer for identify command
Change the stack-allocated buffer for the identification command
to explicitly allocate page-aligned buffers.  Even though the spec
seems to allow having admin queue commands on non page-aligned
buffers, it seems to not be possible on my i.MX8MQ board with a
a Silicon Power P34A80.  Since all of the NVMe drivers I have seen
always do admin commands on a page-aligned buffer, which does work
on my system, it makes sense for us to do that as well.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31 07:22:53 -04:00
Patrick Wildt
8c403402ca nvme: flush dcache on both r/w, and the prp list
It's possible that the data cache for the buffer still holds data
to be flushed to memory, since the buffer was probably used as stack
before.  Thus we need to make sure to flush it also on reads, since
it's possible that the cache is automatically flused to memory after
the NVMe DMA transfer happened, thus overwriting the NVMe transfer's
data.  Also add a missing dcache flush for the prp list.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31 07:22:53 -04:00
Heinrich Schuchardt
232ba76231 virtio: pci: use correct type in virtio_pci_bind()
For printing as %u we should use an unsigned int.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31 07:22:53 -04:00
Marek Vasut
02b0e1a36c usb: ehci-hcd: Keep async schedule running
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disabling async schedule back and forth for every single transaction.
However, enabling/disabling the async schedule does not take effect
immediatelly, but instead may take up to 1 mS (8 uFrames) to complete.

This impacts USB storage significantly, esp. since the recent reduction
of maximum transfer size to support more USB storage devices. This in
turn results in sharp increase in the number of ehci_submit_async()
calls. Since one USB storage BBB transfer does three such calls and
the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB,
which is unacceptable.

However, this overhead can be removed simply by keeping the async
schedule running. Specifically, the first transfer starts the async
schedule and then each and every subsequent transfer only adds a new
QH into that schedule, waits until the QH is completed and does NOT
disable the async schedule. The async schedule is stopped only by
shutting down the controller, which must happen before moving out
of U-Boot, otherwise the controller will corrupt memory.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2019-10-31 12:13:40 +01:00
Patrick Delaunay
067c13c70b dfu: add callback for flush and initiated operation
Add weak callback to allow board specific behavior
- flush
- initiated

This patch prepare usage of DFU back end for communication with
STM32CubeProgrammer on stm32mp1 platform with stm32prog command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
ec44cace4b dfu: add DFU virtual backend
Add a virtual DFU backend to allow board specific read and write
(for OTP update for example).

Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
d5640f700d dfu: add partition support for MTD backend
Add the support of MTD partition for the MTD backend.

The expected dfu_alt_info for one alternate on the mtd device :
	<name> part <part_id>
        <name> partubi <part_id>

"partubi" also erase up to the end of the partition after write operation.

For example: dfu_alt_info = "spl part 1;u-boot part 2; UBI partubi 3"

U-Boot> dfu 0 mtd nand0

Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
6015af28ee dfu: add backend for MTD device
Add DFU backend for MTD device: allow to read
and write on all MTD device (NAND, SPI-NOR,
SPI-NAND,...)

For example :
> set dfu_alt_info "nand_raw raw 0x0 0x100000"
> dfu 0 mtd nand0

This MTD backend provides the same level than dfu nand
backend for NAND and dfu sf backend for SPI-NOR;
So it can replace booth of them but it also
add support of spi-nand.

> set dfu_alt_info "nand_raw raw 0x0 0x100000"
> dfu 0 mtd spi-nand0

The backend code is based on the "mtd" command
introduced by commit 5db66b3aee ("cmd: mtd:
add 'mtd' command")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
0de1022d88 dfu: allow read with no data without error for EOF indication
This patch allows the DFU backend to indicate that that it can't
provide no more data to fill the DFU buffer, by setting b_left =0
without error, even if the size of received data is lower of the
expected total size indicated by get_medium_size.

For USB DFU stack point of view, it is acceptable:
the read length < requested size in DFU_UPLOAD and the
transaction is stopped.

That avoid infinite loop issue in dfu_read_buffer_fill because the
size for the DFU read is limited by get_medium_size = r_left
and the DFU stack expects that read is allowed up to this size.

This issue never occurs for current flash device (where chunk are
always completely read, and b_left will be never 0) but it is useful for
virtual partition when the backend only know the max size of this
alternate, the real size of the data are only known in the read
treatment.

PS: for file access on mmc, EOF is never reached as
    dfu_get_medium_size_mmc returns the exact size of the file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
febabe3ed4 dfu: allow to manage DFU on several devices
Add support of DFU for several interface/device
with one command.

The format for "dfu_alt_info" in this case is :
- <interface> <dev>'='alternate list (';' separated)
- each interface is separated by '&'

The previous behavior is always supported.

One example for NOR (bootloaders) + NAND (rootfs in UBI):

U-Boot> env set dfu_alt_info \
"sf 0:0:10000000:0=spl part 0 1;u-boot part 0 2; \
u-boot-env part 0 3&nand 0=UBI partubi 0,3"

U-Boot> dfu 0 list

DFU alt settings list:
dev: SF alt: 0 name: spl layout: RAW_ADDR
dev: SF alt: 1 name: ssbl layout: RAW_ADDR
dev: SF alt: 2 name: u-boot-env layout: RAW_ADDR
dev: NAND alt: 3 name: UBI layout: RAW_ADDR

U-Boot> dfu 0

$> dfu-util -l

Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=3, name="UBI", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=2, name="u-boot-env", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=1, name="u-boot", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=0, name="spl", serial="002700333338511934383330"

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
9ada683055 dfu: prepare the support of multiple interface
Split the function dfu_config_entities with 2 new functions
- dfu_alt_init
- dfu_alt_add

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
cb986ba0fe dfu: sf: add partition support for nor backend
Copy the partition support from NAND backend to SF,
support part and partubi option.
In case of ubi partition, erase the rest of the
partition as it is mandatory for UBI.

The added code is under compilation flag CONFIG_DFU_SF_PART
activated by default.

for example:

U-Boot> env set dfu_alt_info "spl part 0 1;\
u-boot part 0 2;u-boot-env part 0 3;UBI partubi 0 4"
U-Boot> dfu 0 sf 0:0:10000000:0

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
909b690b31 dfu: cosmetic: cleanup sf to avoid checkpatch error
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Marek Szyprowski
fd15b58c1a dwc3: flush cache only if there is a buffer attached to a request
Calling cache flush on invalid buffer, even with zero length might cause
an exception on certain platforms.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2019-10-31 12:12:31 +01:00
Marek Szyprowski
d2d8eab421 dfu: mmc: add support for in-partition offset
Add possibility to define a part of partition as a separate DFU entity.
This allows to have more than one items on the given partition.

The real use case for this option is TM2 board. It can use u-boot stored
as Linux kernel on the defined partition (as RAW data) and load the real
kernel from the same partition, but stored under the certain offset.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Marek Szyprowski
ade08db899 gadget: f_thor: properly enable 3rd endpoint defined by the protocol
This is needed to make Windows THOR flash tool happy, because it
starts sending data only when interrupt packet is received on the 3rd
endpoint.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Ralph Siemsen
0a815ff7bb dfu: dfu_nand: reduce verbosity
In combination with multiple partitions in NAND, this printf() ends up
being more noise than helpful. Change it to debug() instead.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Vignesh Raghavendra
d624434f5e dwc3-generic: Don't fail probe if clk/reset entries are absent
Some boards don't populate clk/reset entries as these are are optional
as per binding documentation. Therefore, don't fail driver probe if
clk/reset entries are absent in DT.

This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx

Fixes: e8e683d33b ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-10-31 12:11:24 +01:00
Keerthy
3135022cb4 gpio: da8xx_gpio: Fix the _gpio_direction_output function
_gpio_direction_output function currently calls gpio_set_value
with the wrong gpio number. gpio_set_value in the uclass driver
expects a different gpio number and the _gpio_direction_output
is currently providing the number specific to the bank.

Hence fix it by calling the _gpio_set_value function instead.

Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci")
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-10-30 17:48:47 -04:00
Tom Rini
412326d1bc Merge tag 'u-boot-clk-23Oct2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
2019-10-30 13:13:46 -04:00
Heinrich Schuchardt
ee5041451e blk: set log2blksz in blk_create_device()
The ext4 file system requires log2blksz to be set. So when setting the
block size on the block descriptor we should fill this field too.

This fixes a problem with EFI block devices providing ext4 partitions, cf.
https://lists.denx.de/pipermail/u-boot/2019-October/387702.html.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-30 17:49:40 +01:00
Tom Rini
700336f7e4 Merge tag 'mmc-10-29-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc driver cleanup
- spl_mmc bug fix to avoid access wrong emmc partition
2019-10-30 09:06:33 -04:00
Tom Rini
cc64810dc6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- H6 dts(i) sync (Clément)
- H6 PIO (Icenowy)
- Fix pll1 clock calculation (Stefan)
- H6 dram, half DQ (Jernej)
- A64 OLinuXino eMMC (Sunil)
2019-10-30 09:04:52 -04:00
Yangbo Lu
5d336d1701 mmc: fsl_esdhc: drop i.MX DDR support code
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.

0e1bf61 mmc: fsl_esdhc: Add support for DDR mode

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:22 +08:00
Yangbo Lu
2913926f3b mmc: fsl_esdhc: remove redundant DM_MMC checking
Remove redundant DM_MMC checking which is already in DM_MMC conditional
compile block.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:21 +08:00
Yangbo Lu
41dec2fe99 mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.

- Drop non-BLK support for DM_MMC introduced by below patch.
  66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled

- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).

- Use DM_MMC instead of BLK for conditional compile.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:21 +08:00
Jean-Jacques Hiblot
d60ae4c59d fdt: Fix alignment issue when reading 64-bits properties from fdt
The FDT specification [0] gives a requirement of aligning properties on
32-bits. Make sure that the compiler is aware of this constraint when
accessing 64-bits properties.

[0]: https://github.com/devicetree-org/devicetree-specification/blob/master/source/flattened-format.rst

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-27 13:01:53 -06:00
Kever Yang
97b5f9d1a0 dm: core: Update log method for uclass_find_device_by_seq
Use log() insted of debug() for uclass_find_device_by_seq function,
since this print is very much and we can filter it out with log()
interface.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move #define to top of file as per docs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-27 13:01:43 -06:00
Simon Glass
5ca5ec1e32 dm: regmap: Fix mask in regmap_update_bits()
This function assumes that the 'val' parameter has no masked bits set.
This is not defined by the function prototype though. Fix the function to
mask the value and update the documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-27 10:56:41 -06:00
Tom Rini
ffc379b42c - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
 - mtmips: add new drivers for clock, reset-controller and pinctrl
 - mtmips: add support for high speed UART
 - mtmips: update/enhance drivers for SPI and ethernet
 - mtmips: add support for MMC
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Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
2019-10-25 20:07:24 -04:00
Tom Rini
15147dc6a9 Merge branch '2019-10-24-ti-imports'
- Enable DFU on dra7xx boards
- Further Keystone 3 platform improvements
2019-10-25 17:33:28 -04:00
Kevin Scholz
3bb3f266ee ram: k3-j721e: Add support for J721E DDR controller
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
James Doublesin
34f27b2e86 ram: k3-am654: Do not rely on default values for certain DDR register
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.

Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
James Doublesin
c78ac7a0c9 ram: k3-am654: add support for LPDDR4 and DDR3L DDRs
Added training support for LPDDR4 and DDR3L DDRs.  Also added/changed
some register configuration to support all 3 DDR types

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
Tom Rini
271103ac0b Merge branch 'master' of git://git.denx.de/u-boot-usb
- DWC3 improvements
- i.MX7 EHCI bugfix
2019-10-25 13:50:51 -04:00
Tom Rini
c9e50bb12a Second set of u-boot-atmel features and fixes for 2020.01 cycle
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Merge tag 'u-boot-atmel-2020.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features and fixes for 2020.01 cycle

This feature set includes Eugen's work on a new tiny flexcom driver and
eeprom mac retrieval for the sam9x60-ek board.
2019-10-25 13:50:33 -04:00
Tom Rini
e382713d22 Xilinx/FPGA changes for v2020.01 part 2
common:
 - Fix manual relocation for repeatable commands
 
 arm:
 - Also clean up generated dtbos
 
 microblaze:
 - Add support for Manual relocation in crypto framework
 - Tune and align architecture bootm support
 
 zynq:
 - DT sync ups
 - Some defconfig updates
 - Remove empty board_early_init_f()
 
 zynqmp:
 - Clean firmware handing via drivers/firmware/
 - DT/defconfig name alignments
 - DT cleanups with using firmware based clock driver
 - Some defconfig updates
 - Add IIO ina226 DT description
 - Tune zynqmp_psu_init_minimalize.sh script
 - Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216
 
 versal:
 - Clean firmware handing via drivers/firmware/
 - Add gpio support
 - Enable DT overlay/USB/CLK/FPGA
 - DT updates
 - Tune mini configuration
 
 spi:
 - gqspi - Remove unused headers
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Merge tag 'xilinx-for-v2020.01-part2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01 part 2

common:
- Fix manual relocation for repeatable commands

arm:
- Also clean up generated dtbos

microblaze:
- Add support for Manual relocation in crypto framework
- Tune and align architecture bootm support

zynq:
- DT sync ups
- Some defconfig updates
- Remove empty board_early_init_f()

zynqmp:
- Clean firmware handing via drivers/firmware/
- DT/defconfig name alignments
- DT cleanups with using firmware based clock driver
- Some defconfig updates
- Add IIO ina226 DT description
- Tune zynqmp_psu_init_minimalize.sh script
- Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216

versal:
- Clean firmware handing via drivers/firmware/
- Add gpio support
- Enable DT overlay/USB/CLK/FPGA
- DT updates
- Tune mini configuration

spi:
- gqspi - Remove unused headers
2019-10-25 11:23:46 -04:00
Weijie Gao
77ebea23c3 mmc: mtk-sd: add a dts property cd-active-high for builtin-cd mode
This patch adds a dts property cd-active-high for builtin-cd mode to make
it configurable instead of using hardcoded active-low.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
3c92a957ee mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCs
This patch adds mmc support for MediaTek MT7620/MT7628 SoCs.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
877d03903c net: mt7628-eth: add support to isolate LAN/WAN ports
This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to
prevent LAN devices from getting IP address from WAN.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
c88ee3ea0a net: mt7628-eth: free rx descriptor on receiving failure
When received a packet with an invalid length recorded in rx descriptor,
we should free this rx descriptor to allow us to continue to receive
following packets.
Without doing so, u-boot will stuck in a dead loop trying to process this
invalid rx descriptor.

This patch adds a call to mt7628_eth_free_pkt() after received an invalid
packet length.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
f079321009 net: mt7628-eth: make phy link up detection optional via DT
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port).
Although in IOT mode only port0 is usable, the phy0 is still connected
to the switch, not the ethernet gmac directly.

This patch rewrites it and makes it optional. It can be turned on by adding
mediatek,poll-link-phy = <?> explicitly into the eth node. By default the
driver is switch mode with all 5 phy ports working without link detection.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
2734fdef5c net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy reset
This patch removes hardcoded gpio settings as they have been replaced by
pinctrl in dts, and also replaces regmap-based phy reset with a more
generic reset controller.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
4cce51141f phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 part
This patch adds slew rate calibration for mt76x8-usb-phy, removes code
which belongs to mt7620, and gets rid of using syscon and regmap by using
clock driver and reset controller.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
f7ae6b682c reset: add reset controller driver for MediaTek MIPS platform
This patch adds reset controller driver for MediaTek MIPS platform and
header file for mt7628.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
3fad441c54 pinctrl: add support for MediaTek MT7628
This patch adds pinctrl support for mt7628, with a file for common pinmux
functions and a file for mt7628 which has additional support for pinconf.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
43405e009b spi: mt7621-spi: restore default register value after each xfer
Currently this driver uses a different way to implement the spi xfer,
by modifying some fields of two registers, which is incompatible with the
MTK's original SDK linux driver. This will cause the flash data being
damaged by the SDK driver.

This patch lets the mt7621_spi_set_cs() restore the original register
fields after cs deactivated.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
54a6b8e793 spi: mt7621-spi: remove data cache and rewrite its xfer function
The mt7621 spi controller supports continuous generic half-duplex spi
transaction. There is no need to cache xfer data at all.

To achieve this goal, the OPADDR register must be used as the first data
to be sent. And follows the eight generic DIDO registers. But one thing
different between OPADDR and DIDO registers is OPADDR has a reversed byte
order.

With this patch, any amount of data can be read/written in a single xfer
function call.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
f09978566b spi: mt7621-spi: use clock frequency from clk driver
This patch lets the spi driver to use clock provided by the clk driver
since the new clk-mt7628 driver provides accurate sys clock frequency.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
77ed3c42fe clk: add clock driver for MediaTek MT76x8 platform
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
44fa676e58 serial: serial_mtk: add non-DM version for SPL
This patch adds non-DM version for mtk hsuart driver and makes it
compatible with ns16550a driver in configuration.
This is needed in SPL with CONFIG_SPL_DM disabled for reducing size.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:43 +02:00
Weijie Gao
99ced5331b serial: serial_mtk: enable FIFO and disable flow control
This patch adds codes to enable FIFO and disable flow control taken from
ns16550 driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:43 +02:00
William Zhang
e365de9051 drivers: nand: brcmnand: fix nand_chip ecc layout structure
The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.

This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-25 17:20:43 +02:00
Álvaro Fernández Rojas
a9f80cf9ad nand: brcm: add BCM6368 support
This adds support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-25 17:20:43 +02:00
Fabio Estevam
395ec74186 spi-nor-ids: Add support for Adesto AT25SL321
Add an entry for the Adesto AT25SL321 SPI NOR chip.

This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Frieder Schrempf
832ce20278 mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTD
Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in
SPL. They often rely on hacks in the board header files to include
this option conditionally. To be able to fix this, we previously
introduced a separate option SPL_SPI_FLASH_MTD.

Therefore we can now adjust the Makefile and change the code in
sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD).

We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the
header files to the according defconfigs. The affected boards are
socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6
and da850evm.

We do this all in one patch to guarantee bisectibility.

This change was tested with buildman to make sure it does not
introduce any regressions by comparing the resulting binary sizes.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
73d74b5881 spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status
register that indicates various errors that may be encountered during
erase/write operations. Therefore add USE_FSR flag wherever missing.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
8651593a8c spi-nor: spi-nor-ids: Add entries for mt25q variants
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
d66e07cdf9 spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and
n25q512* support 4 Byte stateless addressing opcodes. Therefore drop
SPI_NOR_4B_OPCODES flag from these entries

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Ley Foon Tan
e7e05fcb3e spi: designware_spi: Disable and free clock when remove driver
Disable and free clock when remove driver.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
2a2174d3da mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS
U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS.

Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
cc9118757f mtd: spi-nor-core: Use dev_err for reporting erase/write failures
Use dev_err() when reporting reason for erase/write failures so that
users can be made aware of the reason for failure.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Frieder Schrempf
64f736c901 mtd: spi: Add a new option SPL_SPI_FLASH_MTD to Kconfig
To allow SPI_FLASH_MTD being enabled separately in SPL we add a new
option. The only user currently is the stm32mp15_basic board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
dc738248db spi: Kconfig: Enable SPI_SUNXI for SUNXI
SPI_SUNXI driver is fully dm-aware and the Allwinner
architecture kconfig would have logic to enable the
DM_SPI. So, select default spi sunxi driver for
sunxi architecture.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
77df1a9b66 mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASH
DM_SPI_FLASH should require spi flash interface code for dm
version, so imply SPI_FLASH core by default if any board
enabled DM_SPI_FLASH.

This overcome the explicit enablement of CONFIG_SPI_FLASH on
respective boards when DM_SPI_FLASH being used.

Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Bin Meng
4b06000395 dm: spi: Change cs_info op to return -EINVAL for invalid cs num
We need distinguish the following two situations in various SPI APIs:

- given chip select num is invalid
- given chip select num is valid, but no device is attached

Currently -ENODEV is returned for both cases.

For the first case, it's more reasonable to return -EINVAL instead of
-ENODEV for invalid chip select numbers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Bin Meng
4dd520b36b dm: spi: Return 0 if driver does not implement ops->cs_info
If an SPI controller driver does not implement ops->cs_info, that
probably means any chip select number could be valid, hence let's
return 0 for spi_cs_info().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
0c8e605670 spi: Kconfig: Add help text
Add detailed help text for SPI support.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
97009d543d mtd: spi-nor: ids: Add is25wp256 chip
Add is25wp256, chip to spi-nor id table.

Tested on SiFive FU540 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
989fd97fe5 mtd: spi: Kconfig: Update CONFIG_SPI_FLASH
1) CONFIG_SPI_FLASH is not just a legacy code, but it has common
   core code which handle both dm and non-dm spi flash code. So
   fix the info text to make it clear globally.

2) Since it's flash core it shouldn't depends on legacy SPI,
   so remove the 'depends on SPI'

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:42:57 +05:30
Tom Rini
17fd9915a4 Merge branch '2019-10-24-UFS-support'
- Add Universal Flash Storage (UFS) support
2019-10-24 09:51:48 -04:00
Ye Li
235f5e158e ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.

This patch only supports OTG0 with UTMI PHY.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-10-24 15:31:13 +02:00
Igor Opaniuk
1198a104d3 usb: ehci-mx6: Fix bus enumeration for iMX7 SoCs
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed next to each other, and their addresses incremented by 0x10000.

Example of USB nodes for iMX7S/D:

usbotg1: usb@30b10000 {
    compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
    reg = <0x30b10000 0x200>;
           ^^^^^^^^^^
....
usbotg2: usb@30b20000 {
    compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
    reg = <0x30b20000 0x200>;
           ^^^^^^^^^^
....

usbh: usb@30b30000 {
    compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
    reg = <0x30b30000 0x200>;
           ^^^^^^^^^^
....

Which was leading to usb enumeration issues:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000: probe failed, error -22
scanning bus usb@30b10000 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found

Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-10-24 15:31:13 +02:00
Michal Simek
039c740d66 arm64: zynqmp: Switch to xlnx-zynqmp-clk header
Use prepared header instead of hardcoded values.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
T Karthik Reddy
ef92ed26a5 drivers: crypto: rsa_mod_exp: Add manual relocation for ops->mod_exp()
This patch adds manual relocation for Modular Exponentiation if
CONFIG_NEEDS_MANUAL_RELOC is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
3a79c6052a spi: zynqmp: Remove unused platform headers
There is no reason to include clk.h and hardware.h headers.
Driver doesn't require them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Shubhrajyoti Datta
98927daada gpio: zynq: Add gpio driver support for PMC gpio
This patch adds support for gpio driver for pmc gpio.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Ashok Reddy Soma
982485214f gpio: zynq: Add gpio driver support for Versal
This patch adds support for gpio driver for versal platform

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
44dccd5924 firmware: zynqmp: Clean up zynqmp_power_probe
Fix error debug messages to be more accurate and aligned with debug message
style in the whole file.
And do not initialize ret variable because it is initialized later on and
it is just additional step.

Fixes: 1327d1678b ("firmware: zynqmp: Add zynqmp-power support")
Reported-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
9bed8a63f7 firmware: zynqmp: Report error when xilinx_pm_request called from EL3
Function should report error when called in EL3 context. Also report it as
error instead 0 (success).

Reported-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
403619515e arm64: zynqmp: Convert invoke_smc() to xilinx_pm_request()
Remove macros which use PM_SIP_SVC offset and convert invoke_smc() to
xilinx_pm_request() which do calculation with PM_SIP_SVC already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
6596270ecb arm64: versal: Rename versal_pm_request to xilinx_pm_request
Use generic name instead of Versal specific because this should be also
used on ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
866225f394 arm64: xilinx: Move firmware functions from platform to driver
versal_pm_request() and invoke_smc() are almost the same. Only one
difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id.
The patch is moving platform implementation to firmware driver code for
synchronization.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
0f3604a2b3 arm64: versal: Clean pm_api_id usage
Copy enum values from platform code to firmware code. IDs are shared
between ZynqMP and Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Eugen Hristev
f81649586d misc: microchip_flexcom: introduce microchip_flexcom driver
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-24 13:01:57 +03:00
Jean-Jacques Hiblot
2bbc1bbf5d phy: keystone-usb: handle the transition of the USB power domain
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
3e6ab7327f usb: dwc3: Kconfig: get rid of obsolete mode selection
The mode selection for the DWC3 is kind of obsolete. The driver does not
have to be host only or gadget only. This choice is confusing.
All the remaining callers of dwc3_uboot_init() explicitly set dr_mode
before calling the function, so none rely on a default behavior.

Remove the choice menu and keep only the USB_DWC3_GADGET option. Enable it
by default if USB_GADGET and USB_DWC3 are enabled.
It must be disabled for the evb-rk3328 as it uses DWC2 for the gadget and
DWC3 for the host.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
ba6c5f7a28 usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1a63e5e5fb usb: dwc3-generic: if no max speed is specified in DT, assume super speed
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
b575e90916 usb: dwc3-generic: add a new host driver that uses the dwc3 core
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".

In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1af590df16 usb: dwc3-generic: factorize code
Factor code for re-usability.
This is another step toward adding host support.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
3a38a0adb9 usb: dwc3-generic: use platdata
Separate platform data from the private data.
This is one step toward adding host support.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
33a99b4365 usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1708a12377 usb: xhci: move xhci.h to include usb
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
bbe3d4a6c1 usb: dwc3: switch to peripheral mode when exiting
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:16 +02:00
Jean-Jacques Hiblot
a8973731a4 usb: host: remove the xhci-zynqmp driver
This driver is not used anymore.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:16 +02:00
Vignesh Raghavendra
c2dfd0a4d8 mtd: Add TI HyperBus Memory Controller driver
AM654/J721e has HyperBus Memory Controller that supports HyperFlash and
HyperRAM devices. It provides a memory mapped interface to interact with
these devices. Add a driver to support the same.
Driver calibrates the controller, setups up for MMIO access and probes
HyperFlash child node.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-24 09:49:10 +02:00
Vignesh Raghavendra
d75eacf9b8 mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-24 09:48:53 +02:00
Faiz Abbas
4390eaf676 ufs: Add glue layer driver for TI J721E devices
Add glue layer driver for the controller present on TI's J721E devices.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
ef5fb5a84c ufs: Add Support for Cadence platform UFS driver
Add Support for the platform driver for the Cadence device present on
TI's J721e device.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
7feafb0ae4 ufs: Add Initial Support for UFS subsystem
Add Support for UFS Host Controller Interface (UFSHCI) for communicating
with Universal Flash Storage (UFS) devices. The steps to initialize the
host controller interface are the following:

- Initiate the Host Controller Initialization process by writing to the
Host controller enable register.
- Configure the Host Controller base address registers by allocating a
host memory space and related data structures.
- Unipro link startup procedure
- Check for connected device
- Configure UFS host controller to process requests

Also register this host controller as a SCSI host controller.

Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported to
U-boot.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
8fbac8e23e scsi: Add dma direction member to command structure
Some SCSI devices like UFS use DMA for executing scsi commands and hence
need to know the direction of transfer of the dma. Add a dma_dir element
to the command structure to facilitate this.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
d48f00ed11 scsi: Retry inquiry 3 times to overcome Unit Attention condition
The UFS SCSI device LUNs are observed to return failure the first time a
unit ready inquiry is sent and pass on the second try. Send this
inquiry 3 times to make sure device is ready.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
4ff572830e scsi: Add max_bytes_per_req to scsi_platdata
Add max_bytes_per_req to scsi_platdata to enable the host driver to limit
the number of bytes that can be read/written per request.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
66c54f1a3e scsi: Simplify scsi_read()/_write()
With no non-DM driver using scsi_read()/_write() APIs, remove
the legacy implementations.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
[trini: Reorder slightly and mark scsi_read/write behind BLK test to
avoid warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-23 20:47:12 -04:00
Jean-Jacques Hiblot
9a52be129c test: clk: test clock self assignment
Make sure that the clock self-assignment works by having a clock of
clk-sbox be configured automatically when clk-sbox is probed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
fd1ba29652 drivers: clk: Fix using assigned-clocks in the node of the clock it sets up
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.

example:
muxed_clock: muxed_clock {
	clocks = <&clk_provider 0>, <&clk_provider 1>;
	#clock-cells = <0>;
	assigned-clocks = <&muxed_clock>;
	assigned-clock-parents = <&clk_provider 1>;
};

It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
dd2e0ce2a4 test: clk: Update tests to also check the managed API
Add a few more clocks the clk_sandbox clock provider and get them using
the managed API.
Make sure they are released when the device is removed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
52720c536f drivers: clk: Add a managed API to get clocks from the device-tree
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
8a1661f20e drivers: clk: Handle gracefully NULL pointers
Prepare the way for a managed CLK API by handling NULL pointers without
crashing nor failing.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Lukasz Majewski
727fa4539c clk: Add support for I2C clocks on NXP's imx6q SoC which use CCF
This change adds support for I2C clock modeled in CCF. This code intention
is to only enable those clocks in the I2C driver with default settings.
For that reason the "busy" versions of clocks reuse the generic approach
and would need to be updated when one wants to adjust the I2C clock
frequency in U-Boot.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
02e2a2ad2f clk: Fix error check in clk_set_default_parents()
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Patrick Delaunay
44510daea4 dm: pinctrl: fix for introduce PINCONF_RECURSIVE option
Correct the name of the define used CONFIG_IS_ENABLED which is
not aligned with Kconfig name: CONFIG_$(SPL_)PINCONF_RECURSIVE.

The recursive calls is conditional only for UCLASS_PINCONFIG
"pinconfig" driver.
It is always needed to call pinctrl_post_bind for UCLASS_PINCTRL
"pinctrl", the test CONFIG_IS_ENABLED(PINCONF_RECURSIVE) need to
be removed for this driver.

This correct a regression introduced because the same patch is
applied twice times in u-boot-dm branch:
- commit e878b53a79 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")
- commit c20851b3d8 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-21 09:40:54 -04:00
Patrick Delaunay
ae799ffcae pinctrl: Kconfig: remove duplicated nodes
Remove the duplicated configs introduced when the same patch is
applied twice times:
- commit e878b53a79 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")
- commit c20851b3d8 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-21 09:40:50 -04:00
Tom Rini
3b985bdeab - document alternative libretech-cc installation methods, including upstream TF-A and opensource tools
- add HDMI/CVBS display support for Amlogic G12A SoCs and SEI510 board
 - add support for Amlogic A311D based Khadas VIM3
 - add support for Amlogic S905X3 based SEI610 board, targeting Android support like SEI510
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Merge tag 'u-boot-amlogic-20191018' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- document alternative libretech-cc installation methods, including upstream TF-A and opensource tools
- add HDMI/CVBS display support for Amlogic G12A SoCs and SEI510 board
- add support for Amlogic A311D based Khadas VIM3
- add support for Amlogic S905X3 based SEI610 board, targeting Android support like SEI510
2019-10-18 16:36:44 -04:00
Neil Armstrong
a990c390a3 power: domain: add Amlogic Everything-Else power domain driver
Based on the 54ecb8f7028c ("Linux 5.4-rc1") Everything-Else power domain
driver for Amlogic SoCs.

This driver handles the VPU Power domain and other domains from the
Everything-Else part of the SM1 and G12A SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:33:21 +02:00
Neil Armstrong
2168a52e2b clk: meson-sm1: add compatible
The SM1 clock controller is almost identical to the G12A and
so far the differences don't matter.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:26:59 +02:00
Neil Armstrong
a10388dc69 mmc: meson-gx: add support for mmc-pwrseq-emmc
Add support for mmc-pwrseq-emmc in the meson-gx mmc driver to support
enabling the eMMC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:24:05 +02:00
Neil Armstrong
04eb4f45c1 video: meson: add compatible for Amlogic G12A
Finally add the Amlogic G12A SoC compatible for the VPU driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 11:45:36 +02:00
Neil Armstrong
573687c3be video: meson: sync with linux drm-misc tree
Synchronize the Amlogic Meson Video driver back with the latest
DRM misc tree, adding G12A platform support, from the latest commit:
528a25d040bc ("drm: meson: use match data to detect vpu compatibility")

The sync includes the following changes from Linux adapted to U-Boot:
- Add support for VIC alternate timings
- Switch PLL to 5.94GHz base for 297Mhz pixel clock
- Add registers for G12A SoC
- Add G12A Support for VPP setup
- Add G12A Support for VIU setup
- Add G12A support for OSD1 Plane
- Add G12A support for plane handling in CRTC driver
- Add G12A support for CVBS Encoder
- Add G12A Video Clock setup
- Add G12A support for the DW-HDMI Glue
- fix G12A HDMI PLL settings for 4K60 1000/1001 variations
- fix primary plane disabling
- fix G12A primary plane disabling
- mask value when writing bits relaxed
- crtc: drv: vpp: viu: venc: use proper macros instead of magic constants
- global clean-up
- add macro used to enable HDMI PLL
- venc: set the correct macrovision max amplitude value

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 11:42:55 +02:00
Neil Armstrong
0a3561119f video: meson: remove power domain get
Remove getting and enabling the node power domain since it's now handled
by the dm core directly.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Neil Armstrong
a0513b40cc clk: meson: g12a: add support for VPU/HDMI clocks
Add necessary clock support to set up clock for the VPU and
HDMI support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Neil Armstrong
3dcdf85efd power: domain: meson-gx-pwrc: add G12A support
Add Amlogic G12A support for the gx-pwrc driver, aligned on the
Linux v5.2 driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Sagar Shrikant Kadam
d26b40450b gpio: sifive: add support for DM based gpio driver for FU540-SoC
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.

This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra <wesley@sifive.com> and/or Atish Patra
<atish.patra@wdc.com> (many thanks !!). The linux driver can be referred
here [1]

[1]: https://lkml.org/lkml/2018/10/9/1103

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-18 09:04:01 +08:00
Tom Rini
a2fce50455 Merge tag 'for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-ubi
ubi enhancements for 2020.01
- provide a way for skipping crc checks ported from linux, and add an
  U-Boot command to set this flag on already installed systems.
- fix redundand environment management
2019-10-17 07:26:16 -04:00
Stefan Roese
524acec47c ubi: Print skip_check in ubi_dump_vol_info()
It might be interesting, if "skip_check" is set or not, so lets print
this flag in ubi_dump_vol_info() as well.

hs: fix typo in commit message

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-10-16 05:42:27 +02:00
Quentin Schulz
386f20cade ubi: provide a way to skip CRC checks
Some users of static UBI volumes implement their own integrity check,
thus making the volume CRC check done at open time useless. For
instance, this is the case when one use the ubiblock + dm-verity +
squashfs combination, where dm-verity already checks integrity of the
block device but this time at the block granularity instead of verifying
the whole volume.

Skipping this test drastically improves the boot-time.

Adapted to U-Boot by Stefan Roese.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
2019-10-16 05:42:27 +02:00
Patrick Delaunay
2a43dbdf96 dm: Tidy up dump output when there are many devices
At present the 'Index' column of 'dm tree' assumes there is
two digits, this patch increase it to 3 digits.

It also aligns output of 'dm uclass', assuming the same 3 digits index.

The boards with CONFIG_PINCTRL_FULL activated have one pinconfig
by pin configuration, so they can have more than 100 devices
pinconfig (for example with stm32mp157c-ev1 board we have
106 pinconfig node).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Patrick Delaunay
e878b53a79 dm: pinctrl: introduce PINCONF_RECURSIVE option
In the Linux pinctrl binding, the pin configuration nodes don't need to
be direct children of the pin controller device (may be grandchildren for
example). This behavior is managed with the pinconfig u-class which
recursively bind all the sub-node of the pin controller.

But for some binding (when pin configuration is only children of pin
controller) that is not necessary. U-Boot can save memory and reduce
the number of pinconf instance when this feature is deactivated
(for arch stm32mp for example for SPL).

This patch allows to control this feature with a new option
CONFIG_PINCONF_RECURSIVE when it is possible for each individual
pin controller device.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixed CONFIG_IF_ENABLED() condition, added __maybe_unused:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Anatolij Gustschin
52edfed65d dm: core: device: switch off power domain after device removal
The power domain associated with a device is enabled when probing,
but currently the domain remains enabled when the device is removed.
Some boards started to disable power domains for selected devices
via custom board_quiesce_devices(), but it doesn't work in many
cases, i. e. because devices still can be accessed later in
.remove() callback on behalf of dm_remove_devices_flags().

Utilize the DM core to power off the device power domain, but add a
device flag to be able to selectively let the power domain enabled
after device removal. This might be required for devices that must
remain enabled when booting OS, i. e. serial console for debug
output, etc.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Lokesh Vutla
0cf795a802 power: domain: Introduce dev_power_domain_off
Add dev_power_domain_off() api to disable all the power-domains
corresponding to a device

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Lokesh Vutla
af17b0dad5 remoteproc: k3_arm64: Enable DM_FLAG_DEFAULT_PD_CTRL_OFF
Enable DM_FLAG_DEFAULT_PD_CTRL_OFF for arm64 remote core so that
pd can be enabled after loading the image.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Lokesh Vutla
af94ad418d dm: core: Allow for not controlling the power-domain by DM framework
In some remoteproc cases, enabling the power domain of the core will
start running the core. In such cases image should be loaded before
enabling the power domain. But the current DM framework enables the
power-domain by default during probe. This is causing the remotecore
to start and crash as there is no valid image loaded.

In order to avoid this introduce a DM flag that doesn't allow for
enabling/disabling the power-domain by DM framework.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Michael Trimarchi
36a90eda84 dm: pinctrl: Skip not associated gpio phandle and rise a warning message
Skip not associated gpio phandle let register the other gpios on a group.
We need anyway to send out a warning to the user to fix their uboot-board.dtsi.
Thhe handle id can be found inside the decompiled dtb

dtc -I dtb -O dts -o devicetree.dts spl/u-boot-spl.dtb

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Peng Fan
f0cc4eae9a core: device: use dev_power_domain_on
When multiple power domains attached to a device, need power on
them all, so use dev_power_domain_on to do that.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-15 08:40:02 -06:00
Peng Fan
9c1e982218 power: domain: add dev_power_domain_on
Add this new API to power on multiple domains attached
to a device.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Changed to static inline and added a condition into C file:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Thomas Fitzsimmons
640abba507 dm: spi: Do not assume first SPI bus
When CONFIG_OF_PRIOR_STAGE is enabled, this workaround was needed
before device_bind_common assigned request numbers sequentially in the
absence of aliases.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Thomas Fitzsimmons
7f3289bf6d dm: device: Request next sequence number
For CONFIG_OF_PRIOR_STAGE, in the absence of a device tree alias for a
given device, use the next request number for that type of device.
This allows aliases to be used when they're available, while still
allowing unaliased devices to be probed.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Kayla Theil
d8206ff198 tpm2: Don't assume active low reset value
The reset function sets the pin to 0 then 1 but if the pin is marked
ACTIVE_LOW in the DT it gets inverted and leaves the TPM in reset.
Let the gpio driver take care of the reset polarity.

Signed-off-by: Kayla Theil <kayla.theil@mixed-mode.de>
2019-10-15 08:40:02 -06:00
Patrick Delaunay
c20851b3d8 dm: pinctrl: introduce PINCONF_RECURSIVE option
In the Linux pinctrl binding, the pin configuration nodes don't need to
be direct children of the pin controller device (may be grandchildren for
example). This behavior is managed with the pinconfig u-class which
recursively bind all the sub-node of the pin controller.

But for some binding (when pin configuration is only children of pin
controller) that is not necessary. U-Boot can save memory and reduce
the number of pinconf instance when this feature is deactivated
(for arch stm32mp for example for SPL).

This patch allows to control this feature with a new option
CONFIG_PINCONF_RECURSIVE when it is possible for each individual
pin controller device.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Tom Rini
6f1f28b8e1 u-boot-imx-20191014
-------------------
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
 
 	- logicpd pinmux
 	- i.MX7ULP: imx_ddr_size
 	- fixes Toradex i.MX6/i.MX7
 	- pico-imx7d
 	- tpc70 converted to DM
 	- New Board: meerkat96
 	- add HAB version command
 	- i.MX8 :
       		imx8: Jump from alias to OCRAM address at SPL init
       		imx8qm/qxp: Set SPL TEXT base to OCRAM base
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Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191014
-------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628

	- logicpd pinmux
	- i.MX7ULP: imx_ddr_size
	- fixes Toradex i.MX6/i.MX7
	- pico-imx7d
	- tpc70 converted to DM
	- New Board: meerkat96
	- add HAB version command
	- i.MX8 :
      		imx8: Jump from alias to OCRAM address at SPL init
      		imx8qm/qxp: Set SPL TEXT base to OCRAM base
2019-10-14 13:00:51 -04:00
Tom Rini
cd5ffc5de5 - panel bridge support in stm32 ltdc
- DSI host uclass
 - sandbox DSI host uclass test driver and DSI host test
 - MIPI DSI helpers
 - Synopsys Designware MIPI DSI host bridge driver
 - STM32 DSI controller driver
 - OTM800A and RM68200 panel support
 - DSI host updates for stm32f769 and stm32mp1 dtsi files
 - splash screen for stm32f769 and stm32mp1 boards
 - stm32 defconfig updates for display support
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Merge tag 'video-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- panel bridge support in stm32 ltdc
- DSI host uclass
- sandbox DSI host uclass test driver and DSI host test
- MIPI DSI helpers
- Synopsys Designware MIPI DSI host bridge driver
- STM32 DSI controller driver
- OTM800A and RM68200 panel support
- DSI host updates for stm32f769 and stm32mp1 dtsi files
- splash screen for stm32f769 and stm32mp1 boards
- stm32 defconfig updates for display support
2019-10-14 07:30:16 -04:00
Tom Rini
fae7948011 Merge tag 'mmc-10-10-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- Add sdhci driver for Broadcom iProc platform
- Add a driver callback for power-cycle for mmc
- Implement host_power_cycle callback for stm32_sdmmc2
- spl: dm_mmc: Initialize only the required mmc device
2019-10-14 07:28:32 -04:00
Peng Fan
d02be21d30 i2c: imx_lpi2c: add ipg clk
The controller needs two clk, per clk and ipg clk,
so let's add ipg clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-14 09:31:41 +02:00
Yannick Fertré
06ef131d30 video: add support of panel RM68200
Support for Raydium RM68200 720p dsi 2dl video mode panel.
This rm68200 panel driver is based on the Linux Kernel driver from
drivers/gpu/drm/panel/panel-raydium-rm68200.c.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 23:38:36 +02:00
Yannick Fertré
78157b2fa5 video: add support of panel OTM8009A
Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 23:38:26 +02:00
Yannick Fertré
18b6ca5c5a video: add support of STM32 MIPI DSI controller driver
Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 23:38:12 +02:00
Yannick Fertré
d4f7ea83fc video: add MIPI DSI host controller bridge
Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 23:37:08 +02:00
Yannick Fertré
23f965a4c6 dm: Add a dsi host uclass
Display Serial Interface (DSI) host can usefully be modelled
as their own uclass.
DSI defines a serial bus and a communication protocol
between the host and the device (panel, bridge).

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 23:34:43 +02:00
Yannick Fertré
66c3724656 video: add support of MIPI DSI interface
Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 21:24:47 +02:00
Yannick Fertré
aeaf330649 video: stm32: stm32_ltdc: add bridge to display controller
Manage a bridge insert between the display controller & a panel.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
2019-10-13 21:24:47 +02:00
Tom Rini
9189d6f1e9 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Remember the device being emulated for Sandbox PCI
- Update Kconfig options for FSP 1.0
- Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
2019-10-12 10:52:48 -04:00
Tom Rini
0c9cc5155c Merge branch '2019-10-11-master-imports'
- Assorted cleanups
- FAT bugfixes
- mediatek platform updates
2019-10-12 10:10:59 -04:00
Tero Kristo
260777fc23 clk: cdce9xx: add support for cdce9xx clock synthesizer
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-10-11 13:32:39 -04:00
Lokesh Vutla
e704cd6466 mmc: am654_sdhci: Drop a redundant power_domain_on in probe
Power-domain is enabled by default in device_probe. am654 mmc driver
is enabling power-domain again in probe. As the second call is
redundant, drop power_domain_on from probe.

Tested-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-10-11 13:31:18 -04:00
Patrice Chotard
e8e9715df2 regulator: fixed: Modify enable-active-high behavior
Regulator should not be enabled at probe time if regulator-boot-on
property is not in the dt node.

"enable-active-high" property is only used to indicate the GPIO
polarity.

See kernel documentation :
 - Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
 - Documentation/devicetree/bindings/regulator/gpio-regulator.yaml

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-10-11 10:10:19 -04:00
Oleksandr Rybalko
5b7a2bf318 ata: ahci: Don't forget to clear upper address regs.
In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
2019-10-11 10:10:19 -04:00
Oleksandr Rybalko
25643a5c3e ahci-pci: ASM1061 report wrong class, but support AHCI.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
2019-10-11 10:10:18 -04:00
Ryder Lee
235bad02e5 phy: mediatek: add MediaTek T-PHY support for PCIe
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now
we just enable PCIe. As for the other functionalities will be
added gradually in upcoming days.

This is adapted from the Linux version.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11 10:10:18 -04:00
Ryder Lee
42d37450e5 pci: mediatek: add PCIe controller support for MT7623
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-10-11 10:09:58 -04:00
Kursad Oney
b47f4891e5 spi: bcm63xx_hsspi: Continue init when using no reset and fixed-clock.
The Broadcom ARM implementations do not yet have a clock framework so
one can use a fixed clock as the root clock of the hsspi block. The
fixed clock does not have an "enable" routine, since it's always
enabled. So when we hit this issue, getting an ENOSYS return, do not
bail but continue initialization.

Similarly the block might already have been out of reset, say, when
we are booting from a SPI device. So if the reset signal is not configured
in the device tree, do not bail out and instead skip deasserting the reset.

Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-11 10:09:16 -04:00
Kursad Oney
3ae64e8f25 spi: bcm63xx_hsspi: switch to raw I/O functions.
Make the driver compatible with both big and little endian SOCs.
Replace big-endian calls with their raw equivalents, expect for
writing the command to FIFO. That still has to be in big-endian
format.

Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-11 10:09:16 -04:00
Kursad Oney
9a3eddd263 spi: hsspi: allow to be used on bcm6858 and bcm63158
This IP exists in both MIPS and ARM cores, so we also
allow to use this driver on bcm6858 and bcm63158.

Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-11 10:09:16 -04:00
Lokesh Vutla
ab827b3857 remoteproc: Introduce K3 C66 and C71 remoteproc driver
Certain SoCs with K3 architecture have integrated a C66 Corepac DSP
subsystem and an advanced C71 DSPs. Introduce a remoteproc driver
that that does take care of loading an elf to any of the specified
DSPs and start it.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
4c850356a8 remoteproc: Introduce K3 remoteproc driver for R5F subsystem
SoCs with K3 architecture have an integrated Arm Cortex-R5F subsystem
that is comprised of dual-core Arm Cortex-R5F processor cores. This R5
subsytem can be configured at boot time to be either run in a LockStep
mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
This subsystem has each Tightly-Coupled Memory (TCM) internal memories
for each core split between two banks - TCMA and TCMB.

Add a remoteproc driver to support this subsystem to be able to load
and boot the R5 cores primarily in LockStep mode or split mode.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
f7954828b8 remoteproc: tisci_proc: Add helper api for controlling core power domain
Power domain for the remote cores needs to be handled in a right
sequence as mandated by the spec. Introduce tisci helper apis
that can control power-domains of remote cores. TISCI clients
can use this api and control the remote cores power domain instead
of hooking it to power-domain layer.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
81e39fbd92 remoteproc: elf_loader: Introduce rproc_elf_get_boot_addr() api
Introduce rproc_elf_get_boot_addr() that returns the entry point of
the elf file. This api auto detects the 64/32 bit elf file and returns
the boot addr accordingly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
856c0ad413 remoteproc: elf_loader: Introduce a common elf loader and checker functions
Introduce a common remoteproc elf loader and checker functions that
automatically detects the 64 bit elf file or 32 bit elf file and
loads/checks the sections accordingly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
e3c4d6f01f remoteproc: elf-loader: Add 64 bit elf loading support
The current rproc-elf-loader supports loading of only 32 bit elf files.
Introduce support for loading of 64 bit elf files in rproc-elf-loader.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
14d963d1b5 remoteproc: elf_loader: Always check the validity of the image before loading
rproc_elf32_load_image() rely on user to send a valid address for elf loading.
Instead do a sanity check on the address passed by user. This will help
all rproc elf users to not call sanity_check explicitly before calling
elf_loading.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11 10:07:34 -04:00
Lokesh Vutla
c08eb93626 remoteproc: ops: Add elf section size as input parameter to device_to_virt api
Introduce a new parameter "size" that accepts size of the region to
remoteproc ops callback device_to_virt(). This can enforce more checks
on the region that device_to_virt() is dealing with.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Fabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com>
2019-10-11 10:07:33 -04:00
Lokesh Vutla
240b932010 dm: core: Add a function to count the children of a device
Add a function to count the available children of a device.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:33 -04:00
Simon Glass
6498fda140 sandbox: pci: Remember the device being emulated
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11 17:37:15 +08:00
Yann Gautier
a8ef8b2289 mmc: stm32_sdmmc2: implement host_power_cycle callback
For the correct power cycle sequence with stm32_sdmmc2, the write of the
power cycle value in PWRCTL field of SDMMC_POWER register is now done in
stm32_sdmmc2_host_power_cycle() and no more in stm32_sdmmc2_pwrcycle().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-10-10 10:59:48 +08:00
Yann Gautier
3602a56ac6 mmc: add a driver callback for power-cycle
Some MMC peripherals require specific power cycle sequence, where some
registers need to be written between the regulator is turned off and then
back on. This is the case for the MMC IP embedded in STM32MP1 SoC.

In STM32MP157 reference manual [1], the power cycle sequence is:
1. Reset the SDMMC with the RCC.SDMMCxRST register bit. This will reset
the SDMMC to the reset state and the CPSM and DPSM to the Idle state.
2. Disable the Vcc power to the card.
3. Set the SDMMC in power-cycle state. This will make that the
SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are driven low, to prevent the card
from being supplied through the signal lines.
4. After minimum 1ms enable the Vcc power to the card.
5. After the power ramp period set the SDMMC to the power-off state for
minimum 1ms. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are set to
drive “1”.
6. After the 1ms delay set the SDMMC to power-on state in which the
SDMMC_CK clock will be enabled.
7. After 74 SDMMC_CK cycles the first command can be sent to the card.

The step 3. cannot be handled by the current framework implementation.
A new callback (host_power_cycle) is created, and called in
mmc_power_cycle(), after mmc_power_off().

The incorrect power cycle sequence has shown some boot failures on
STM32MP1 with some SD-cards, especially on cold boots when the input
frequency is low (<= 25MHz).
Those failures are no more seen with this correct power cycle sequence.

[1] https://www.st.com/resource/en/reference_manual/DM00327659.pdf

Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-10-10 10:59:48 +08:00
Arun Parameswaran
36645f45a0 drivers: mmc: Add sdhci driver for Broadcom iProc platform
Add SDHCI driver for iProc family of Broadcom devices.

Signed-off-by: Corneliu Doban <corneliu.doban@broadcom.com>
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Pavithra Ravi <pavithra.ravi@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
2019-10-10 10:59:48 +08:00