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https://github.com/AsahiLinux/u-boot
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Xilinx fixes for v2020.04-rc4
- Fix link good bit handling in dp83867 - Rename generic Zynq defconfig - Fix zybo z7 low leve setup - Fix error path in zynq_gem driver and fix 64bit usage - Fix invalid clock name quieries for Versal - Fix zynq/zynqmp SPL low level configuration via DT selection -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXlywqgAKCRDKSWXLKUoM IWNzAJ0fVSiXix2p49pKgI8N0f0SU/QPAACfTE+auG3EEmq7WfoXXvK+bzsI4eQ= =oFil -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx fixes for v2020.04-rc4 - Fix link good bit handling in dp83867 - Rename generic Zynq defconfig - Fix zybo z7 low leve setup - Fix error path in zynq_gem driver and fix 64bit usage - Fix invalid clock name quieries for Versal - Fix zynq/zynqmp SPL low level configuration via DT selection
This commit is contained in:
Tom Rini
commit
bd7bb38699
11 changed files with 50 additions and 14 deletions
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@ -5,3 +5,4 @@ F: arch/arm/dts/zynq-*
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F: board/xilinx/zynq/
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F: include/configs/zynq*.h
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F: configs/zynq_*_defconfig
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F: configs/xilinx_zynq_*
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@ -13,6 +13,11 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F
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$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
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endif
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DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
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ifeq ($(DEVICE_TREE),)
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DEVICE_TREE := unset
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endif
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ifeq ($(init-objs),)
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hw-platform-y :=$(shell echo $(DEVICE_TREE))
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init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
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@ -219,8 +219,8 @@ static unsigned long ps7_mio_init_data_3_0[] = {
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EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
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EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
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EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
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EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
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EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
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EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
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EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
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EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
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EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
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EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
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@ -13,6 +13,11 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN
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$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
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endif
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DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
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ifeq ($(DEVICE_TREE),)
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DEVICE_TREE := unset
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endif
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ifeq ($(init-objs),)
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hw-platform-y :=$(shell echo $(DEVICE_TREE))
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init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
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@ -6,7 +6,7 @@ CONFIG_DM_GPIO=y
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CONFIG_SPL_STACK_R_ADDR=0x200000
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CONFIG_SPL=y
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CONFIG_DEBUG_UART_BASE=0xe0001000
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CONFIG_DEBUG_UART_CLOCK=50000000
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CONFIG_DEBUG_UART_CLOCK=100000000
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CONFIG_DEBUG_UART=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_SYS_CUSTOM_LDSCRIPT=y
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@ -571,6 +571,12 @@ static void versal_get_clock_info(void)
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continue;
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clock[i].valid = attr & CLK_VALID_MASK;
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/* skip query for Invalid clock */
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ret = versal_is_valid_clock(i);
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if (ret != CLK_VALID_MASK)
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continue;
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clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
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CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
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nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
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@ -1120,12 +1120,15 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
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static void arasan_check_ondie(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct nand_config *nand = nand_get_controller_data(nand_chip);
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struct nand_drv *info = nand_get_controller_data(nand_chip);
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struct nand_config *nand = &info->config;
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u8 maf_id, dev_id;
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u8 get_feature[4];
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u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
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u32 i;
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nand_chip->select_chip(mtd, 0);
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/* Send the command for reading device ID */
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nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
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@ -1150,10 +1153,12 @@ static void arasan_check_ondie(struct mtd_info *mtd)
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for (i = 0; i < 4; i++)
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get_feature[i] = nand_chip->read_byte(mtd);
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if (get_feature[0] & ENABLE_ONDIE_ECC)
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if (get_feature[0] & ENABLE_ONDIE_ECC) {
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nand->on_die_ecc_enabled = true;
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else
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printf("On-DIE ECC Enabled\n");
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} else {
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printf("%s: Unable to enable OnDie ECC\n", __func__);
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}
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/* Use the BBT pattern descriptors */
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nand_chip->bbt_td = &bbt_main_descr;
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@ -65,6 +65,7 @@
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#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
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#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
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#define DP83867_PHYCR_RESERVED_MASK BIT(11)
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#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
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#define DP83867_MDI_CROSSOVER 5
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#define DP83867_MDI_CROSSOVER_MDIX 2
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#define DP83867_PHYCTRL_SGMIIEN 0x0800
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@ -284,6 +285,9 @@ static int dp83867_config(struct phy_device *phydev)
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val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
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val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
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/* Do not force link good */
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val &= ~DP83867_PHYCR_FORCE_LINK_GOOD;
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/* The code below checks if "port mirroring" N/A MODE4 has been
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* enabled during power on bootstrap.
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*
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@ -655,14 +655,16 @@ static int zynq_gem_probe(struct udevice *dev)
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return -ENOMEM;
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memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
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u32 addr = (ulong)priv->rxbuffers;
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ulong addr = (ulong)priv->rxbuffers;
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flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
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barrier();
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/* Align bd_space to MMU_SECTION_SHIFT */
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bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
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if (!bd_space)
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return -ENOMEM;
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if (!bd_space) {
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ret = -ENOMEM;
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goto err1;
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}
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mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
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BD_SPACE, DCACHE_OFF);
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@ -674,7 +676,7 @@ static int zynq_gem_probe(struct udevice *dev)
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ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
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if (ret < 0) {
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dev_err(dev, "failed to get clock\n");
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return -EINVAL;
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goto err1;
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}
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priv->bus = mdio_alloc();
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@ -684,9 +686,19 @@ static int zynq_gem_probe(struct udevice *dev)
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ret = mdio_register_seq(priv->bus, dev->seq);
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if (ret)
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return ret;
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goto err2;
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return zynq_phy_init(dev);
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ret = zynq_phy_init(dev);
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if (ret)
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goto err2;
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return ret;
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err2:
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free(priv->rxbuffers);
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err1:
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free(priv->tx_bd);
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return ret;
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}
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static int zynq_gem_remove(struct udevice *dev)
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@ -41,8 +41,6 @@
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# define CONFIG_BOOTP_MAY_FAIL
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#endif
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/* QSPI */
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/* NOR */
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#ifdef CONFIG_MTD_NOR_FLASH
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# define CONFIG_SYS_FLASH_BASE 0xE2000000
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