mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
Merge branch '2019-10-24-ti-imports'
- Enable DFU on dra7xx boards - Further Keystone 3 platform improvements
This commit is contained in:
Tom Rini
commit
15147dc6a9
44 changed files with 39198 additions and 28 deletions
|
|
@ -32,3 +32,20 @@
|
|||
&mmc2_iodelay_hs200_rev20_conf {
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||||
u-boot,dm-spl;
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||||
};
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||||
|
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&omap_dwc3_1 {
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||||
u-boot,dm-spl;
|
||||
};
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||||
|
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&usb1 {
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u-boot,dm-spl;
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dr_mode = "peripheral";
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||||
};
|
||||
|
||||
&usb2_phy1 {
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u-boot,dm-spl;
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};
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&usb3_phy1 {
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u-boot,dm-spl;
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};
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|
|
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|||
|
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@ -44,3 +44,20 @@
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&mmc2_iodelay_hs200_rev20_conf {
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u-boot,dm-spl;
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};
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|
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&omap_dwc3_1 {
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u-boot,dm-spl;
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};
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&usb1 {
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u-boot,dm-spl;
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dr_mode = "peripheral";
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};
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&usb2_phy1 {
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u-boot,dm-spl;
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};
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&usb3_phy1 {
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u-boot,dm-spl;
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};
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|
|
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|||
|
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@ -44,3 +44,20 @@
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&mmc2_iodelay_hs200_rev20_conf {
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u-boot,dm-spl;
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};
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&omap_dwc3_1 {
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u-boot,dm-spl;
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};
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&usb1 {
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u-boot,dm-spl;
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dr_mode = "peripheral";
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};
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&usb2_phy1 {
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u-boot,dm-spl;
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};
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&usb3_phy1 {
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u-boot,dm-spl;
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};
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|
|
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23
arch/arm/dts/dra72-evm-u-boot.dtsi
Normal file
23
arch/arm/dts/dra72-evm-u-boot.dtsi
Normal file
|
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "omap5-u-boot.dtsi"
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&omap_dwc3_1 {
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u-boot,dm-spl;
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};
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&usb1 {
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u-boot,dm-spl;
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dr_mode = "peripheral";
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};
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|
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&usb2_phy1 {
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u-boot,dm-spl;
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||||
};
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|
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&usb3_phy1 {
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u-boot,dm-spl;
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||||
};
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|
|
@ -24,3 +24,20 @@
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&mmc2_iodelay_hs200_conf {
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u-boot,dm-spl;
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};
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&omap_dwc3_1 {
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u-boot,dm-spl;
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};
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&usb1 {
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u-boot,dm-spl;
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dr_mode = "peripheral";
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};
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|
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&usb2_phy1 {
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u-boot,dm-spl;
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};
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|
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&usb3_phy1 {
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u-boot,dm-spl;
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};
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|
|
|
|||
|
|
@ -74,6 +74,8 @@
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<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
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<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
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||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
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||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
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<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
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||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
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||||
|
|
@ -86,6 +88,8 @@
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|||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
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<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
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||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
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||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
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||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
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||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
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||||
|
|
|
|||
|
|
@ -1,15 +1,16 @@
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|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
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||||
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* This file was generated by the AM65x_DRA80xM EMIF Tool:
|
||||
* This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
|
||||
* http://www.ti.com/lit/pdf/spracj0
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||||
* Configuration Parameters
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||||
* Memory Type: DDR4
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* Data Rate: 1600
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* Data Rate: 1600 MT/s
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||||
* ECC Enabled: No
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* Data Width: 32
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* Data Width: 32 bits
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*/
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#define DDR_PLL_FREQUENCY 400000000
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#define DDRSS_V2H_CTL_REG 0x000073FF
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#define DDRCTL_MSTR 0x41040010
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#define DDRCTL_RFSHCTL0 0x00210070
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#define DDRCTL_ECCCFG0 0x00000000
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|
|
@ -32,10 +33,10 @@
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|||
#define DDRCTL_DRAMTMG5 0x04040302
|
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#define DDRCTL_DRAMTMG6 0x00000004
|
||||
#define DDRCTL_DRAMTMG7 0x00000404
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||||
#define DDRCTL_DRAMTMG8 0x03030C05
|
||||
#define DDRCTL_DRAMTMG8 0x03030A05
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#define DDRCTL_DRAMTMG9 0x00020208
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#define DDRCTL_DRAMTMG10 0x001C180A
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#define DDRCTL_DRAMTMG11 0x1106010E
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#define DDRCTL_DRAMTMG11 0x0E06010E
|
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#define DDRCTL_DRAMTMG12 0x00020008
|
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#define DDRCTL_DRAMTMG13 0x0B100002
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#define DDRCTL_DRAMTMG14 0x00000000
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||||
|
|
@ -47,7 +48,7 @@
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|||
#define DDRCTL_DFITMG1 0x000A0606
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#define DDRCTL_DFITMG2 0x00000604
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#define DDRCTL_DFIMISC 0x00000001
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#define DDRCTL_ADDRMAP0 0x001F1F1F
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#define DDRCTL_ADDRMAP0 0x0000001F
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#define DDRCTL_ADDRMAP1 0x003F0808
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#define DDRCTL_ADDRMAP2 0x00000000
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||||
#define DDRCTL_ADDRMAP3 0x00000000
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||||
|
|
@ -83,13 +84,13 @@
|
|||
#define DDRPHY_DCR 0x0000040C
|
||||
#define DDRPHY_DTPR0 0x041A0B06
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#define DDRPHY_DTPR1 0x28140000
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||||
#define DDRPHY_DTPR2 0x0034E300
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||||
#define DDRPHY_DTPR3 0x02800800
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#define DDRPHY_DTPR2 0x0034E255
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#define DDRPHY_DTPR3 0x01D50800
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#define DDRPHY_DTPR4 0x31180805
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#define DDRPHY_DTPR5 0x00250B06
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#define DDRPHY_DTPR6 0x00000505
|
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#define DDRPHY_ZQCR 0x008A2A58
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||||
#define DDRPHY_ZQ0PR0 0x000077DD
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||||
#define DDRPHY_ZQ0PR0 0x000077DD
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||||
#define DDRPHY_ZQ1PR0 0x000077DD
|
||||
#define DDRPHY_MR0 0x00000214
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||||
#define DDRPHY_MR1 0x00000501
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||||
|
|
@ -109,6 +110,8 @@
|
|||
#define DDRPHY_DX8SL2PLLCR0 0x021c4000
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#define DDRPHY_DTCR0 0x8000B1C7
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||||
#define DDRPHY_DTCR1 0x00010236
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#define DDRPHY_ACIOCR0 0x30070000
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#define DDRPHY_ACIOCR3 0x00000001
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#define DDRPHY_ACIOCR5 0x04800000
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#define DDRPHY_IOVCR0 0x0F0C0C0C
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#define DDRPHY_DX0GCR0 0x00000000
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|
|
@ -148,9 +151,12 @@
|
|||
#define DDRPHY_DX3GTR0 0x00020002
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#define DDRPHY_DX4GTR0 0x00020002
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#define DDRPHY_ODTCR 0x00010000
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#define DDRPHY_DX8SL0IOCR 0x04800000
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#define DDRPHY_DX8SL1IOCR 0x04800000
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#define DDRPHY_DX8SL2IOCR 0x04800000
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#define DDRPHY_DX8SL0IOCR 0x74800000
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#define DDRPHY_DX8SL1IOCR 0x74800000
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#define DDRPHY_DX8SL2IOCR 0x74800000
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#define DDRPHY_DX8SL0DXCTL2 0x00141830
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#define DDRPHY_DX8SL1DXCTL2 0x00141830
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#define DDRPHY_DX8SL2DXCTL2 0x00141830
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#define DDRPHY_DX8SL0DQSCTL 0x01264000
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#define DDRPHY_DX8SL1DQSCTL 0x01264000
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#define DDRPHY_DX8SL2DQSCTL 0x01264000
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|
@ -17,6 +17,10 @@
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|||
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
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u-boot,dm-spl;
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|
||||
ti,ss-reg = <
|
||||
DDRSS_V2H_CTL_REG
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||||
>;
|
||||
|
||||
ti,ctl-reg = <
|
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DDRCTL_DFIMISC
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DDRCTL_DFITMG0
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||||
|
|
@ -132,12 +136,15 @@
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|||
DDRPHY_DX8SL0DXCTL2
|
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DDRPHY_DX8SL0IOCR
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DDRPHY_DX8SL0PLLCR0
|
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DDRPHY_DX8SL0DQSCTL
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DDRPHY_DX8SL1DXCTL2
|
||||
DDRPHY_DX8SL1IOCR
|
||||
DDRPHY_DX8SL1PLLCR0
|
||||
DDRPHY_DX8SL1DQSCTL
|
||||
DDRPHY_DX8SL2DXCTL2
|
||||
DDRPHY_DX8SL2IOCR
|
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DDRPHY_DX8SL2PLLCR0
|
||||
DDRPHY_DX8SL2DQSCTL
|
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DDRPHY_DXCCR
|
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DDRPHY_ODTCR
|
||||
DDRPHY_PGCR0
|
||||
|
|
@ -168,6 +175,8 @@
|
|||
>;
|
||||
|
||||
ti,phy-ioctl = <
|
||||
DDRPHY_ACIOCR0
|
||||
DDRPHY_ACIOCR3
|
||||
DDRPHY_ACIOCR5
|
||||
DDRPHY_IOVCR0
|
||||
>;
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
#include "k3-am654.dtsi"
|
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#include "k3-am654-base-board-u-boot.dtsi"
|
||||
#include "k3-am654-base-board-ddr4-1600MHz.dtsi"
|
||||
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
|
||||
#include "k3-am654-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
|
|||
2195
arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
Normal file
2195
arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi
Normal file
File diff suppressed because it is too large
Load diff
2212
arch/arm/dts/k3-j721e-ddr.dtsi
Normal file
2212
arch/arm/dts/k3-j721e-ddr.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -6,6 +6,8 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "k3-j721e-som-p0.dtsi"
|
||||
#include "k3-j721e-ddr-evm-lp4-3733.dtsi"
|
||||
#include "k3-j721e-ddr.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
|
||||
ocp2scp@4a080000 {
|
||||
compatible = "ti,omap-ocp2scp", "simple-bus";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
ocp2scp@4a090000 {
|
||||
|
|
|
|||
|
|
@ -224,6 +224,8 @@ static void do_nonsec_virt_switch(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
__weak void board_prep_linux(bootm_headers_t *images) { }
|
||||
|
||||
/* Subcommand: PREP */
|
||||
static void boot_prep_linux(bootm_headers_t *images)
|
||||
{
|
||||
|
|
@ -270,6 +272,8 @@ static void boot_prep_linux(bootm_headers_t *images)
|
|||
printf("FDT and ATAGS support not compiled in - hanging\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
board_prep_linux(images);
|
||||
}
|
||||
|
||||
__weak bool armv7_boot_nonsec_default(void)
|
||||
|
|
|
|||
|
|
@ -233,3 +233,14 @@ int print_cpuinfo(void)
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
void board_prep_linux(bootm_headers_t *images)
|
||||
{
|
||||
debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
|
||||
images->os.start, images->os.end);
|
||||
__asm_flush_dcache_range(images->os.start,
|
||||
ROUND(images->os.end,
|
||||
CONFIG_SYS_CACHELINE_SIZE));
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static void store_boot_index_from_rom(void)
|
|||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
#if defined(CONFIG_K3_LOAD_SYSFW)
|
||||
#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
#endif
|
||||
|
|
@ -117,6 +117,12 @@ void board_init_f(ulong dummy)
|
|||
/* Prepare console output */
|
||||
preloader_console_init();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_K3_J721E_DDRSS)
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret)
|
||||
panic("DRAM init failed: %d\n", ret);
|
||||
#endif
|
||||
}
|
||||
|
||||
u32 spl_boot_mode(const u32 boot_device)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ config TARGET_J721E_R5_EVM
|
|||
select K3_LOAD_SYSFW
|
||||
select RAM
|
||||
select SPL_RAM
|
||||
select K3_J721E_DDRSS
|
||||
imply SYS_K3_SPL_ATF
|
||||
|
||||
endchoice
|
||||
|
|
|
|||
|
|
@ -48,6 +48,9 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
}
|
||||
|
||||
images->ep = relocated_addr;
|
||||
images->os.start = relocated_addr;
|
||||
images->os.end = relocated_addr + image_size;
|
||||
|
||||
lmb_reserve(&images->lmb, images->ep, le32_to_cpu(image_size));
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -25,8 +25,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
|||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_DMA_SUPPORT=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_DFU=y
|
||||
CONFIG_CMD_SPL=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
|
|
@ -39,7 +42,7 @@ CONFIG_SPL_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
|
||||
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
|
||||
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
|
||||
# CONFIG_ENV_IS_IN_FAT is not set
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
|
|
@ -85,6 +88,7 @@ CONFIG_MII=y
|
|||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_PIPE3_PHY=y
|
||||
CONFIG_SPL_PIPE3_PHY=y
|
||||
CONFIG_OMAP_USB2_PHY=y
|
||||
CONFIG_PMIC_PALMAS=y
|
||||
CONFIG_PMIC_LP873X=y
|
||||
|
|
@ -107,7 +111,9 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_OMAP=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_DWC3_PHY_OMAP=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
|
|
|
|||
|
|
@ -30,8 +30,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
|||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_DMA_SUPPORT=y
|
||||
# CONFIG_SPL_NAND_SUPPORT is not set
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
|
|
@ -42,7 +45,7 @@ CONFIG_SPL_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
|
||||
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
|
||||
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
|
||||
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
|
||||
# CONFIG_ENV_IS_IN_FAT is not set
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
|
|
@ -88,6 +91,7 @@ CONFIG_MII=y
|
|||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_PIPE3_PHY=y
|
||||
CONFIG_SPL_PIPE3_PHY=y
|
||||
CONFIG_OMAP_USB2_PHY=y
|
||||
CONFIG_PMIC_PALMAS=y
|
||||
CONFIG_PMIC_LP873X=y
|
||||
|
|
@ -110,7 +114,9 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_OMAP=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_DWC3_PHY_OMAP=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
|
|
|
|||
2241
doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
Normal file
2241
doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -54,5 +54,16 @@ config K3_AM654_DDRSS
|
|||
config add support for the initialization of the external
|
||||
SDRAM devices connected to DDR subsystem.
|
||||
|
||||
config K3_J721E_DDRSS
|
||||
bool "Enable J721E DDRSS support"
|
||||
depends on RAM
|
||||
help
|
||||
The J721E DDR subsystem comprises DDR controller, DDR PHY and
|
||||
wrapper logic to integrate these blocks in the device. The DDR
|
||||
subsystem is used to provide an interface to external SDRAM
|
||||
devices which can be utilized for storing program or data.
|
||||
Enabling this config adds support for the DDR memory controller
|
||||
on J721E family of SoCs.
|
||||
|
||||
source "drivers/ram/rockchip/Kconfig"
|
||||
source "drivers/ram/stm32mp1/Kconfig"
|
||||
|
|
|
|||
|
|
@ -14,3 +14,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
|||
|
||||
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
|
||||
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
||||
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
|
||||
|
|
|
|||
|
|
@ -143,6 +143,7 @@ static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
|
|||
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
|
||||
|
||||
|
|
@ -152,6 +153,7 @@ static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
|
|||
ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
|
||||
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
|
||||
ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
|
||||
|
|
@ -204,11 +206,13 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
|
|||
|
||||
debug("%s: DDR phy register configuration started\n", __func__);
|
||||
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
|
||||
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
|
||||
|
|
@ -240,6 +244,11 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
|
|||
ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
|
||||
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
|
||||
|
||||
|
|
@ -250,6 +259,8 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
|
|||
ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
|
||||
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
|
||||
|
||||
|
|
@ -285,6 +296,10 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
|
|||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
|
||||
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
|
||||
|
||||
debug("%s: DDR phy register configuration completed\n", __func__);
|
||||
}
|
||||
|
||||
|
|
@ -354,13 +369,32 @@ int read_dqs_training(struct am654_ddrss_desc *ddrss)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int rest_training(struct am654_ddrss_desc *ddrss)
|
||||
int dqs2dq_training(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
|
||||
|
||||
debug("%s: Rest of the training started\n", __func__);
|
||||
debug("%s: DQS2DQ training started\n", __func__);
|
||||
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
|
||||
PGSR0_DQS2DQDONE_MASK,
|
||||
PGSR0_DQS2DQERR_MASK);
|
||||
if (ret) {
|
||||
if (ret == -ETIMEDOUT)
|
||||
printf("%s: ERROR: DQS2DQ training timedout\n",
|
||||
__func__);
|
||||
else
|
||||
printf("%s:ERROR: DQS2DQ training failed\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
debug("%s: DQS2DQ training completed\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
int ret;
|
||||
|
||||
debug("%s: Write Leveling adjustment\n", __func__);
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
|
||||
|
|
@ -374,6 +408,14 @@ int rest_training(struct am654_ddrss_desc *ddrss)
|
|||
__func__);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rest_training(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
int ret;
|
||||
|
||||
debug("%s: Rest of the training started\n", __func__);
|
||||
|
||||
debug("%s: Read Deskew adjustment\n", __func__);
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
|
||||
|
|
@ -422,7 +464,12 @@ int rest_training(struct am654_ddrss_desc *ddrss)
|
|||
__func__);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int VREF_training(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
int ret;
|
||||
debug("%s: VREF training\n", __func__);
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
|
||||
PGSR0_VERR_MASK);
|
||||
|
|
@ -433,6 +480,56 @@ int rest_training(struct am654_ddrss_desc *ddrss)
|
|||
printf("%s: ERROR: VREF training failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
|
||||
val &= ~0xFF;
|
||||
val |= 0xF7;
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
|
||||
|
||||
val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
|
||||
val &= ~0xFF;
|
||||
val |= 0xF7;
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
|
||||
|
||||
val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
|
||||
val &= ~0xFF;
|
||||
val |= 0xF7;
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
|
||||
|
||||
sdelay(16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
|
||||
val &= ~0xFF;
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
|
||||
|
||||
val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
|
||||
val &= ~0xFF;
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
|
||||
|
||||
val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
|
||||
val &= ~0xFF;
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
|
||||
|
||||
sdelay(16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cleanup_training(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
u32 val;
|
||||
u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
|
||||
|
||||
ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
|
||||
dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
|
||||
|
|
@ -528,10 +625,15 @@ int rest_training(struct am654_ddrss_desc *ddrss)
|
|||
static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
|
||||
|
||||
debug("Starting DDR initialization...\n");
|
||||
|
||||
debug("%s(ddrss=%p)\n", __func__, ddrss);
|
||||
|
||||
ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
|
||||
ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
|
||||
reg->ddrss_v2h_ctl_reg);
|
||||
|
||||
am654_ddrss_ctrl_configuration(ddrss);
|
||||
|
||||
|
|
@ -541,6 +643,7 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
|
|||
|
||||
am654_ddrss_phy_configuration(ddrss);
|
||||
|
||||
debug("Starting DDR training...\n");
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
|
||||
|
|
@ -561,15 +664,162 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = write_leveling(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
val = am654_ddrss_get_type(ddrss);
|
||||
|
||||
ret = read_dqs_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
switch (val) {
|
||||
case DDR_TYPE_LPDDR4:
|
||||
|
||||
ret = rest_training(ddrss);
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
|
||||
PGSR0_DRAM_INIT_MASK, 0);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "DRAM initialization failed %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* must perform DRAM_INIT twice for LPDDR4 */
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
|
||||
PGSR0_DRAM_INIT_MASK, 0);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "DRAM initialization failed %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
|
||||
if (ret) {
|
||||
printf("%s: ERROR: DRAM Wait for init complete timedout\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = write_leveling(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = enable_dqs_pd(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = read_dqs_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = disable_dqs_pd(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = dqs2dq_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = write_leveling_adjustment(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rest_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = VREF_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
debug("LPDDR4 training complete\n");
|
||||
break;
|
||||
|
||||
case DDR_TYPE_DDR4:
|
||||
|
||||
debug("Starting DDR4 training\n");
|
||||
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
|
||||
PGSR0_DRAM_INIT_MASK, 0);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "DRAM initialization failed %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
|
||||
if (ret) {
|
||||
printf("%s: ERROR: DRAM Wait for init complete timedout\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = write_leveling(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = read_dqs_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = write_leveling_adjustment(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rest_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = VREF_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
debug("DDR4 training complete\n");
|
||||
break;
|
||||
|
||||
case DDR_TYPE_DDR3:
|
||||
|
||||
debug("Starting DDR3 training\n");
|
||||
|
||||
ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
|
||||
PGSR0_DRAM_INIT_MASK, 0);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "DRAM initialization failed %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
|
||||
if (ret) {
|
||||
printf("%s: ERROR: DRAM Wait for init complete timedout\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = write_leveling(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = enable_dqs_pd(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = read_dqs_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = disable_dqs_pd(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = write_leveling_adjustment(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rest_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
debug("DDR3 training complete\n");
|
||||
break;
|
||||
default:
|
||||
printf("%s: ERROR: Unsupported DDR type\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = cleanup_training(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -581,6 +831,8 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
|
|||
ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
|
||||
ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
|
||||
|
||||
debug("Completed DDR training\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -682,6 +934,14 @@ static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
|
|||
}
|
||||
ddrss->ddrss_phy_cfg = (void *)reg;
|
||||
|
||||
ret = dev_read_u32_array(dev, "ti,ss-reg",
|
||||
(u32 *)&ddrss->params.ss_reg,
|
||||
sizeof(ddrss->params.ss_reg) / sizeof(u32));
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot read ti,ss-reg params\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dev_read_u32_array(dev, "ti,ctl-reg",
|
||||
(u32 *)&ddrss->params.ctl_reg,
|
||||
sizeof(ddrss->params.ctl_reg) / sizeof(u32));
|
||||
|
|
|
|||
|
|
@ -996,6 +996,10 @@
|
|||
PGSR0_DIDONE_MASK)
|
||||
#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK)
|
||||
|
||||
struct ddrss_ss_reg_params {
|
||||
u32 ddrss_v2h_ctl_reg;
|
||||
};
|
||||
|
||||
struct ddrss_ddrctl_reg_params {
|
||||
u32 ddrctl_dfimisc;
|
||||
u32 ddrctl_dfitmg0;
|
||||
|
|
@ -1111,12 +1115,15 @@ struct ddrss_ddrphy_cfg_params {
|
|||
u32 ddrphy_dx8sl0dxctl2;
|
||||
u32 ddrphy_dx8sl0iocr;
|
||||
u32 ddrphy_dx8sl0pllcr0;
|
||||
u32 ddrphy_dx8sl0dqsctl;
|
||||
u32 ddrphy_dx8sl1dxctl2;
|
||||
u32 ddrphy_dx8sl1iocr;
|
||||
u32 ddrphy_dx8sl1pllcr0;
|
||||
u32 ddrphy_dx8sl1dqsctl;
|
||||
u32 ddrphy_dx8sl2dxctl2;
|
||||
u32 ddrphy_dx8sl2iocr;
|
||||
u32 ddrphy_dx8sl2pllcr0;
|
||||
u32 ddrphy_dx8sl2dqsctl;
|
||||
u32 ddrphy_dxccr;
|
||||
u32 ddrphy_odtcr;
|
||||
u32 ddrphy_pgcr0;
|
||||
|
|
@ -1147,6 +1154,8 @@ struct ddrss_ddrphy_ctrl_params {
|
|||
};
|
||||
|
||||
struct ddrss_ddrphy_ioctl_params {
|
||||
u32 ddrphy_aciocr0;
|
||||
u32 ddrphy_aciocr3;
|
||||
u32 ddrphy_aciocr5;
|
||||
u32 ddrphy_iovcr0;
|
||||
};
|
||||
|
|
@ -1173,6 +1182,7 @@ struct ddrss_ddrphy_zq_params {
|
|||
};
|
||||
|
||||
struct ddrss_params {
|
||||
struct ddrss_ss_reg_params ss_reg;
|
||||
struct ddrss_ddrctl_reg_params ctl_reg;
|
||||
struct ddrss_ddrctl_crc_params ctl_crc;
|
||||
struct ddrss_ddrctl_ecc_params ctl_ecc;
|
||||
|
|
|
|||
8
drivers/ram/k3-j721e/Makefile
Normal file
8
drivers/ram/k3-j721e/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
#
|
||||
|
||||
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
|
||||
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
|
||||
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o
|
||||
119
drivers/ram/k3-j721e/cps_drv_lpddr4.h
Normal file
119
drivers/ram/k3-j721e/cps_drv_lpddr4.h
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2017-2018 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* cps_drv_lpddr4.h
|
||||
* Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef CPS_DRV_H_
|
||||
#define CPS_DRV_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <inttypes.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
/**
|
||||
* \brief Read a 32-bit value from memory.
|
||||
* \param reg address of the memory mapped hardware register
|
||||
* \return the value at the given address
|
||||
*/
|
||||
#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
|
||||
|
||||
/**
|
||||
* \brief Write a 32-bit address value to memory.
|
||||
* \param reg address of the memory mapped hardware register
|
||||
* \param value unsigned 32-bit value to write
|
||||
*/
|
||||
#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
|
||||
|
||||
/**
|
||||
* \brief Subtitue the value of fld macro and concatinate with required string
|
||||
* \param fld field name
|
||||
*/
|
||||
#define CPS_FLD_MASK(fld) (fld ## _MASK)
|
||||
#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
|
||||
#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
|
||||
#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
|
||||
#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
|
||||
|
||||
/**
|
||||
* \brief Read a value of bit-field from the register value.
|
||||
* \param reg register name
|
||||
* \param fld field name
|
||||
* \param reg_value register value
|
||||
* \return bit-field value
|
||||
*/
|
||||
#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \
|
||||
(uint32_t)(CPS_FLD_SHIFT(fld)), \
|
||||
(uint32_t)(reg_value)))
|
||||
|
||||
/**
|
||||
* \brief Write a value of the bit-field into the register value.
|
||||
* \param reg register name
|
||||
* \param fld field name
|
||||
* \param reg_value register value
|
||||
* \param value value to be written to bit-field
|
||||
* \return modified register value
|
||||
*/
|
||||
#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \
|
||||
(uint32_t)(CPS_FLD_SHIFT(fld)), \
|
||||
(uint32_t)(reg_value), (uint32_t)(value)))
|
||||
|
||||
/**
|
||||
* \brief Set bit within the register value.
|
||||
* \param reg register name
|
||||
* \param fld field name
|
||||
* \param reg_value register value
|
||||
* \return modified register value
|
||||
*/
|
||||
#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
|
||||
(uint32_t)(CPS_FLD_MASK(fld)), \
|
||||
(uint32_t)(CPS_FLD_WOCLR(fld)), \
|
||||
(uint32_t)(reg_value)))
|
||||
|
||||
static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
|
||||
{
|
||||
uint32_t result = (reg_value & mask) >> shift;
|
||||
|
||||
return (result);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Write a value of the bit-field into the register value.
|
||||
* \param mask mask for the bit-field
|
||||
* \param shift bit-field shift from LSB
|
||||
* \param reg_value register value
|
||||
* \param value value to be written to bit-field
|
||||
* \return modified register value
|
||||
*/
|
||||
static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
|
||||
{
|
||||
uint32_t new_value = (value << shift) & mask;
|
||||
|
||||
new_value = (reg_value & ~mask) | new_value;
|
||||
return (new_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Set bit within the register value.
|
||||
* \param width width of the bit-field
|
||||
* \param mask mask for the bit-field
|
||||
* \param is_woclr is bit-field has 'write one to clear' flag set
|
||||
* \param reg_value register value
|
||||
* \return modified register value
|
||||
*/
|
||||
static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
|
||||
{
|
||||
uint32_t new_value = reg_value;
|
||||
/* Confirm the field to be bit and not write to clear type */
|
||||
if ((width == 1U) && (is_woclr == 0U)) {
|
||||
new_value |= mask;
|
||||
}
|
||||
|
||||
return (new_value);
|
||||
}
|
||||
#endif /* CPS_DRV_H_ */
|
||||
372
drivers/ram/k3-j721e/k3-j721e-ddrss.c
Normal file
372
drivers/ram/k3-j721e/k3-j721e-ddrss.c
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Texas Instruments' J721E DDRSS driver
|
||||
*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <ram.h>
|
||||
#include <asm/io.h>
|
||||
#include <power-domain.h>
|
||||
#include <wait_bit.h>
|
||||
|
||||
#include "lpddr4_obj_if.h"
|
||||
#include "lpddr4_if.h"
|
||||
#include "lpddr4_structs_if.h"
|
||||
#include "lpddr4_ctl_regs.h"
|
||||
|
||||
#define SRAM_MAX 512
|
||||
|
||||
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
|
||||
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
|
||||
|
||||
struct j721e_ddrss_desc {
|
||||
struct udevice *dev;
|
||||
void __iomem *ddrss_ss_cfg;
|
||||
void __iomem *ddrss_ctrl_mmr;
|
||||
struct power_domain ddrcfg_pwrdmn;
|
||||
struct power_domain ddrdata_pwrdmn;
|
||||
struct clk ddr_clk;
|
||||
struct clk osc_clk;
|
||||
u32 ddr_freq1;
|
||||
u32 ddr_freq2;
|
||||
u32 ddr_fhs_cnt;
|
||||
};
|
||||
|
||||
static LPDDR4_OBJ *driverdt;
|
||||
static lpddr4_config config;
|
||||
static lpddr4_privatedata pd;
|
||||
|
||||
static struct j721e_ddrss_desc *ddrss;
|
||||
|
||||
#define TH_MACRO_EXP(fld, str) (fld##str)
|
||||
|
||||
#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
|
||||
#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
|
||||
#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
|
||||
#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
|
||||
#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
|
||||
|
||||
#define str(s) #s
|
||||
#define xstr(s) str(s)
|
||||
|
||||
#define CTL_SHIFT 11
|
||||
#define PHY_SHIFT 11
|
||||
#define PI_SHIFT 10
|
||||
|
||||
#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
|
||||
char *i, *pstr= xstr(REG); offset = 0;\
|
||||
for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
|
||||
offset = offset * 10 + (*i - '0'); }\
|
||||
} while (0)
|
||||
|
||||
static void j721e_lpddr4_ack_freq_upd_req(void)
|
||||
{
|
||||
unsigned int req_type, counter;
|
||||
|
||||
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
|
||||
|
||||
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
|
||||
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
|
||||
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
|
||||
true, 10000, false)) {
|
||||
printf("Timeout during frequency handshake\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
req_type = readl(ddrss->ddrss_ctrl_mmr +
|
||||
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
|
||||
|
||||
debug("%s: received freq change req: req type = %d, req no. = %d \n",
|
||||
__func__, req_type, counter);
|
||||
|
||||
if (req_type == 1)
|
||||
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
|
||||
else if (req_type == 2)
|
||||
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
|
||||
else if (req_type == 0)
|
||||
/* Put DDR pll in bypass mode */
|
||||
clk_set_rate(&ddrss->ddr_clk,
|
||||
clk_get_rate(&ddrss->osc_clk));
|
||||
else
|
||||
printf("%s: Invalid freq request type\n", __func__);
|
||||
|
||||
writel(0x1, ddrss->ddrss_ctrl_mmr +
|
||||
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
|
||||
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
|
||||
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
|
||||
false, 10, false)) {
|
||||
printf("Timeout during frequency handshake\n");
|
||||
hang();
|
||||
}
|
||||
writel(0x0, ddrss->ddrss_ctrl_mmr +
|
||||
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
|
||||
}
|
||||
}
|
||||
|
||||
static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
|
||||
lpddr4_infotype infotype)
|
||||
{
|
||||
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
|
||||
j721e_lpddr4_ack_freq_upd_req();
|
||||
}
|
||||
}
|
||||
|
||||
static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
|
||||
{
|
||||
int ret;
|
||||
|
||||
debug("%s(ddrss=%p)\n", __func__, ddrss);
|
||||
|
||||
ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
|
||||
if (ret) {
|
||||
dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
|
||||
{
|
||||
struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
|
||||
phys_addr_t reg;
|
||||
int ret;
|
||||
|
||||
debug("%s(dev=%p)\n", __func__, dev);
|
||||
|
||||
reg = dev_read_addr_name(dev, "cfg");
|
||||
if (reg == FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "No reg property for DDRSS wrapper logic\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
ddrss->ddrss_ss_cfg = (void *)reg;
|
||||
|
||||
reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
|
||||
if (reg == FDT_ADDR_T_NONE) {
|
||||
dev_err(dev, "No reg property for CTRL MMR\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
ddrss->ddrss_ctrl_mmr = (void *)reg;
|
||||
|
||||
ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
|
||||
if (ret) {
|
||||
dev_err(dev, "power_domain_get() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
|
||||
if (ret) {
|
||||
dev_err(dev, "power_domain_get() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
|
||||
if (ret)
|
||||
dev_err(dev, "clk get failed%d\n", ret);
|
||||
|
||||
ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
|
||||
if (ret)
|
||||
dev_err(dev, "clk get failed for osc clk %d\n", ret);
|
||||
|
||||
ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
|
||||
if (ret)
|
||||
dev_err(dev, "ddr freq1 not populated %d\n", ret);
|
||||
|
||||
ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
|
||||
if (ret)
|
||||
dev_err(dev, "ddr freq2 not populated %d\n", ret);
|
||||
|
||||
ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
|
||||
if (ret)
|
||||
dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
|
||||
|
||||
/* Put DDR pll in bypass mode */
|
||||
ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
|
||||
if (ret)
|
||||
dev_err(dev, "ddr clk bypass failed\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void j721e_lpddr4_probe(void)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
uint16_t configsize = 0U;
|
||||
|
||||
status = driverdt->probe(&config, &configsize);
|
||||
|
||||
if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
|
||||
|| (configsize > SRAM_MAX)) {
|
||||
printf("LPDDR4_Probe: FAIL\n");
|
||||
hang();
|
||||
} else {
|
||||
debug("LPDDR4_Probe: PASS\n");
|
||||
}
|
||||
}
|
||||
|
||||
void j721e_lpddr4_init(void)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
|
||||
if ((sizeof(pd) != sizeof(lpddr4_privatedata))
|
||||
|| (sizeof(pd) > SRAM_MAX)) {
|
||||
printf("LPDDR4_Init: FAIL\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
|
||||
config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
|
||||
|
||||
status = driverdt->init(&pd, &config);
|
||||
|
||||
if ((status > 0U) ||
|
||||
(pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
|
||||
(pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
|
||||
(pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
|
||||
printf("LPDDR4_Init: FAIL\n");
|
||||
hang();
|
||||
} else {
|
||||
debug("LPDDR4_Init: PASS\n");
|
||||
}
|
||||
}
|
||||
|
||||
void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
|
||||
(u32 *) reginit_data->denalictlreg,
|
||||
LPDDR4_CTL_REG_COUNT);
|
||||
if (ret)
|
||||
printf("Error reading ctrl data\n");
|
||||
|
||||
for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
|
||||
reginit_data->updatectlreg[i] = true;
|
||||
|
||||
ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
|
||||
(u32 *) reginit_data->denaliphyindepreg,
|
||||
LPDDR4_PHY_INDEP_REG_COUNT);
|
||||
if (ret)
|
||||
printf("Error reading PI data\n");
|
||||
|
||||
for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
|
||||
reginit_data->updatephyindepreg[i] = true;
|
||||
|
||||
ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
|
||||
(u32 *) reginit_data->denaliphyreg,
|
||||
LPDDR4_PHY_REG_COUNT);
|
||||
if (ret)
|
||||
printf("Error reading PHY data\n");
|
||||
|
||||
for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
|
||||
reginit_data->updatephyreg[i] = true;
|
||||
}
|
||||
|
||||
void j721e_lpddr4_hardware_reg_init(void)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
lpddr4_reginitdata reginitdata;
|
||||
|
||||
populate_data_array_from_dt(®initdata);
|
||||
|
||||
status = driverdt->writectlconfig(&pd, ®initdata);
|
||||
if (!status) {
|
||||
status = driverdt->writephyindepconfig(&pd, ®initdata);
|
||||
}
|
||||
if (!status) {
|
||||
status = driverdt->writephyconfig(&pd, ®initdata);
|
||||
}
|
||||
if (status) {
|
||||
printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void j721e_lpddr4_start(void)
|
||||
{
|
||||
uint32_t status = 0U;
|
||||
uint32_t regval = 0U;
|
||||
uint32_t offset = 0U;
|
||||
|
||||
TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
|
||||
|
||||
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
|
||||
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
|
||||
printf("LPDDR4_StartTest: FAIL\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
status = driverdt->start(&pd);
|
||||
if (status > 0U) {
|
||||
printf("LPDDR4_StartTest: FAIL\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
|
||||
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
|
||||
printf("LPDDR4_Start: FAIL\n");
|
||||
hang();
|
||||
} else {
|
||||
debug("LPDDR4_Start: PASS\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int j721e_ddrss_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
ddrss = dev_get_priv(dev);
|
||||
|
||||
debug("%s(dev=%p)\n", __func__, dev);
|
||||
|
||||
ret = j721e_ddrss_ofdata_to_priv(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ddrss->dev = dev;
|
||||
ret = j721e_ddrss_power_on(ddrss);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
driverdt = lpddr4_getinstance();
|
||||
j721e_lpddr4_probe();
|
||||
j721e_lpddr4_init();
|
||||
j721e_lpddr4_hardware_reg_init();
|
||||
j721e_lpddr4_start();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ram_ops j721e_ddrss_ops = {
|
||||
.get_info = j721e_ddrss_get_info,
|
||||
};
|
||||
|
||||
static const struct udevice_id j721e_ddrss_ids[] = {
|
||||
{.compatible = "ti,j721e-ddrss"},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(j721e_ddrss) = {
|
||||
.name = "j721e_ddrss",
|
||||
.id = UCLASS_RAM,
|
||||
.of_match = j721e_ddrss_ids,
|
||||
.ops = &j721e_ddrss_ops,
|
||||
.probe = j721e_ddrss_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
|
||||
};
|
||||
2119
drivers/ram/k3-j721e/lpddr4.c
Normal file
2119
drivers/ram/k3-j721e/lpddr4.c
Normal file
File diff suppressed because it is too large
Load diff
825
drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
Normal file
825
drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
Normal file
|
|
@ -0,0 +1,825 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
|
||||
#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
|
||||
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
|
||||
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
|
||||
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
|
||||
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH 9U
|
||||
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
|
||||
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
|
||||
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
|
||||
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U
|
||||
#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062
|
||||
#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET 0U
|
||||
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET 0U
|
||||
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
|
||||
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
|
||||
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075
|
||||
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075
|
||||
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
|
||||
1546
drivers/ram/k3-j721e/lpddr4_ctl_regs.h
Normal file
1546
drivers/ram/k3-j721e/lpddr4_ctl_regs.h
Normal file
File diff suppressed because it is too large
Load diff
2373
drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
Normal file
2373
drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
Normal file
File diff suppressed because it is too large
Load diff
2373
drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
Normal file
2373
drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
Normal file
File diff suppressed because it is too large
Load diff
2373
drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
Normal file
2373
drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
Normal file
File diff suppressed because it is too large
Load diff
2373
drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
Normal file
2373
drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
Normal file
File diff suppressed because it is too large
Load diff
7793
drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
Normal file
7793
drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
Normal file
File diff suppressed because it is too large
Load diff
578
drivers/ram/k3-j721e/lpddr4_if.h
Normal file
578
drivers/ram/k3-j721e/lpddr4_if.h
Normal file
|
|
@ -0,0 +1,578 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
|
||||
**********************************************************************
|
||||
* WARNING: This file is auto-generated using api-generator utility.
|
||||
* api-generator: 12.02.13bb8d5
|
||||
* Do not edit it manually.
|
||||
**********************************************************************
|
||||
* Cadence Core Driver for LPDDR4.
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_IF_H
|
||||
#define LPDDR4_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/** @defgroup ConfigInfo Configuration and Hardware Operation Information
|
||||
* The following definitions specify the driver operation environment that
|
||||
* is defined by hardware configuration or client code. These defines are
|
||||
* located in the header file of the core driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* Defines
|
||||
**********************************************************************/
|
||||
/** Number of chip-selects */
|
||||
#define LPDDR4_MAX_CS (2U)
|
||||
|
||||
/** Number of accessible registers for controller. */
|
||||
#define LPDDR4_CTL_REG_COUNT (459U)
|
||||
|
||||
/** Number of accessible registers for PHY Independent Module. */
|
||||
#define LPDDR4_PHY_INDEP_REG_COUNT (300U)
|
||||
|
||||
/** Number of accessible registers for PHY. */
|
||||
#define LPDDR4_PHY_REG_COUNT (1423U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DataStructure Dynamic Data Structures
|
||||
* This section defines the data structures used by the driver to provide
|
||||
* hardware information, modification and dynamic operation of the driver.
|
||||
* These data structures are defined in the header file of the core driver
|
||||
* and utilized by the API.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* Forward declarations
|
||||
**********************************************************************/
|
||||
typedef struct lpddr4_config_s lpddr4_config;
|
||||
typedef struct lpddr4_privatedata_s lpddr4_privatedata;
|
||||
typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
|
||||
typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
|
||||
typedef struct lpddr4_reginitdata_s lpddr4_reginitdata;
|
||||
|
||||
/**********************************************************************
|
||||
* Enumerations
|
||||
**********************************************************************/
|
||||
/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_CTL_REGS = 0U,
|
||||
LPDDR4_PHY_REGS = 1U,
|
||||
LPDDR4_PHY_INDEP_REGS = 2U
|
||||
} lpddr4_regblock;
|
||||
|
||||
/** Controller status or error interrupts. */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_RESET_DONE = 0U,
|
||||
LPDDR4_BUS_ACCESS_ERROR = 1U,
|
||||
LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U,
|
||||
LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U,
|
||||
LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U,
|
||||
LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U,
|
||||
LPDDR4_ECC_SCRUB_DONE = 6U,
|
||||
LPDDR4_ECC_SCRUB_ERROR = 7U,
|
||||
LPDDR4_PORT_COMMAND_ERROR = 8U,
|
||||
LPDDR4_MC_INIT_DONE = 9U,
|
||||
LPDDR4_LP_DONE = 10U,
|
||||
LPDDR4_BIST_DONE = 11U,
|
||||
LPDDR4_WRAP_ERROR = 12U,
|
||||
LPDDR4_INVALID_BURST_ERROR = 13U,
|
||||
LPDDR4_RDLVL_ERROR = 14U,
|
||||
LPDDR4_RDLVL_GATE_ERROR = 15U,
|
||||
LPDDR4_WRLVL_ERROR = 16U,
|
||||
LPDDR4_CA_TRAINING_ERROR = 17U,
|
||||
LPDDR4_DFI_UPDATE_ERROR = 18U,
|
||||
LPDDR4_MRR_ERROR = 19U,
|
||||
LPDDR4_PHY_MASTER_ERROR = 20U,
|
||||
LPDDR4_WRLVL_REQ = 21U,
|
||||
LPDDR4_RDLVL_REQ = 22U,
|
||||
LPDDR4_RDLVL_GATE_REQ = 23U,
|
||||
LPDDR4_CA_TRAINING_REQ = 24U,
|
||||
LPDDR4_LEVELING_DONE = 25U,
|
||||
LPDDR4_PHY_ERROR = 26U,
|
||||
LPDDR4_MR_READ_DONE = 27U,
|
||||
LPDDR4_TEMP_CHANGE = 28U,
|
||||
LPDDR4_TEMP_ALERT = 29U,
|
||||
LPDDR4_SW_DQS_COMPLETE = 30U,
|
||||
LPDDR4_DQS_OSC_BV_UPDATED = 31U,
|
||||
LPDDR4_DQS_OSC_OVERFLOW = 32U,
|
||||
LPDDR4_DQS_OSC_VAR_OUT = 33U,
|
||||
LPDDR4_MR_WRITE_DONE = 34U,
|
||||
LPDDR4_INHIBIT_DRAM_DONE = 35U,
|
||||
LPDDR4_DFI_INIT_STATE = 36U,
|
||||
LPDDR4_DLL_RESYNC_DONE = 37U,
|
||||
LPDDR4_TDFI_TO = 38U,
|
||||
LPDDR4_DFS_DONE = 39U,
|
||||
LPDDR4_DFS_STATUS = 40U,
|
||||
LPDDR4_REFRESH_STATUS = 41U,
|
||||
LPDDR4_ZQ_STATUS = 42U,
|
||||
LPDDR4_SW_REQ_MODE = 43U,
|
||||
LPDDR4_LOR_BITS = 44U
|
||||
} lpddr4_ctlinterrupt;
|
||||
|
||||
/** PHY Independent Module status or error interrupts. */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U,
|
||||
LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
|
||||
LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
|
||||
LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
|
||||
LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U,
|
||||
LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
|
||||
LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U,
|
||||
LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
|
||||
LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
|
||||
LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U,
|
||||
LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
|
||||
LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U,
|
||||
LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U,
|
||||
LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
|
||||
LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U,
|
||||
LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U,
|
||||
LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
|
||||
LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
|
||||
} lpddr4_phyindepinterrupt;
|
||||
|
||||
/** List of informations and warnings from driver. */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_DRV_NONE = 0U,
|
||||
LPDDR4_DRV_SOC_PLL_UPDATE = 1U
|
||||
} lpddr4_infotype;
|
||||
|
||||
/** Low power interface wake up timing parameters */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_LPI_PD_WAKEUP_FN = 0U,
|
||||
LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
|
||||
LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
|
||||
LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
|
||||
LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
|
||||
LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
|
||||
LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
|
||||
} lpddr4_lpiwakeupparam;
|
||||
|
||||
/** Half Datapath mode setting */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_REDUC_ON = 0U,
|
||||
LPDDR4_REDUC_OFF = 1U
|
||||
} lpddr4_reducmode;
|
||||
|
||||
/** ECC Control parameter setting */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_ECC_DISABLED = 0U,
|
||||
LPDDR4_ECC_ENABLED = 1U,
|
||||
LPDDR4_ECC_ERR_DETECT = 2U,
|
||||
LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
|
||||
} lpddr4_eccenable;
|
||||
|
||||
/** Data Byte Inversion mode setting */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_DBI_RD_ON = 0U,
|
||||
LPDDR4_DBI_RD_OFF = 1U,
|
||||
LPDDR4_DBI_WR_ON = 2U,
|
||||
LPDDR4_DBI_WR_OFF = 3U
|
||||
} lpddr4_dbimode;
|
||||
|
||||
/** Controller Frequency Set Point number */
|
||||
typedef enum
|
||||
{
|
||||
LPDDR4_FSP_0 = 0U,
|
||||
LPDDR4_FSP_1 = 1U,
|
||||
LPDDR4_FSP_2 = 2U
|
||||
} lpddr4_ctlfspnum;
|
||||
|
||||
/**********************************************************************
|
||||
* Callbacks
|
||||
**********************************************************************/
|
||||
/**
|
||||
* Reports informations and warnings that need to be communicated.
|
||||
* Params:
|
||||
* pD - driver state info specific to this instance.
|
||||
* infoType - Type of information.
|
||||
*/
|
||||
typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype);
|
||||
|
||||
/**
|
||||
* Reports interrupts received by the controller.
|
||||
* Params:
|
||||
* pD - driver state info specific to this instance.
|
||||
* ctlInterrupt - Interrupt raised
|
||||
* chipSelect - Chip for which interrupt raised
|
||||
*/
|
||||
typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect);
|
||||
|
||||
/**
|
||||
* Reports interrupts received by the PHY Independent Module.
|
||||
* Params:
|
||||
* privateData - driver state info specific to this instance.
|
||||
* phyIndepInterrupt - Interrupt raised
|
||||
* chipSelect - Chip for which interrupt raised
|
||||
*/
|
||||
typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DriverFunctionAPI Driver Function API
|
||||
* Prototypes for the driver API functions. The user application can link statically to the
|
||||
* necessary API functions and call them directly.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* API methods
|
||||
**********************************************************************/
|
||||
|
||||
/**
|
||||
* Checks configuration object.
|
||||
* @param[in] config Driver/hardware configuration required.
|
||||
* @param[out] configSize Size of memory allocations required.
|
||||
* @return CDN_EOK on success (requirements structure filled).
|
||||
* @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
|
||||
*/
|
||||
uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize);
|
||||
|
||||
/**
|
||||
* Init function to be called after LPDDR4_probe() to set up the
|
||||
* driver configuration. Memory should be allocated for drv_data
|
||||
* (using the size determined using LPDDR4_probe) before calling this
|
||||
* API. init_settings should be initialised with base addresses for
|
||||
* PHY Indepenent Module, Controller and PHY before calling this
|
||||
* function. If callbacks are required for interrupt handling, these
|
||||
* should also be configured in init_settings.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] cfg Specifies driver/hardware configuration.
|
||||
* @return CDN_EOK on success
|
||||
* @return EINVAL if illegal/inconsistent values in cfg.
|
||||
* @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
|
||||
*/
|
||||
uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg);
|
||||
|
||||
/**
|
||||
* Start the driver.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
*/
|
||||
uint32_t lpddr4_start(const lpddr4_privatedata* pd);
|
||||
|
||||
/**
|
||||
* Read a register from the controller, PHY or PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
|
||||
* @param[in] regOffset Register offset
|
||||
* @param[out] regValue Register value read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regOffset if out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
|
||||
|
||||
/**
|
||||
* Write a register in the controller, PHY or PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
|
||||
* @param[in] regOffset Register offset
|
||||
* @param[in] regValue Register value to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regOffset is out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
|
||||
|
||||
/**
|
||||
* Read a memory mode register from DRAM
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
|
||||
* @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
|
||||
* @param[out] mmrStatus Status of mode register read(mrr) instruction.
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regNumber is out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
|
||||
|
||||
/**
|
||||
* Write a memory mode register in DRAM
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
|
||||
* @param[out] mrwStatus Status of mode register write(mrw) instruction.
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regNumber is out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
|
||||
|
||||
/**
|
||||
* Write a set of initialisation values to the controller registers
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] regValues Register values to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Write a set of initialisation values to the PHY registers
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] regValues Register values to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Write a set of initialisation values to the PHY Independent Module
|
||||
* registers
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] regValues Register values to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read values of the controller registers in bulk (Set 'updateCtlReg'
|
||||
* to read) and store in memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] regValues Register values which are read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read the values of the PHY module registers in bulk (Set
|
||||
* 'updatePhyReg' to read) and store in memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] regValues Register values which are read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read the values of the PHY Independent module registers in bulk(Set
|
||||
* 'updatePhyIndepReg' to read) and store in memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] regValues Register values which are read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read the current interrupt mask for the controller
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] mask Value of interrupt mask
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask);
|
||||
|
||||
/**
|
||||
* Sets the interrupt mask for the controller
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mask Value of interrupt mask to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask);
|
||||
|
||||
/**
|
||||
* Check whether a specific controller interrupt is active
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be checked
|
||||
* @param[out] irqStatus Status of the interrupt, TRUE if active
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
|
||||
|
||||
/**
|
||||
* Acknowledge a specific controller interrupt
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be acknowledged
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
|
||||
|
||||
/**
|
||||
* Read the current interrupt mask for the PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] mask Value of interrupt mask
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
|
||||
|
||||
/**
|
||||
* Sets the interrupt mask for the PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mask Value of interrupt mask to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
|
||||
|
||||
/**
|
||||
* Check whether a specific PHY Independent Module interrupt is active
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be checked
|
||||
* @param[out] irqStatus Status of the interrupt, TRUE if active
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
|
||||
|
||||
/**
|
||||
* Acknowledge a specific PHY Independent Module interrupt
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be acknowledged
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
|
||||
|
||||
/**
|
||||
* Retrieve status information after a failed init. The
|
||||
* DebugStructInfo will be filled in with error codes which can be
|
||||
* referenced against the driver documentation for further details.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] debugInfo status
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if debugInfo is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
|
||||
|
||||
/**
|
||||
* Get the current value of Low power Interface wake up time.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] lpiWakeUpParam LPI timing parameter
|
||||
* @param[in] fspNum Frequency copy
|
||||
* @param[out] cycles Timing value(in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if powerMode is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Set the current value of Low power Interface wake up time.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] lpiWakeUpParam LPI timing parameter
|
||||
* @param[in] fspNum Frequency copy
|
||||
* @param[in] cycles Timing value(in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if powerMode is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Get the current value for ECC auto correction
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] eccParam ECC parameter setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
|
||||
|
||||
/**
|
||||
* Set the value for ECC auto correction. This API must be called
|
||||
* before startup of memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] eccParam ECC control parameter setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
|
||||
|
||||
/**
|
||||
* Get the current value for the Half Datapath option
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] mode Half Datapath setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mode is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
|
||||
|
||||
/**
|
||||
* Set the value for the Half Datapath option. This API must be
|
||||
* called before startup of memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mode Half Datapath setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mode is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
|
||||
|
||||
/**
|
||||
* Get the current value for Data Bus Inversion setting. This will be
|
||||
* compared with the current DRAM setting using the MR3 register.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] on_off DBI read value
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off);
|
||||
|
||||
/**
|
||||
* Get the current value for Data Bus Inversion setting. This will be
|
||||
* compared with the current DRAM setting using the MR3 register.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] on_off DBI write value
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off);
|
||||
|
||||
/**
|
||||
* Set the mode for Data Bus Inversion. This will also be set in DRAM
|
||||
* using the MR3 controller register. This API must be called before
|
||||
* startup of memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mode status
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mode is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
|
||||
|
||||
/**
|
||||
* Get the current value for the refresh rate (reading Refresh per
|
||||
* command timing).
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] fspNum Frequency set number
|
||||
* @param[out] cycles Refresh rate (in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if rate is NULL
|
||||
*/
|
||||
uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Set the refresh rate (writing Refresh per command timing).
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] fspNum Frequency set number
|
||||
* @param[in] cycles Refresh rate (in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if rate is NULL
|
||||
*/
|
||||
uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Handle Refreshing per chip select
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] trefInterval status
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if chipSelect is invalid
|
||||
*/
|
||||
uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval);
|
||||
|
||||
#endif /* LPDDR4_IF_H */
|
||||
55
drivers/ram/k3-j721e/lpddr4_obj_if.c
Normal file
55
drivers/ram/k3-j721e/lpddr4_obj_if.c
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
|
||||
**********************************************************************
|
||||
* WARNING: This file is auto-generated using api-generator utility.
|
||||
* api-generator: 12.02.13bb8d5
|
||||
* Do not edit it manually.
|
||||
**********************************************************************
|
||||
* Cadence Core Driver for LPDDR4.
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
#include "lpddr4_obj_if.h"
|
||||
|
||||
LPDDR4_OBJ *lpddr4_getinstance(void)
|
||||
{
|
||||
static LPDDR4_OBJ driver = {
|
||||
.probe = lpddr4_probe,
|
||||
.init = lpddr4_init,
|
||||
.start = lpddr4_start,
|
||||
.readreg = lpddr4_readreg,
|
||||
.writereg = lpddr4_writereg,
|
||||
.getmmrregister = lpddr4_getmmrregister,
|
||||
.setmmrregister = lpddr4_setmmrregister,
|
||||
.writectlconfig = lpddr4_writectlconfig,
|
||||
.writephyconfig = lpddr4_writephyconfig,
|
||||
.writephyindepconfig = lpddr4_writephyindepconfig,
|
||||
.readctlconfig = lpddr4_readctlconfig,
|
||||
.readphyconfig = lpddr4_readphyconfig,
|
||||
.readphyindepconfig = lpddr4_readphyindepconfig,
|
||||
.getctlinterruptmask = lpddr4_getctlinterruptmask,
|
||||
.setctlinterruptmask = lpddr4_setctlinterruptmask,
|
||||
.checkctlinterrupt = lpddr4_checkctlinterrupt,
|
||||
.ackctlinterrupt = lpddr4_ackctlinterrupt,
|
||||
.getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
|
||||
.setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
|
||||
.checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
|
||||
.ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
|
||||
.getdebuginitinfo = lpddr4_getdebuginitinfo,
|
||||
.getlpiwakeuptime = lpddr4_getlpiwakeuptime,
|
||||
.setlpiwakeuptime = lpddr4_setlpiwakeuptime,
|
||||
.geteccenable = lpddr4_geteccenable,
|
||||
.seteccenable = lpddr4_seteccenable,
|
||||
.getreducmode = lpddr4_getreducmode,
|
||||
.setreducmode = lpddr4_setreducmode,
|
||||
.getdbireadmode = lpddr4_getdbireadmode,
|
||||
.getdbiwritemode = lpddr4_getdbiwritemode,
|
||||
.setdbimode = lpddr4_setdbimode,
|
||||
.getrefreshrate = lpddr4_getrefreshrate,
|
||||
.setrefreshrate = lpddr4_setrefreshrate,
|
||||
.refreshperchipselect = lpddr4_refreshperchipselect,
|
||||
};
|
||||
|
||||
return &driver;
|
||||
}
|
||||
383
drivers/ram/k3-j721e/lpddr4_obj_if.h
Normal file
383
drivers/ram/k3-j721e/lpddr4_obj_if.h
Normal file
|
|
@ -0,0 +1,383 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
|
||||
**********************************************************************
|
||||
* WARNING: This file is auto-generated using api-generator utility.
|
||||
* api-generator: 12.02.13bb8d5
|
||||
* Do not edit it manually.
|
||||
**********************************************************************
|
||||
* Cadence Core Driver for LPDDR4.
|
||||
**********************************************************************
|
||||
*/
|
||||
#ifndef LPDDR4_OBJ_IF_H
|
||||
#define LPDDR4_OBJ_IF_H
|
||||
|
||||
#include "lpddr4_if.h"
|
||||
|
||||
/** @defgroup DriverObject Driver API Object
|
||||
* API listing for the driver. The API is contained in the object as
|
||||
* function pointers in the object structure. As the actual functions
|
||||
* resides in the Driver Object, the client software must first use the
|
||||
* global GetInstance function to obtain the Driver Object Pointer.
|
||||
* The actual APIs then can be invoked using obj->(api_name)() syntax.
|
||||
* These functions are defined in the header file of the core driver
|
||||
* and utilized by the API.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* API methods
|
||||
**********************************************************************/
|
||||
typedef struct lpddr4_obj_s
|
||||
{
|
||||
/**
|
||||
* Checks configuration object.
|
||||
* @param[in] config Driver/hardware configuration required.
|
||||
* @param[out] configSize Size of memory allocations required.
|
||||
* @return CDN_EOK on success (requirements structure filled).
|
||||
* @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
|
||||
*/
|
||||
uint32_t (*probe)(const lpddr4_config* config, uint16_t* configsize);
|
||||
|
||||
/**
|
||||
* Init function to be called after LPDDR4_probe() to set up the
|
||||
* driver configuration. Memory should be allocated for drv_data
|
||||
* (using the size determined using LPDDR4_probe) before calling
|
||||
* this API. init_settings should be initialised with base addresses
|
||||
* for PHY Indepenent Module, Controller and PHY before calling this
|
||||
* function. If callbacks are required for interrupt handling, these
|
||||
* should also be configured in init_settings.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] cfg Specifies driver/hardware configuration.
|
||||
* @return CDN_EOK on success
|
||||
* @return EINVAL if illegal/inconsistent values in cfg.
|
||||
* @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
|
||||
*/
|
||||
uint32_t (*init)(lpddr4_privatedata* pd, const lpddr4_config* cfg);
|
||||
|
||||
/**
|
||||
* Start the driver.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
*/
|
||||
uint32_t (*start)(const lpddr4_privatedata* pd);
|
||||
|
||||
/**
|
||||
* Read a register from the controller, PHY or PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
|
||||
* @param[in] regOffset Register offset
|
||||
* @param[out] regValue Register value read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regOffset if out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
|
||||
|
||||
/**
|
||||
* Write a register in the controller, PHY or PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
|
||||
* @param[in] regOffset Register offset
|
||||
* @param[in] regValue Register value to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regOffset is out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
|
||||
|
||||
/**
|
||||
* Read a memory mode register from DRAM
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
|
||||
* @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
|
||||
* @param[out] mmrStatus Status of mode register read(mrr) instruction.
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regNumber is out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
|
||||
|
||||
/**
|
||||
* Write a memory mode register in DRAM
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
|
||||
* @param[out] mrwStatus Status of mode register write(mrw) instruction.
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regNumber is out of range or regValue is NULL
|
||||
*/
|
||||
uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
|
||||
|
||||
/**
|
||||
* Write a set of initialisation values to the controller registers
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] regValues Register values to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t (*writectlconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Write a set of initialisation values to the PHY registers
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] regValues Register values to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t (*writephyconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Write a set of initialisation values to the PHY Independent Module
|
||||
* registers
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] regValues Register values to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t (*writephyindepconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read values of the controller registers in bulk (Set
|
||||
* 'updateCtlReg' to read) and store in memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] regValues Register values which are read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t (*readctlconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read the values of the PHY module registers in bulk (Set
|
||||
* 'updatePhyReg' to read) and store in memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] regValues Register values which are read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t (*readphyconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read the values of the PHY Independent module registers in
|
||||
* bulk(Set 'updatePhyIndepReg' to read) and store in memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] regValues Register values which are read
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if regValues is NULL
|
||||
*/
|
||||
uint32_t (*readphyindepconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
|
||||
|
||||
/**
|
||||
* Read the current interrupt mask for the controller
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] mask Value of interrupt mask
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t (*getctlinterruptmask)(const lpddr4_privatedata* pd, uint64_t* mask);
|
||||
|
||||
/**
|
||||
* Sets the interrupt mask for the controller
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mask Value of interrupt mask to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t (*setctlinterruptmask)(const lpddr4_privatedata* pd, const uint64_t* mask);
|
||||
|
||||
/**
|
||||
* Check whether a specific controller interrupt is active
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be checked
|
||||
* @param[out] irqStatus Status of the interrupt, TRUE if active
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t (*checkctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
|
||||
|
||||
/**
|
||||
* Acknowledge a specific controller interrupt
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be acknowledged
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t (*ackctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
|
||||
|
||||
/**
|
||||
* Read the current interrupt mask for the PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] mask Value of interrupt mask
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask);
|
||||
|
||||
/**
|
||||
* Sets the interrupt mask for the PHY Independent Module
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mask Value of interrupt mask to be written
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mask pointer is NULL
|
||||
*/
|
||||
uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask);
|
||||
|
||||
/**
|
||||
* Check whether a specific PHY Independent Module interrupt is
|
||||
* active
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be checked
|
||||
* @param[out] irqStatus Status of the interrupt, TRUE if active
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t (*checkphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
|
||||
|
||||
/**
|
||||
* Acknowledge a specific PHY Independent Module interrupt
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] intr Interrupt to be acknowledged
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if intr is not valid
|
||||
*/
|
||||
uint32_t (*ackphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
|
||||
|
||||
/**
|
||||
* Retrieve status information after a failed init. The
|
||||
* DebugStructInfo will be filled in with error codes which can be
|
||||
* referenced against the driver documentation for further details.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] debugInfo status
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if debugInfo is NULL
|
||||
*/
|
||||
uint32_t (*getdebuginitinfo)(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
|
||||
|
||||
/**
|
||||
* Get the current value of Low power Interface wake up time.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] lpiWakeUpParam LPI timing parameter
|
||||
* @param[in] fspNum Frequency copy
|
||||
* @param[out] cycles Timing value(in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if powerMode is NULL
|
||||
*/
|
||||
uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Set the current value of Low power Interface wake up time.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] lpiWakeUpParam LPI timing parameter
|
||||
* @param[in] fspNum Frequency copy
|
||||
* @param[in] cycles Timing value(in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if powerMode is NULL
|
||||
*/
|
||||
uint32_t (*setlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Get the current value for ECC auto correction
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] eccParam ECC parameter setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t (*geteccenable)(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
|
||||
|
||||
/**
|
||||
* Set the value for ECC auto correction. This API must be called
|
||||
* before startup of memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] eccParam ECC control parameter setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t (*seteccenable)(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
|
||||
|
||||
/**
|
||||
* Get the current value for the Half Datapath option
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] mode Half Datapath setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mode is NULL
|
||||
*/
|
||||
uint32_t (*getreducmode)(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
|
||||
|
||||
/**
|
||||
* Set the value for the Half Datapath option. This API must be
|
||||
* called before startup of memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mode Half Datapath setting
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mode is NULL
|
||||
*/
|
||||
uint32_t (*setreducmode)(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
|
||||
|
||||
/**
|
||||
* Get the current value for Data Bus Inversion setting. This will
|
||||
* be compared with the current DRAM setting using the MR3
|
||||
* register.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] on_off DBI read value
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t (*getdbireadmode)(const lpddr4_privatedata* pd, bool* on_off);
|
||||
|
||||
/**
|
||||
* Get the current value for Data Bus Inversion setting. This will
|
||||
* be compared with the current DRAM setting using the MR3
|
||||
* register.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[out] on_off DBI write value
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if on_off is NULL
|
||||
*/
|
||||
uint32_t (*getdbiwritemode)(const lpddr4_privatedata* pd, bool* on_off);
|
||||
|
||||
/**
|
||||
* Set the mode for Data Bus Inversion. This will also be set in DRAM
|
||||
* using the MR3 controller register. This API must be called
|
||||
* before startup of memory.
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] mode status
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if mode is NULL
|
||||
*/
|
||||
uint32_t (*setdbimode)(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
|
||||
|
||||
/**
|
||||
* Get the current value for the refresh rate (reading Refresh per
|
||||
* command timing).
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] fspNum Frequency set number
|
||||
* @param[out] cycles Refresh rate (in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if rate is NULL
|
||||
*/
|
||||
uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Set the refresh rate (writing Refresh per command timing).
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] fspNum Frequency set number
|
||||
* @param[in] cycles Refresh rate (in cycles)
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if rate is NULL
|
||||
*/
|
||||
uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
|
||||
|
||||
/**
|
||||
* Handle Refreshing per chip select
|
||||
* @param[in] pD Driver state info specific to this instance.
|
||||
* @param[in] trefInterval status
|
||||
* @return CDN_EOK on success.
|
||||
* @return EINVAL if chipSelect is invalid
|
||||
*/
|
||||
uint32_t (*refreshperchipselect)(const lpddr4_privatedata* pd, const uint32_t trefinterval);
|
||||
|
||||
} LPDDR4_OBJ;
|
||||
|
||||
/**
|
||||
* In order to access the LPDDR4 APIs, the upper layer software must call
|
||||
* this global function to obtain the pointer to the driver object.
|
||||
* @return LPDDR4_OBJ* Driver Object Pointer
|
||||
*/
|
||||
extern LPDDR4_OBJ *lpddr4_getinstance(void);
|
||||
|
||||
#endif /* LPDDR4_OBJ_IF_H */
|
||||
2061
drivers/ram/k3-j721e/lpddr4_phy_core_macros.h
Normal file
2061
drivers/ram/k3-j721e/lpddr4_phy_core_macros.h
Normal file
File diff suppressed because it is too large
Load diff
5397
drivers/ram/k3-j721e/lpddr4_pi_macros.h
Normal file
5397
drivers/ram/k3-j721e/lpddr4_pi_macros.h
Normal file
File diff suppressed because it is too large
Load diff
56
drivers/ram/k3-j721e/lpddr4_private.h
Normal file
56
drivers/ram/k3-j721e/lpddr4_private.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2018 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
**********************************************************************
|
||||
* Cadence Core Driver for LPDDR4.
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_PRIV_H
|
||||
#define LPDDR4_PRIV_H
|
||||
|
||||
#define PRODUCT_ID (0x1046U)
|
||||
#define VERSION_0 (0x54d5da40U)
|
||||
#define VERSION_1 (0xc1865a1U)
|
||||
|
||||
#define BIT_MASK (0x1U)
|
||||
#define BYTE_MASK (0xffU)
|
||||
#define NIBBLE_MASK (0xfU)
|
||||
|
||||
#define WORD_SHIFT (32U)
|
||||
#define WORD_MASK (0xffffffffU)
|
||||
#define SLICE_WIDTH (0x100)
|
||||
/* Number of Data slices */
|
||||
#define DSLICE_NUM (4U)
|
||||
/*Number of Address Slices */
|
||||
#define ASLICE_NUM (1U)
|
||||
|
||||
/* Number of accessible registers in each slice */
|
||||
#define DSLICE0_REG_COUNT (140U)
|
||||
#define DSLICE1_REG_COUNT (140U)
|
||||
#define DSLICE2_REG_COUNT (140U)
|
||||
#define DSLICE3_REG_COUNT (140U)
|
||||
#define ASLICE0_REG_COUNT (52U)
|
||||
#define PHY_CORE_REG_COUNT (140U)
|
||||
|
||||
#define CTL_OFFSET 0
|
||||
#define PI_OFFSET (((uint32_t)1) << 11)
|
||||
#define PHY_OFFSET (((uint32_t)1) << 12)
|
||||
|
||||
/* BIT[17] on INT_MASK_1 register. */
|
||||
#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
|
||||
|
||||
/* Init Error information bits */
|
||||
#define PLL_READY (0x3U)
|
||||
#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
|
||||
#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
|
||||
#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
|
||||
#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U)
|
||||
#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U))
|
||||
#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
|
||||
#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U))
|
||||
#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U))
|
||||
#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U))
|
||||
|
||||
#endif /* LPDDR4_PRIV_H */
|
||||
1165
drivers/ram/k3-j721e/lpddr4_sanity.h
Normal file
1165
drivers/ram/k3-j721e/lpddr4_sanity.h
Normal file
File diff suppressed because it is too large
Load diff
121
drivers/ram/k3-j721e/lpddr4_structs_if.h
Normal file
121
drivers/ram/k3-j721e/lpddr4_structs_if.h
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/**********************************************************************
|
||||
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
|
||||
**********************************************************************
|
||||
* WARNING: This file is auto-generated using api-generator utility.
|
||||
* api-generator: 12.02.13bb8d5
|
||||
* Do not edit it manually.
|
||||
**********************************************************************
|
||||
* Cadence Core Driver for LPDDR4.
|
||||
**********************************************************************
|
||||
*/
|
||||
#ifndef LPDDR4_STRUCTS_IF_H
|
||||
#define LPDDR4_STRUCTS_IF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpddr4_if.h"
|
||||
|
||||
/** @defgroup DataStructure Dynamic Data Structures
|
||||
* This section defines the data structures used by the driver to provide
|
||||
* hardware information, modification and dynamic operation of the driver.
|
||||
* These data structures are defined in the header file of the core driver
|
||||
* and utilized by the API.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**********************************************************************
|
||||
* Structures and unions
|
||||
**********************************************************************/
|
||||
/**
|
||||
* Configuration of device.
|
||||
* Object of this type is used for probe and init functions.
|
||||
*/
|
||||
struct lpddr4_config_s
|
||||
{
|
||||
/** Base address of controller registers */
|
||||
struct lpddr4_ctlregs_s* ctlbase;
|
||||
/** Information/warning handler */
|
||||
lpddr4_infocallback infohandler;
|
||||
/** Controller interrupt handler */
|
||||
lpddr4_ctlcallback ctlinterrupthandler;
|
||||
/** PHY Independent Module interrupt handler */
|
||||
lpddr4_phyindepcallback phyindepinterrupthandler;
|
||||
};
|
||||
|
||||
/**
|
||||
* Structure contains private data for Core Driver that should not be used by
|
||||
* upper layers. This is not a part of API and manipulating of those data may cause
|
||||
* unpredictable behavior of Core Driver.
|
||||
*/
|
||||
struct lpddr4_privatedata_s
|
||||
{
|
||||
/** Base address of controller registers */
|
||||
struct lpddr4_ctlregs_s* ctlbase;
|
||||
/** Information/warning handler */
|
||||
lpddr4_infocallback infohandler;
|
||||
/** Controller interrupt handler */
|
||||
lpddr4_ctlcallback ctlinterrupthandler;
|
||||
/** PHY Independent Module interrupt handler */
|
||||
lpddr4_phyindepcallback phyindepinterrupthandler;
|
||||
};
|
||||
|
||||
/** Structure to contain debug information reported by the driver. */
|
||||
struct lpddr4_debuginfo_s
|
||||
{
|
||||
/** PLL Lock error. */
|
||||
bool pllerror;
|
||||
/** I/O calibration error. */
|
||||
bool iocaliberror;
|
||||
/** RX offset error. */
|
||||
bool rxoffseterror;
|
||||
/** CA training error. */
|
||||
bool catraingerror;
|
||||
/** Write levelling error. */
|
||||
bool wrlvlerror;
|
||||
/** Gate Level error. */
|
||||
bool gatelvlerror;
|
||||
/** Read Level error. */
|
||||
bool readlvlerror;
|
||||
/** Write DQ training error. */
|
||||
bool dqtrainingerror;
|
||||
};
|
||||
|
||||
/** Frequency Set Point mode register values */
|
||||
struct lpddr4_fspmoderegs_s
|
||||
{
|
||||
/** MR1 register data for the FSP. */
|
||||
uint8_t mr1data_fn[LPDDR4_MAX_CS];
|
||||
/** MR2 register data for the FSP. */
|
||||
uint8_t mr2data_fn[LPDDR4_MAX_CS];
|
||||
/** MR3 register data for the FSP. */
|
||||
uint8_t mr3data_fn[LPDDR4_MAX_CS];
|
||||
/** MR11 register data for the FSP. */
|
||||
uint8_t mr11data_fn[LPDDR4_MAX_CS];
|
||||
/** MR12 register data for the FSP. */
|
||||
uint8_t mr12data_fn[LPDDR4_MAX_CS];
|
||||
/** MR13 register data for the FSP. */
|
||||
uint8_t mr13data_fn[LPDDR4_MAX_CS];
|
||||
/** MR14 register data for the FSP. */
|
||||
uint8_t mr14data_fn[LPDDR4_MAX_CS];
|
||||
/** MR22 register data for the selected frequency. */
|
||||
uint8_t mr22data_fn[LPDDR4_MAX_CS];
|
||||
};
|
||||
|
||||
/** Structure to hold data set to initalise registers. */
|
||||
struct lpddr4_reginitdata_s
|
||||
{
|
||||
/** Register initialisation data for the Controller. */
|
||||
uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT];
|
||||
/** Should be set to true, if the corresponding denaliCtlReg element has been updated. */
|
||||
bool updatectlreg[LPDDR4_CTL_REG_COUNT];
|
||||
/** Register initialisation data for PHY independent module. */
|
||||
uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
|
||||
/** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */
|
||||
bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
|
||||
/** Register initialisation data for the PHY. */
|
||||
uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT];
|
||||
/** Should be set to true, if the corresponding denaliPhyReg element has been updated. */
|
||||
bool updatephyreg[LPDDR4_PHY_REG_COUNT];
|
||||
};
|
||||
|
||||
#endif /* LPDDR4_STRUCTS_IF_H */
|
||||
Loading…
Reference in a new issue