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ram: k3-am654: Do not rely on default values for certain DDR register
Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
James Doublesin
Tom Rini
parent
c78ac7a0c9
commit
34f27b2e86
4 changed files with 85 additions and 19 deletions
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@ -1,15 +1,16 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* This file was generated by the AM65x_DRA80xM EMIF Tool:
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* This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
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* http://www.ti.com/lit/pdf/spracj0
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* Configuration Parameters
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* Memory Type: DDR4
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* Data Rate: 1600
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* Data Rate: 1600 MT/s
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* ECC Enabled: No
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* Data Width: 32
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* Data Width: 32 bits
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*/
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#define DDR_PLL_FREQUENCY 400000000
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#define DDRSS_V2H_CTL_REG 0x000073FF
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#define DDRCTL_MSTR 0x41040010
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#define DDRCTL_RFSHCTL0 0x00210070
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#define DDRCTL_ECCCFG0 0x00000000
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@ -32,10 +33,10 @@
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#define DDRCTL_DRAMTMG5 0x04040302
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#define DDRCTL_DRAMTMG6 0x00000004
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#define DDRCTL_DRAMTMG7 0x00000404
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#define DDRCTL_DRAMTMG8 0x03030C05
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#define DDRCTL_DRAMTMG8 0x03030A05
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#define DDRCTL_DRAMTMG9 0x00020208
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#define DDRCTL_DRAMTMG10 0x001C180A
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#define DDRCTL_DRAMTMG11 0x1106010E
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#define DDRCTL_DRAMTMG11 0x0E06010E
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#define DDRCTL_DRAMTMG12 0x00020008
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#define DDRCTL_DRAMTMG13 0x0B100002
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#define DDRCTL_DRAMTMG14 0x00000000
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@ -47,7 +48,7 @@
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#define DDRCTL_DFITMG1 0x000A0606
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#define DDRCTL_DFITMG2 0x00000604
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#define DDRCTL_DFIMISC 0x00000001
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#define DDRCTL_ADDRMAP0 0x001F1F1F
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#define DDRCTL_ADDRMAP0 0x0000001F
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#define DDRCTL_ADDRMAP1 0x003F0808
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#define DDRCTL_ADDRMAP2 0x00000000
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#define DDRCTL_ADDRMAP3 0x00000000
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@ -83,13 +84,13 @@
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#define DDRPHY_DCR 0x0000040C
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#define DDRPHY_DTPR0 0x041A0B06
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#define DDRPHY_DTPR1 0x28140000
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#define DDRPHY_DTPR2 0x0034E300
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#define DDRPHY_DTPR3 0x02800800
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#define DDRPHY_DTPR2 0x0034E255
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#define DDRPHY_DTPR3 0x01D50800
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#define DDRPHY_DTPR4 0x31180805
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#define DDRPHY_DTPR5 0x00250B06
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#define DDRPHY_DTPR6 0x00000505
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#define DDRPHY_ZQCR 0x008A2A58
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#define DDRPHY_ZQ0PR0 0x000077DD
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#define DDRPHY_ZQ0PR0 0x000077DD
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#define DDRPHY_ZQ1PR0 0x000077DD
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#define DDRPHY_MR0 0x00000214
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#define DDRPHY_MR1 0x00000501
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@ -109,6 +110,8 @@
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#define DDRPHY_DX8SL2PLLCR0 0x021c4000
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#define DDRPHY_DTCR0 0x8000B1C7
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#define DDRPHY_DTCR1 0x00010236
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#define DDRPHY_ACIOCR0 0x30070000
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#define DDRPHY_ACIOCR3 0x00000001
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#define DDRPHY_ACIOCR5 0x04800000
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#define DDRPHY_IOVCR0 0x0F0C0C0C
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#define DDRPHY_DX0GCR0 0x00000000
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@ -148,9 +151,12 @@
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#define DDRPHY_DX3GTR0 0x00020002
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#define DDRPHY_DX4GTR0 0x00020002
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#define DDRPHY_ODTCR 0x00010000
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#define DDRPHY_DX8SL0IOCR 0x04800000
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#define DDRPHY_DX8SL1IOCR 0x04800000
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#define DDRPHY_DX8SL2IOCR 0x04800000
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#define DDRPHY_DX8SL0IOCR 0x74800000
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#define DDRPHY_DX8SL1IOCR 0x74800000
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#define DDRPHY_DX8SL2IOCR 0x74800000
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#define DDRPHY_DX8SL0DXCTL2 0x00141830
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#define DDRPHY_DX8SL1DXCTL2 0x00141830
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#define DDRPHY_DX8SL2DXCTL2 0x00141830
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#define DDRPHY_DX8SL0DQSCTL 0x01264000
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#define DDRPHY_DX8SL1DQSCTL 0x01264000
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#define DDRPHY_DX8SL2DQSCTL 0x01264000
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@ -17,6 +17,10 @@
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assigned-clock-rates = <DDR_PLL_FREQUENCY>;
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u-boot,dm-spl;
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ti,ss-reg = <
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DDRSS_V2H_CTL_REG
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>;
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ti,ctl-reg = <
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DDRCTL_DFIMISC
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DDRCTL_DFITMG0
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@ -132,12 +136,15 @@
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DDRPHY_DX8SL0DXCTL2
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DDRPHY_DX8SL0IOCR
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DDRPHY_DX8SL0PLLCR0
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DDRPHY_DX8SL0DQSCTL
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DDRPHY_DX8SL1DXCTL2
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DDRPHY_DX8SL1IOCR
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DDRPHY_DX8SL1PLLCR0
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DDRPHY_DX8SL1DQSCTL
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DDRPHY_DX8SL2DXCTL2
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DDRPHY_DX8SL2IOCR
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DDRPHY_DX8SL2PLLCR0
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DDRPHY_DX8SL2DQSCTL
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DDRPHY_DXCCR
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DDRPHY_ODTCR
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DDRPHY_PGCR0
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@ -168,6 +175,8 @@
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>;
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ti,phy-ioctl = <
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DDRPHY_ACIOCR0
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DDRPHY_ACIOCR3
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DDRPHY_ACIOCR5
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DDRPHY_IOVCR0
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>;
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@ -259,6 +259,8 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
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ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
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ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
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ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
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ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
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ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
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@ -294,6 +296,10 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
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debug("%s: DDR phy register configuration completed\n", __func__);
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}
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@ -479,18 +485,43 @@ int VREF_training(struct am654_ddrss_desc *ddrss)
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int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
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{
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x012640F7);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x012640F7);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x012640F7);
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u32 val;
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val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
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val &= ~0xFF;
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val |= 0xF7;
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
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val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
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val &= ~0xFF;
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val |= 0xF7;
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
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val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
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val &= ~0xFF;
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val |= 0xF7;
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
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sdelay(16);
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return 0;
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}
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int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
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{
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x01264000);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x01264000);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x01264000);
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u32 val;
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val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
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val &= ~0xFF;
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
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val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
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val &= ~0xFF;
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
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val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
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val &= ~0xFF;
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
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sdelay(16);
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return 0;
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}
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@ -595,12 +626,14 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
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{
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int ret;
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u32 val;
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struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
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debug("Starting DDR initialization...\n");
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debug("%s(ddrss=%p)\n", __func__, ddrss);
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ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
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ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
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reg->ddrss_v2h_ctl_reg);
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am654_ddrss_ctrl_configuration(ddrss);
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@ -901,6 +934,14 @@ static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
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}
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ddrss->ddrss_phy_cfg = (void *)reg;
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ret = dev_read_u32_array(dev, "ti,ss-reg",
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(u32 *)&ddrss->params.ss_reg,
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sizeof(ddrss->params.ss_reg) / sizeof(u32));
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if (ret) {
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dev_err(dev, "Cannot read ti,ss-reg params\n");
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return ret;
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}
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ret = dev_read_u32_array(dev, "ti,ctl-reg",
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(u32 *)&ddrss->params.ctl_reg,
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sizeof(ddrss->params.ctl_reg) / sizeof(u32));
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@ -996,6 +996,10 @@
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PGSR0_DIDONE_MASK)
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#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK)
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struct ddrss_ss_reg_params {
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u32 ddrss_v2h_ctl_reg;
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};
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struct ddrss_ddrctl_reg_params {
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u32 ddrctl_dfimisc;
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u32 ddrctl_dfitmg0;
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@ -1111,12 +1115,15 @@ struct ddrss_ddrphy_cfg_params {
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u32 ddrphy_dx8sl0dxctl2;
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u32 ddrphy_dx8sl0iocr;
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u32 ddrphy_dx8sl0pllcr0;
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u32 ddrphy_dx8sl0dqsctl;
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u32 ddrphy_dx8sl1dxctl2;
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u32 ddrphy_dx8sl1iocr;
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u32 ddrphy_dx8sl1pllcr0;
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u32 ddrphy_dx8sl1dqsctl;
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u32 ddrphy_dx8sl2dxctl2;
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u32 ddrphy_dx8sl2iocr;
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u32 ddrphy_dx8sl2pllcr0;
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u32 ddrphy_dx8sl2dqsctl;
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u32 ddrphy_dxccr;
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u32 ddrphy_odtcr;
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u32 ddrphy_pgcr0;
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@ -1147,6 +1154,8 @@ struct ddrss_ddrphy_ctrl_params {
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};
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struct ddrss_ddrphy_ioctl_params {
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u32 ddrphy_aciocr0;
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u32 ddrphy_aciocr3;
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u32 ddrphy_aciocr5;
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u32 ddrphy_iovcr0;
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};
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@ -1173,6 +1182,7 @@ struct ddrss_ddrphy_zq_params {
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};
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struct ddrss_params {
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struct ddrss_ss_reg_params ss_reg;
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struct ddrss_ddrctl_reg_params ctl_reg;
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struct ddrss_ddrctl_crc_params ctl_crc;
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struct ddrss_ddrctl_ecc_params ctl_ecc;
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