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clk: mediatek: fix clock-rate overflow problem

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This patch fix clock-rate overflow problem in mediatek
clock driver common part.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This commit is contained in:
Sam Shih 2020-01-10 16:30:30 +08:00 committed by Tom Rini
parent 72ab603b20
commit d8588ba55f
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/mediatek/clk-mtk.c
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@ -39,7 +39,7 @@
* this function is recursively called to find the parent to calculate
* the accurate frequency.
*/
static int mtk_clk_find_parent_rate(struct clk *clk, int id,
static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
const struct driver *drv)
{
struct clk parent = { .id = id, };
@ -285,7 +285,7 @@ static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
return rate;
}
static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
@ -307,7 +307,7 @@ static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
return mtk_factor_recalc_rate(fdiv, rate);
}
static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux = &priv->tree->muxes[off];