- Khadas VIM3L based on Amlogic S905D3 support

- Various fixups for amlogic boards
 - Unnecessary header includes drop into video/meson
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl4V0PgACgkQd9zb2sjI
 SdEuPw//c0APhovWXXCsRckccBF8SK3WRsVcj5M36g7WXVdUo+MXaPzDUEyDAMfU
 xS51FaN7lJJ7ntxEvJ3loFDYh0WrYoanCW+9KxMnJ0GVTdWg6nL0u4yq4exD9f4d
 N9Tv8NaN0y2Jn97Y3L70qlutVJjTzUd1oRKWmGDESvXj3+WrJdffEL0uBrCcbmF/
 kyEQ3RiDuGhfNrC/mSdhQFG2kmeQc43+Fb1OYq8Wm28zwtYvZuJpdn7FTtwGQk0+
 iCjIUN0RKcD+HedJVxHmSnOOTehydk6xQX9215ebo/tTz+WtoqXrFPjEr1mgAhRV
 ojEdJcEKAFGwTYuRDmeO6lwAv+k0fkF4drGi7uAOQa3JwD90aKgR0Ig80CzVq1vW
 m79WDHFbaQnpIGf94kONF8X0M9nWN9/XYmpJe6KuQaO7YEsIIBsbFP657pJp1J1m
 xfwzl2xlx7yaDeR8xv4/N67REuSF/ILeJA0tykkm7NEWkkBrz1d+dXiOaTceY/Wu
 z7s3QGpHINMOzuxMZKEZazt+0KQ4UlbAxYRQU3oNRkW3WaCoGimpbjC9FJa4FpoA
 Cx2PBRunzx8rK87ZS/X7VUa2v454MSkCGwpmqP+PrekoL2rsRNx/3gWHpzb+Z7E/
 nAd0uukYy/WSlzv6bfpRdemQi27gSvDnERf4dj/4kiAiMoKkeiA=
 =rkHZ
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20200108' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Khadas VIM3L based on Amlogic S905D3 support
- Various fixups for amlogic boards
- Unnecessary header includes drop into video/meson
This commit is contained in:
Tom Rini 2020-01-08 15:23:37 -05:00
commit 9af51fb3a5
15 changed files with 334 additions and 16 deletions

View file

@ -153,6 +153,7 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-g12a-sei510.dtb \
meson-g12b-odroid-n2.dtb \
meson-g12b-a311d-khadas-vim3.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-sei610.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \

View file

@ -0,0 +1,95 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/dts-v1/;
#include "meson-sm1.dtsi"
#include "meson-khadas-vim3.dtsi"
/ {
compatible = "khadas,vim3l", "amlogic,sm1";
model = "Khadas VIM3L";
vddcpu: regulator-vddcpu {
/*
* Silergy SY8030DEC Regulator.
*/
compatible = "pwm-regulator";
regulator-name = "VDDCPU";
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&vsys_3v3>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;
regulator-boot-on;
regulator-always-on;
};
};
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin1";
status = "okay";
};
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
* an USB3.0 Type A connector and a M.2 Key M slot. The PHY driving
* these differential lines is shared between the USB3.0 controller
* and the PCIe Controller, thus only a single controller can use it.
* If the MCU is configured to mux the PCIe/USB3.0 differential lines
* to the M.2 Key M slot, uncomment the following block to disable
* USB3.0 from the USB Complex and enable the PCIe controller.
* The End User is not expected to uncomment the following except for
* testing purposes, but instead rely on the firmware/bootloader to
* update these nodes accordingly if PCIe mode is selected by the MCU.
*/
/*
&pcie {
status = "okay";
};
&usb {
phys = <&usb2_phy0>, <&usb2_phy1>;
phy-names = "usb2-phy0", "usb2-phy1";
};
*/

View file

@ -8,6 +8,7 @@ config MESON64_COMMON
select DM_SERIAL
select SYSCON
select REGMAP
select PWRSEQ
select BOARD_LATE_INIT
imply CMD_DM

View file

@ -4,4 +4,5 @@ S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/w400/
F: configs/khadas-vim3_defconfig
F: configs/khadas-vim3l_defconfig
F: configs/odroid-n2_defconfig

View file

@ -0,0 +1,132 @@
U-Boot for Khadas VIM3L
=======================
Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion
Technology Co., Ltd. with the following specifications:
- Amlogic S905D3 Arm Cortex-A55 quad-core SoC
- 2GB LPDDR4 SDRAM
- Gigabit Ethernet
- HDMI 2.1 display
- 40-pin GPIO header
- 1 x USB 3.0 Host, 1 x USB 2.0 Host
- eMMC, microSD
- M.2
- Infrared receiver
Schematics are available on the manufacturer website.
Currently the U-Boot port supports the following devices:
- serial
- eMMC, microSD
- Ethernet
- I2C
- Regulators
- Reset controller
- Clock controller
- ADC
u-boot compilation
==================
> export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim3l_defconfig
> make
Image creation
==============
Amlogic doesn't provide sources for the firmware and for tools needed
to create the bootloader image, so it is necessary to obtain them from
the git tree published by the board vendor:
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
> tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
> export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
> DIR=vim3l-u-boot
> git clone --depth 1 \
https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
$DIR
> cd vim3l-u-boot
> make kvim3l_defconfig
> make
> export UBOOTDIR=$PWD
Go back to mainline U-Boot source tree then :
> mkdir fip
> cp $UBOOTDIR/build/scp_task/bl301.bin fip/
> cp $UBOOTDIR/build/board/khadas/kvim3l/firmware/acs.bin fip/
> cp $UBOOTDIR/fip/g12a/bl2.bin fip/
> cp $UBOOTDIR/fip/g12a/bl30.bin fip/
> cp $UBOOTDIR/fip/g12a/bl31.img fip/
> cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
> cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
> cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
> cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
> cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
> cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
> cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
> cp $UBOOTDIR/fip/g12a/piei.fw fip/
> cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
> cp u-boot.bin fip/bl33.bin
> sh fip/blx_fix.sh \
fip/bl30.bin \
fip/zero_tmp \
fip/bl30_zero.bin \
fip/bl301.bin \
fip/bl301_zero.bin \
fip/bl30_new.bin \
bl30
> sh fip/blx_fix.sh \
fip/bl2.bin \
fip/zero_tmp \
fip/bl2_zero.bin \
fip/acs.bin \
fip/bl21_zero.bin \
fip/bl2_new.bin \
bl2
> $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
--output fip/bl30_new.bin.g12a.enc \
--level v3
> $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
--output fip/bl30_new.bin.enc \
--level v3 --type bl30
> $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
--output fip/bl31.img.enc \
--level v3 --type bl31
> $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
--output fip/bl33.bin.enc \
--level v3 --type bl33 --compress lz4
> $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
--output fip/bl2.n.bin.sig
> $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
--output fip/u-boot.bin \
--bl2 fip/bl2.n.bin.sig \
--bl30 fip/bl30_new.bin.enc \
--bl31 fip/bl31.img.enc \
--bl33 fip/bl33.bin.enc \
--ddrfw1 fip/ddr4_1d.fw \
--ddrfw2 fip/ddr4_2d.fw \
--ddrfw3 fip/ddr3_1d.fw \
--ddrfw4 fip/piei.fw \
--ddrfw5 fip/lpddr4_1d.fw \
--ddrfw6 fip/lpddr4_2d.fw \
--ddrfw7 fip/diag_lpddr4.fw \
--ddrfw8 fip/aml_ddr.fw \
--ddrfw9 fip/lpddr3_1d.fw \
--level v3
and then write the image to SD with:
> DEV=/dev/your_sd_device
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
> dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

View file

@ -0,0 +1,62 @@
CONFIG_ARM=y
CONFIG_SYS_BOARD="w400"
CONFIG_ARCH_MESON=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_MESON_G12A=y
CONFIG_ENV_SIZE=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff803000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_IDENT_STRING=" khadas-vim3l"
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_POWER_DOMAIN=y
CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_MESON_G12A=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_MESON=y
CONFIG_VIDEO_DT_SIMPLEFB=y
CONFIG_OF_LIBFDT_OVERLAY=y

View file

@ -6,6 +6,10 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include "meson_vpu.h"
/* DMC Registers */

View file

@ -6,6 +6,11 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <linux/bitfield.h>
#include "meson_vpu.h"
/* OSDx_BLKx_CFG */

View file

@ -6,6 +6,8 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <edid.h>
#include "meson_vpu.h"
#include <linux/iopoll.h>

View file

@ -6,7 +6,11 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include <common.h>
#include <dm.h>
#include <edid.h>
#include <fdtdec.h>
#include <asm/io.h>
#include "meson_vpu.h"
enum {

View file

@ -6,13 +6,17 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson_vpu.h"
#include <common.h>
#include <display.h>
#include <dm.h>
#include <efi_loader.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <fdt_support.h>
#include <linux/sizes.h>
#include <asm/arch/mem.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include "meson_vpu.h"
#include "meson_registers.h"
#include "simplefb_common.h"
@ -27,6 +31,14 @@ static struct meson_framebuffer {
bool is_cvbs;
} meson_fb = { 0 };
bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
enum vpu_compatible family)
{
enum vpu_compatible compat = dev_get_driver_data(priv->dev);
return compat == family;
}
static int meson_vpu_setup_mode(struct udevice *dev, struct udevice *disp)
{
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);

View file

@ -9,14 +9,12 @@
#ifndef __MESON_VPU_H__
#define __MESON_VPU_H__
#include <common.h>
#include <dm.h>
#include <video.h>
#include <display.h>
#include <linux/io.h>
#include <linux/bitfield.h>
#include "meson_registers.h"
struct display_timing;
struct udevice;
enum {
/* Maximum size we support */
VPU_MAX_WIDTH = 3840,
@ -38,13 +36,8 @@ struct meson_vpu_priv {
void __iomem *dmc_base;
};
static inline bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
enum vpu_compatible family)
{
enum vpu_compatible compat = dev_get_driver_data(priv->dev);
return compat == family;
}
bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
enum vpu_compatible family);
#define hhi_update_bits(offset, mask, value) \
writel_bits(mask, value, priv->hhi_base + offset)

View file

@ -8,6 +8,10 @@
#define DEBUG
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include "meson_vpu.h"
/* HHI Registers */

View file

@ -8,7 +8,7 @@
#define __MESON64_CONFIG_H
/* Generic Interrupt Controller Definitions */
#if defined(CONFIG_MESON_AXG)
#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
#define GICD_BASE 0xffc01000
#define GICC_BASE 0xffc02000
#else /* MESON GXL and GXBB */

View file

@ -17,6 +17,8 @@
#include <stdio_dev.h>
struct udevice;
struct video_uc_platdata {
uint align;
uint size;