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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Browse source 
Updates and fixes for ls1028a, lx2160a, ls1012a, ls1021a, ls2080a,
ls1088a platforms:
- lx2-rev2 pcie support, enetc related updates, layerscape-pcie fixes
This commit is contained in:
Tom Rini 2020-01-25 12:20:51 -05:00
commit 40521a6c90
48 changed files with 481 additions and 133 deletions
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10
arch/arm/Kconfig
View file

@ -1141,7 +1141,6 @@ config TARGET_VEXPRESS64_JUNO
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
select ARCH_LS2080A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select FSL_DDR_SYNC_REFRESH
@ -1154,7 +1153,6 @@ config TARGET_LS2080A_EMU
config TARGET_LS2080A_SIMU
bool "Support ls2080a_simu"
select ARCH_LS2080A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
@ -1167,7 +1165,6 @@ config TARGET_LS2080A_SIMU
config TARGET_LS1088AQDS
bool "Support ls1088aqds"
select ARCH_LS1088A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@ -1183,7 +1180,6 @@ config TARGET_LS1088AQDS
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARCH_LS2080A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@ -1202,7 +1198,6 @@ config TARGET_LS2080AQDS
config TARGET_LS2080ARDB
bool "Support ls2080ardb"
select ARCH_LS2080A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@ -1221,7 +1216,6 @@ config TARGET_LS2080ARDB
config TARGET_LS2081ARDB
bool "Support ls2081ardb"
select ARCH_LS2080A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
@ -1235,7 +1229,6 @@ config TARGET_LS2081ARDB
config TARGET_LX2160ARDB
bool "Support lx2160ardb"
select ARCH_LX2160A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@ -1249,7 +1242,6 @@ config TARGET_LX2160ARDB
config TARGET_LX2160AQDS
bool "Support lx2160aqds"
select ARCH_LX2160A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@ -1372,7 +1364,6 @@ config TARGET_LS1028AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select ARCH_MISC_INIT
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@ -1394,7 +1385,6 @@ config TARGET_LS1028ARDB
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT

3
arch/arm/cpu/armv7/ls102xa/Kconfig
View file

@ -29,11 +29,9 @@ menu "LS102xA architecture"
config LS1_DEEP_SLEEP
bool "Deep sleep"
depends on ARCH_LS1021A
config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA"
depends on ARCH_LS1021A
default 2
help
Set this number to the maximum number of possible CPUs in the SoC.
@ -98,7 +96,6 @@ config SYS_HAS_SERDES
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A
default 8
config SYS_FSL_ERRATUM_A008407

1
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -242,6 +242,7 @@ config FSL_LSCH2
select SYS_FSL_SEC_BE
config FSL_LSCH3
select ARCH_MISC_INIT
bool
config NXP_LSCH3_2

14
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View file

@ -1632,3 +1632,17 @@ __weak int dram_init(void)
return 0;
}
#ifdef CONFIG_ARCH_MISC_INIT
__weak int serdes_misc_init(void)
{
return 0;
}
int arch_misc_init(void)
{
serdes_misc_init();
return 0;
}
#endif

59
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View file

@ -600,3 +600,62 @@ void fsl_serdes_init(void)
serdes3_prtcl_map);
#endif
}
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
char scfg[16], snum[16];
int cfgr = 0;
u32 cfg;
cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
cfg = serdes_get_number(sd, cfg);
#if defined(SRDS_BITS_PER_LANE)
/*
* reverse lanes, lane 0 should be printed first so it must be moved to
* high order bits.
* For example bb58 should read 85bb, lane 0 being protocol 8.
* This only applies to SoCs that define SRDS_BITS_PER_LANE and have
* independent per-lane protocol configuration, at this time LS1028A and
* LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
* lanes as a single value.
*/
for (int i = 0; i < SRDS_MAX_LANES; i++) {
int tmp;
tmp = cfg >> (i * SRDS_BITS_PER_LANE);
tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
cfgr |= tmp;
}
#endif /* SRDS_BITS_PER_LANE */
snprintf(snum, 16, "serdes%d", sd);
snprintf(scfg, 16, "%x", cfgr);
env_set(snum, scfg);
return 0;
}
int serdes_misc_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
FSL_CHASSIS3_SRDS3_PRTCL_MASK,
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
#endif
return 0;
}

4
arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c
View file

@ -35,6 +35,10 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} },
{0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} },
{0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} },
{0x7777, {SGMII1, SGMII2, SGMII3, SGMII4} },
{0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
{0xb998, {SGMII_T1, SGMII2, SGMII3, PCIE1} },
{0xbb56, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} },
{}
};

23
arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
View file

@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
struct serdes_config {
u8 ip_protocol;
@ -32,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
@ -48,6 +51,15 @@ static struct serdes_config *serdes_cfg_tbl[] = {
serdes2_cfg_tbl,
};
bool soc_has_mac1(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
unsigned int version = SVR_SOC_VER(svr);
return (version == SVR_LS1088A || version == SVR_LS1084A);
}
int serdes_get_number(int serdes, int cfg)
{
struct serdes_config *ptr;
@ -87,7 +99,14 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/*
* LS1044A/1048A support only one XFI port
* Disable MAC1 for LS1044A/1048A
*/
if (serdes == FSL_SRDS_1 && lane == 2) {
if (!soc_has_mac1())
return 0;
}
ptr = serdes_cfg_tbl[serdes];
while (ptr->ip_protocol) {
if (ptr->ip_protocol == cfg)

5
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -647,6 +647,11 @@ void fsl_lsch2_early_init_f(void)
SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
SCFG_SNPCNFGCR_SATAWRSNP);
#elif defined(CONFIG_ARCH_LS1012A)
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
SCFG_SNPCNFGCR_SATAWRSNP);
#else
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP |

2
arch/arm/include/asm/arch-fsl-layerscape/config.h
View file

@ -123,6 +123,7 @@
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
/* TZ Protection Controller Definitions */
#define TZPC_BASE 0x02200000
@ -252,6 +253,7 @@
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */

9
board/freescale/ls1028a/ls1028a.c
View file

@ -25,6 +25,7 @@
#include <fdtdec.h>
#include <miiphy.h>
#include "../common/qixis.h"
#include "../drivers/net/fsl_enetc.h"
DECLARE_GLOBAL_DATA_PTR;
@ -108,8 +109,8 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
config_board_mux();
@ -162,6 +163,10 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_icid(blob);
#ifdef CONFIG_FSL_ENETC
fdt_fixup_enetc_mac(blob);
#endif
return 0;
}
#endif

2
board/freescale/ls1046afrwy/eth.c
View file

@ -53,6 +53,8 @@ int board_eth_init(bd_t *bis)
fm_info_set_mdio(FM1_DTSEC10, dev);
fm_info_set_mdio(FM1_DTSEC1, dev);
fm_disable_port(FM1_DTSEC9);
cpu_eth_init(bis);
#endif

7
board/freescale/ls1088a/ls1088a.c
View file

@ -811,13 +811,6 @@ void detail_board_ddr_info(void)
print_ddr_info(0);
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
return 0;
}
#endif
#ifdef CONFIG_FSL_MC_ENET
void board_quiesce_devices(void)
{

7
board/freescale/ls2080a/ls2080a.c
View file

@ -49,13 +49,6 @@ void detail_board_ddr_info(void)
#endif
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
return 0;
}
#endif
int board_eth_init(bd_t *bis)
{
int error = 0;

7
board/freescale/ls2080aqds/ls2080aqds.c
View file

@ -289,13 +289,6 @@ void detail_board_ddr_info(void)
#endif
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
return 0;
}
#endif
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
void fdt_fixup_board_enet(void *fdt)
{

7
board/freescale/ls2080ardb/ls2080ardb.c
View file

@ -318,13 +318,6 @@ void detail_board_ddr_info(void)
#endif
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
return 0;
}
#endif
#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{

23
board/freescale/lx2160a/lx2160a.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Copyright 2018-2020 NXP
*/
#include <common.h>
@ -132,7 +132,7 @@ int board_fix_fdt(void *fdt)
{ "ccsr", "dbi" },
{ "pf_ctrl", "ctrl" }
};
int off = -1, i;
int off = -1, i = 0;
if (IS_SVR_REV(get_svr(), 1, 0))
return 0;
@ -149,7 +149,7 @@ int board_fix_fdt(void *fdt)
reg_name = reg_names;
remaining_names_len = names_len - (reg_name - reg_names);
for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
old_name_len = strlen(reg_names_map[i].old_str);
new_name_len = strlen(reg_names_map[i].new_str);
if (memcmp(reg_name, reg_names_map[i].old_str,
@ -165,6 +165,7 @@ int board_fix_fdt(void *fdt)
new_name_len);
names_len -= old_name_len;
names_len += new_name_len;
i++;
}
reg_name = memchr(reg_name, '\0', remaining_names_len);
@ -191,9 +192,9 @@ void esdhc_dspi_status_fixup(void *blob)
{
const char esdhc0_path[] = "/soc/esdhc@2140000";
const char esdhc1_path[] = "/soc/esdhc@2150000";
const char dspi0_path[] = "/soc/dspi@2100000";
const char dspi1_path[] = "/soc/dspi@2110000";
const char dspi2_path[] = "/soc/dspi@2120000";
const char dspi0_path[] = "/soc/spi@2100000";
const char dspi1_path[] = "/soc/spi@2110000";
const char dspi2_path[] = "/soc/spi@2120000";
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
@ -243,10 +244,12 @@ void esdhc_dspi_status_fixup(void *blob)
& FSL_CHASSIS3_IIC5_PMUX_MASK;
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
if (iic5_pmux == IIC5_PMUX_SPI3) {
if (iic5_pmux == IIC5_PMUX_SPI3)
do_fixup_by_path(blob, dspi2_path, "status", "okay",
sizeof("okay"), 1);
}
else
do_fixup_by_path(blob, dspi2_path, "status", "disabled",
sizeof("disabled"), 1);
}
#endif
@ -580,8 +583,8 @@ void detail_board_ddr_info(void)
print_ddr_info(0);
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
config_board_mux();

1
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
View file

@ -53,4 +53,5 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_CMD_SETEXPR=y
CONFIG_RSA_SOFTWARE_EXP=y

4
configs/ls1012afrwy_tfa_defconfig
View file

@ -55,4 +55,8 @@ CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_XHCI_DWC3=y

2
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
View file

@ -30,7 +30,7 @@ CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=1
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_OF_CONTROL=y

2
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
View file

@ -27,7 +27,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"

4
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View file

@ -17,6 +17,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
@ -51,8 +52,10 @@ CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
@ -73,5 +76,6 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_RSA=y
CONFIG_CMD_SETEXPR=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

3
configs/ls1028aqds_tfa_defconfig
View file

@ -18,6 +18,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
@ -57,8 +58,10 @@ CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_MDIO_MUX_I2CREG=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

1
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
View file

@ -73,5 +73,6 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_WDT=y
CONFIG_WDT_SP805=y
CONFIG_RSA=y
CONFIG_CMD_SETEXPR=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

1
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
View file

@ -62,4 +62,5 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_CMD_SETEXPR=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

1
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
View file

@ -56,3 +56,4 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_SETEXPR=y

4
configs/ls1046afrwy_tfa_defconfig
View file

@ -56,5 +56,9 @@ CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y

1
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
View file

@ -61,3 +61,4 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_SETEXPR=y

1
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
View file

@ -54,3 +54,4 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_RSA=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_SETEXPR=y

2
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
View file

@ -27,7 +27,7 @@ CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SETEXPR=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"

4
configs/ls1088ardb_tfa_defconfig
View file

@ -72,4 +72,8 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

2
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
View file

@ -28,7 +28,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y

4
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
View file

@ -17,6 +17,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
@ -27,6 +28,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
@ -55,6 +57,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
@ -70,3 +73,4 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_SETEXPR=y

2
configs/lx2160aqds_tfa_defconfig
View file

@ -18,6 +18,7 @@ CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
@ -57,6 +58,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y

4
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
View file

@ -18,6 +18,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
@ -28,6 +29,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
@ -51,6 +53,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
@ -65,3 +68,4 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_SETEXPR=y

2
configs/lx2160ardb_tfa_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
@ -56,6 +57,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y

156
drivers/net/fsl_enetc.c
View file

@ -14,6 +14,69 @@
#include "fsl_enetc.h"
#define ENETC_DRIVER_NAME "enetc_eth"
/*
* sets the MAC address in IERB registers, this setting is persistent and
* carried over to Linux.
*/
static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn,
const u8 *enetaddr)
{
#ifdef CONFIG_ARCH_LS1028A
/*
* LS1028A is the only part with IERB at this time and there are plans to change
* its structure, keep this LS1028A specific for now
*/
#define IERB_BASE 0x1f0800000ULL
#define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \
+ (n) * 4)
static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
u16 lower = *(const u16 *)(enetaddr + 4);
u32 upper = *(const u32 *)enetaddr;
if (ierb_fn_to_pf[devfn] < 0)
return;
out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper);
out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower);
#endif
}
/* sets up primary MAC addresses in DT/IERB */
void fdt_fixup_enetc_mac(void *blob)
{
struct pci_child_platdata *ppdata;
struct eth_pdata *pdata;
struct udevice *dev;
struct uclass *uc;
char path[256];
int offset;
int devfn;
uclass_get(UCLASS_ETH, &uc);
uclass_foreach_dev(dev, uc) {
if (!dev->driver || !dev->driver->name ||
strcmp(dev->driver->name, ENETC_DRIVER_NAME))
continue;
pdata = dev_get_platdata(dev);
ppdata = dev_get_parent_platdata(dev);
devfn = PCI_FUNC(ppdata->devfn);
enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr);
snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x",
PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn));
offset = fdt_path_offset(blob, path);
if (offset < 0)
continue;
fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6);
}
}
/*
* Bind the device:
* - set a more explicit name on the interface
@ -122,16 +185,34 @@ static int enetc_init_rgmii(struct udevice *dev)
return 0;
}
/* set up MAC and serdes for SXGMII */
static int enetc_init_sxgmii(struct udevice *dev)
/* set up MAC configuration for the given interface type */
static void enetc_setup_mac_iface(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
u32 if_mode;
/* set ifmode to (US)XGMII */
if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
switch (priv->if_type) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
enetc_init_rgmii(dev);
break;
case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_USXGMII:
case PHY_INTERFACE_MODE_XFI:
/* set ifmode to (US)XGMII */
if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
break;
};
}
/* set up serdes for SXGMII */
static int enetc_init_sxgmii(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
if (!enetc_has_imdio(dev))
return 0;
@ -267,14 +348,57 @@ static int enetc_remove(struct udevice *dev)
return 0;
}
/* ENETC Port MAC address registers, accepts big-endian format */
static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
/*
* LS1028A is the only part with IERB at this time and there are plans to
* change its structure, keep this LS1028A specific for now.
*/
#define LS1028A_IERB_BASE 0x1f0800000ULL
#define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \
+ (pf) * 0x100 + (vf) * 8)
#define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4)
static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
{
struct pci_child_platdata *ppdata = dev_get_parent_platdata(dev);
const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
struct eth_pdata *plat = dev_get_platdata(dev);
int devfn = PCI_FUNC(ppdata->devfn);
u8 *addr = plat->enetaddr;
u32 lower, upper;
int pf;
if (devfn >= ARRAY_SIZE(devfn_to_pf))
return 0;
pf = devfn_to_pf[devfn];
if (pf < 0)
return 0;
lower = *(const u16 *)(addr + 4);
upper = *(const u32 *)addr;
out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper);
out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower);
return 0;
}
static int enetc_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct enetc_priv *priv = dev_get_priv(dev);
u8 *addr = plat->enetaddr;
if (IS_ENABLED(CONFIG_ARCH_LS1028A))
return enetc_ls1028a_write_hwaddr(dev);
u16 lower = *(const u16 *)(addr + 4);
u32 upper = *(const u32 *)addr;
enetc_write_port(priv, ENETC_PSIPMAR0, upper);
enetc_write_port(priv, ENETC_PSIPMAR1, lower);
return 0;
}
/* Configure port parameters (# of rings, frame size, enable port) */
@ -405,7 +529,6 @@ static void enetc_setup_rx_bdr(struct udevice *dev)
*/
static int enetc_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct enetc_priv *priv = dev_get_priv(dev);
/* reset and enable the PCI device */
@ -413,23 +536,13 @@ static int enetc_start(struct udevice *dev)
dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
if (!is_valid_ethaddr(plat->enetaddr)) {
enetc_dbg(dev, "invalid MAC address, generate random ...\n");
net_random_ethaddr(plat->enetaddr);
}
enetc_set_primary_mac_addr(priv, plat->enetaddr);
enetc_enable_si_port(priv);
/* setup Tx/Rx buffer descriptors */
enetc_setup_tx_bdr(dev);
enetc_setup_rx_bdr(dev);
if (priv->if_type == PHY_INTERFACE_MODE_RGMII ||
priv->if_type == PHY_INTERFACE_MODE_RGMII_ID ||
priv->if_type == PHY_INTERFACE_MODE_RGMII_RXID ||
priv->if_type == PHY_INTERFACE_MODE_RGMII_TXID)
enetc_init_rgmii(dev);
enetc_setup_mac_iface(dev);
if (priv->phy)
phy_startup(priv->phy);
@ -548,10 +661,11 @@ static const struct eth_ops enetc_ops = {
.send = enetc_send,
.recv = enetc_recv,
.stop = enetc_stop,
.write_hwaddr = enetc_write_hwaddr,
};
U_BOOT_DRIVER(eth_enetc) = {
.name = "enetc_eth",
.name = ENETC_DRIVER_NAME,
.id = UCLASS_ETH,
.bind = enetc_bind,
.probe = enetc_probe,

3
drivers/net/fsl_enetc.h
View file

@ -227,4 +227,7 @@ int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
int reg, u16 val);
/* sets up primary MAC addresses in DT/IERB */
void fdt_fixup_enetc_mac(void *blob);
#endif /* _ENETC_H */

5
drivers/pci/Makefile
View file

@ -34,9 +34,10 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o pcie_layerscape_fixup_common.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o pcie_layerscape.o
pcie_layerscape_gen4_fixup.o \
pcie_layerscape_fixup_common.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o

13
drivers/pci/pcie_layerscape.c
View file

@ -312,20 +312,9 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
/* Disable all bars in RC mode */
static void ls_pcie_disable_bars(struct ls_pcie *pcie)
{
u32 sriov;
sriov = in_le32(pcie->dbi + PCIE_SRIOV);
/*
* TODO: For PCIe controller with SRIOV, the method to disable bars
* is different and more complex, so will add later.
*/
if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
return;
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
}
static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)

23
drivers/pci/pcie_layerscape_fixup.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2019 NXP
* Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@ -17,6 +17,7 @@
#include <asm/arch/clock.h>
#endif
#include "pcie_layerscape.h"
#include "pcie_layerscape_fixup_common.h"
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
@ -30,17 +31,6 @@ static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
return -ENOSPC; /* LUT is full */
}
/* returns the next available streamid for pcie, -errno if failed */
static int ls_pcie_next_streamid(void)
{
static int next_stream_id = FSL_PEX_STREAM_ID_START;
if (next_stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
return next_stream_id++;
}
static void lut_writel(struct ls_pcie *pcie, unsigned int value,
unsigned int offset)
{
@ -191,10 +181,12 @@ static void fdt_fixup_pcie_ls(void *blob)
bus = bus->parent;
pcie = dev_get_priv(bus);
streamid = ls_pcie_next_streamid();
streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
if (streamid < 0) {
debug("ERROR: no stream ids free\n");
continue;
} else {
pcie->stream_id_cur++;
}
index = ls_pcie_next_lut_index(pcie);
@ -215,6 +207,7 @@ static void fdt_fixup_pcie_ls(void *blob)
fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
streamid);
}
pcie_board_fix_fdt(blob);
}
#endif
@ -271,7 +264,7 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
}
/* Fixup Kernel DT for PCIe */
void ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup_ls(void *blob, bd_t *bd)
{
struct ls_pcie *pcie;
@ -284,7 +277,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
}
#else /* !CONFIG_OF_BOARD_SETUP */
void ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup_ls(void *blob, bd_t *bd)
{
}
#endif

124
drivers/pci/pcie_layerscape_fixup_common.c Normal file
View file

@ -0,0 +1,124 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2020 NXP
*
* PCIe DT fixup for NXP Layerscape SoCs
* Author: Wasim Khan <wasim.khan@nxp.com>
*
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include "pcie_layerscape_fixup_common.h"
void ft_pci_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
uint svr;
svr = SVR_SOC_VER(get_svr());
if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
ft_pci_setup_ls_gen4(blob, bd);
else
#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
ft_pci_setup_ls(blob, bd);
}
#if defined(CONFIG_FSL_LAYERSCAPE)
int lx2_board_fix_fdt(void *fdt)
{
char *reg_name, *old_str, *new_str;
const char *reg_names;
int names_len, old_str_len, new_str_len, remaining_str_len;
struct str_map {
char *old_str;
char *new_str;
} reg_names_map[] = {
{ "csr_axi_slave", "regs" },
{ "config_axi_slave", "config" }
};
int off = -1, i;
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
while (off != -FDT_ERR_NOTFOUND) {
fdt_setprop(fdt, off, "compatible", "fsl,ls2088a-pcie",
strlen("fsl,ls2088a-pcie") + 1);
reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
if (!reg_names)
continue;
reg_name = (char *)reg_names;
remaining_str_len = names_len - (reg_name - reg_names);
i = 0;
while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
old_str = reg_names_map[i].old_str;
new_str = reg_names_map[i].new_str;
old_str_len = strlen(old_str);
new_str_len = strlen(new_str);
if (memcmp(reg_name, old_str, old_str_len) == 0) {
/* first only leave required bytes for new_str
* and copy rest of the string after it
*/
memcpy(reg_name + new_str_len,
reg_name + old_str_len,
remaining_str_len - old_str_len);
/* Now copy new_str */
memcpy(reg_name, new_str, new_str_len);
names_len -= old_str_len;
names_len += new_str_len;
i++;
}
reg_name = memchr(reg_name, '\0', remaining_str_len);
if (!reg_name)
break;
reg_name += 1;
remaining_str_len = names_len - (reg_name - reg_names);
}
fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
fdt_delprop(fdt, off, "apio-wins");
fdt_delprop(fdt, off, "ppio-wins");
off = fdt_node_offset_by_compatible(fdt, off,
"fsl,lx2160a-pcie");
}
return 0;
}
int pcie_board_fix_fdt(void *fdt)
{
uint svr;
svr = SVR_SOC_VER(get_svr());
if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0))
return lx2_board_fix_fdt(fdt);
return 0;
}
#ifdef CONFIG_ARCH_LX2160A
/* returns the next available streamid for pcie, -errno if failed */
int pcie_next_streamid(int currentid, int idx)
{
if (currentid > FSL_PEX_STREAM_ID_END)
return -EINVAL;
return currentid | ((idx + 1) << 11);
}
#else
/* returns the next available streamid for pcie, -errno if failed */
int pcie_next_streamid(int currentid, int idx)
{
static int next_stream_id = FSL_PEX_STREAM_ID_START;
if (next_stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
return next_stream_id++;
}
#endif
#endif /* CONFIG_FSL_LAYERSCAPE */

22
drivers/pci/pcie_layerscape_fixup_common.h Normal file
View file

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019-2020 NXP
*
* PCIe DT fixup for NXP Layerscape SoCs
* Author: Wasim Khan <wasim.khan@nxp.com>
*
*/
#ifndef _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
#define _PCIE_LAYERSCAPE_FIXUP_COMMON_H_
#include <common.h>
void ft_pci_setup_ls(void *blob, bd_t *bd);
#ifdef CONFIG_PCIE_LAYERSCAPE_GEN4
void ft_pci_setup_ls_gen4(void *blob, bd_t *bd);
#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
int pcie_next_streamid(int currentid, int id);
int pcie_board_fix_fdt(void *fdt);
#endif //_PCIE_LAYERSCAPE_FIXUP_COMMON_H_

24
drivers/pci/pcie_layerscape_gen4_fixup.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2018-2019 NXP
* Copyright 2018-2020 NXP
*
* PCIe Gen4 driver for NXP Layerscape SoCs
* Author: Hou Zhiqiang <Minder.Hou@gmail.com>
@ -19,6 +19,7 @@
#include <asm/arch/clock.h>
#endif
#include "pcie_layerscape_gen4.h"
#include "pcie_layerscape_fixup_common.h"
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
/*
@ -32,19 +33,6 @@ static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
return -ENOSPC; /* LUT is full */
}
/* returns the next available streamid for pcie, -errno if failed */
static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
{
int stream_id = pcie->stream_id_cur;
if (stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
pcie->stream_id_cur++;
return stream_id | ((pcie->idx + 1) << 11);
}
/*
* Program a single LUT entry
*/
@ -161,10 +149,12 @@ static void fdt_fixup_pcie_ls_gen4(void *blob)
bus = bus->parent;
pcie = dev_get_priv(bus);
streamid = ls_pcie_g4_next_streamid(pcie);
streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
if (streamid < 0) {
debug("ERROR: no stream ids free\n");
continue;
} else {
pcie->stream_id_cur++;
}
index = ls_pcie_g4_next_lut_index(pcie);
@ -234,7 +224,7 @@ static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
}
/* Fixup Kernel DT for PCIe */
void ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
{
struct ls_pcie_g4 *pcie;
@ -247,7 +237,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
}
#else /* !CONFIG_OF_BOARD_SETUP */
void ft_pci_setup(void *blob, bd_t *bd)
void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
{
}
#endif

2
include/configs/ls1012afrwy.h
View file

@ -63,7 +63,7 @@
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernelheader_size=0x40000\0" \
"kernel_addr_r=0x81000000\0" \
"kernel_addr_r=0x96000000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0x96000000\0" \
"kernel_size=0x2800000\0" \

2
include/configs/ls1012ardb.h
View file

@ -69,7 +69,7 @@
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x81000000\0" \
"kernel_addr_r=0x96000000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \

4
include/configs/lx2160a_common.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018-2019 NXP
* Copyright 2018-2020 NXP
*/
#ifndef __LX2_COMMON_H
@ -229,8 +229,6 @@ unsigned long get_board_ddr_clk(void);
BOOTENV \
"mcmemsize=0x70000000\0" \
XSPI_MC_INIT_CMD \
"boot_scripts=lx2160ardb_boot.scr\0" \
"boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \

4
include/configs/lx2160aqds.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018-2019 NXP
* Copyright 2018-2020 NXP
*/
#ifndef __LX2_QDS_H
@ -120,6 +120,8 @@ u8 qixis_esdhc_detect_quirk(void);
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
"lx2160aqds_vdd_mv=800\0" \
"boot_scripts=lx2160aqds_boot.scr\0" \
"boot_script_hdr=hdr_lx2160aqds_bs.out\0" \
"BOARD=lx2160aqds\0" \
"xspi_bootcmd=echo Trying load from flexspi..;" \
"sf probe 0:0 && sf read $load_addr " \

4
include/configs/lx2160ardb.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Copyright 2018,2020 NXP
*/
#ifndef __LX2_RDB_H
@ -89,6 +89,8 @@
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
"boot_scripts=lx2160ardb_boot.scr\0" \
"boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
"lx2160ardb_vdd_mv=800\0" \
"BOARD=lx2160ardb\0" \
"xspi_bootcmd=echo Trying load from flexspi..;" \