mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
- H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
This commit is contained in:
commit
cc64810dc6
56 changed files with 359 additions and 94 deletions
|
@ -540,6 +540,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
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sun50i-a64-nanopi-a64.dtb \
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sun50i-a64-oceanic-5205-5inmfd.dtb \
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sun50i-a64-olinuxino.dtb \
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sun50i-a64-olinuxino-emmc.dtb \
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sun50i-a64-orangepi-win.dtb \
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sun50i-a64-pine64-lts.dtb \
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sun50i-a64-pine64-plus.dtb \
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23
arch/arm/dts/sun50i-a64-olinuxino-emmc.dts
Normal file
23
arch/arm/dts/sun50i-a64-olinuxino-emmc.dts
Normal file
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Martin Ayotte <martinayotte@gmail.com>
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* Copyright (C) 2019 Sunil Mohan Adapa <sunil@medhas.org>
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*/
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#include "sun50i-a64-olinuxino.dts"
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/ {
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model = "Olimex A64-Olinuxino-eMMC";
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compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64";
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};
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_pins>;
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vmmc-supply = <®_dcdc1>;
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vqmmc-supply = <®_dcdc1>;
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bus-width = <8>;
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non-removable;
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cap-mmc-hw-reset;
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status = "okay";
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};
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12
arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi
Normal file
12
arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi
Normal file
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@ -0,0 +1,12 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include "sunxi-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &spi0;
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};
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};
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@ -14,6 +14,7 @@
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compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
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aliases {
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ethernet0 = &emac;
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serial0 = &uart0;
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};
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@ -21,6 +22,17 @@
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stdout-path = "serial0:115200n8";
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};
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connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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@ -41,6 +53,40 @@
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};
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};
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&de {
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status = "okay";
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};
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&ehci0 {
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status = "okay";
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};
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&ext_rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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phy-supply = <®_aldo2>;
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status = "okay";
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};
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&hdmi {
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status = "okay";
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};
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&hdmi_out {
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hdmi_out_con: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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&mdio {
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ext_rgmii_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mmc0 {
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vmmc-supply = <®_cldo1>;
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
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@ -57,6 +103,15 @@
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status = "okay";
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};
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&ohci0 {
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status = "okay";
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};
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&pio {
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vcc-pd-supply = <®_cldo1>;
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vcc-pg-supply = <®_aldo1>;
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};
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&r_i2c {
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status = "okay";
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@ -177,8 +232,29 @@
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};
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};
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&r_pio {
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/*
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* PL0 and PL1 are used for PMIC I2C
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* don't enable the pl-supply else
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* it will fail at boot
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*
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* vcc-pl-supply = <®_aldo1>;
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*/
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vcc-pm-supply = <®_aldo1>;
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_ph_pins>;
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status = "okay";
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};
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&usb2otg {
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dr_mode = "host";
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status = "okay";
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};
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&usb2phy {
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usb0_vbus-supply = <®_vcc5v>;
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status = "okay";
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};
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@ -127,6 +127,12 @@
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status = "okay";
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};
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&pio {
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vcc-pc-supply = <®_bldo2>;
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vcc-pd-supply = <®_cldo1>;
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vcc-pg-supply = <®_aldo1>;
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};
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&r_i2c {
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status = "okay";
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@ -243,10 +249,16 @@
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pcf8563: rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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interrupt-parent = <&r_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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#clock-cells = <0>;
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};
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};
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&r_pio {
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vcc-pm-supply = <®_aldo1>;
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_ph_pins>;
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@ -101,7 +101,7 @@
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#size-cells = <1>;
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ranges;
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display-engine@1000000 {
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bus@1000000 {
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compatible = "allwinner,sun50i-h6-de3",
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"allwinner,sun50i-a64-de2";
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reg = <0x1000000 0x400000>;
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@ -203,11 +203,32 @@
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#reset-cells = <1>;
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};
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dma: dma-controller@3002000 {
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compatible = "allwinner,sun50i-h6-dma";
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reg = <0x03002000 0x1000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
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clock-names = "bus", "mbus";
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dma-channels = <16>;
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dma-requests = <46>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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sid: sid@3006000 {
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compatible = "allwinner,sun50i-h6-sid";
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reg = <0x03006000 0x400>;
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};
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watchdog: watchdog@30090a0 {
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compatible = "allwinner,sun50i-h6-wdt",
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"allwinner,sun6i-a31-wdt";
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reg = <0x030090a0 0x20>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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/* Broken on some H6 boards */
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status = "disabled";
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x0300b000 0x400>;
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@ -243,6 +264,18 @@
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bias-pull-up;
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};
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/*
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* /omit-if-no-ref/ isn't supported by U-boot
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* keep this comment to avoid bad sync with Linux
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*/
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC4", "PC5", "PC6",
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"PC7", "PC8", "PC9", "PC10",
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@ -294,6 +327,8 @@
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -445,7 +480,6 @@
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resets = <&ccu RST_BUS_OHCI3>,
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<&ccu RST_BUS_EHCI3>;
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phys = <&usb2phy 3>;
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phy-names = "usb";
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status = "disabled";
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};
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@ -457,7 +491,6 @@
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<&ccu CLK_USB_OHCI3>;
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resets = <&ccu RST_BUS_OHCI3>;
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phys = <&usb2phy 3>;
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phy-names = "usb";
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status = "disabled";
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};
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@ -613,6 +646,13 @@
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#reset-cells = <1>;
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};
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r_watchdog: watchdog@7020400 {
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compatible = "allwinner,sun50i-h6-wdt",
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"allwinner,sun6i-a31-wdt";
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reg = <0x07020400 0x20>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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r_intc: interrupt-controller@7021000 {
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compatible = "allwinner,sun50i-h6-r-intc",
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"allwinner,sun6i-a31-r-intc";
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@ -315,6 +315,7 @@ struct dram_para {
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u8 cols;
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u8 rows;
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u8 ranks;
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u8 bus_full_width;
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const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
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const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
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};
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|
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@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
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struct sunxi_gpio_int gpio_int;
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};
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#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
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#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
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#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
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&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
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&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
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|
|
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@ -275,7 +275,10 @@ config MACH_SUN9I
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config MACH_SUN50I
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bool "sun50i (Allwinner A64)"
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select ARM64
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select SPI
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select DM_I2C
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select DM_SPI if SPI
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select DM_SPI_FLASH
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select PHY_SUN4I_USB
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select SUN6I_PRCM
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select SUNXI_DE2
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|
|
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@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
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static int gpio_init(void)
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{
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__maybe_unused uint val;
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#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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@ -139,6 +140,14 @@ static int gpio_init(void)
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#error Unsupported console port number. Please fix pin mux settings in board.c
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#endif
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#ifdef CONFIG_MACH_SUN50I_H6
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/* Update PIO power bias configuration by copy hardware detected value */
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val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
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writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
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val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
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writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
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#endif
|
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|
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return 0;
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}
|
||||
|
||||
|
|
|
@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
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if (clk > 1152000000) {
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k = 2;
|
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} else if (clk > 768000000) {
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k = 3;
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k = 4;
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m = 2;
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}
|
||||
|
||||
|
|
|
@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para)
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u8 rows = para->rows;
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u8 ranks = para->ranks;
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||||
|
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if (!para->bus_full_width)
|
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cols -= 1;
|
||||
|
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/* Ranks */
|
||||
if (ranks == 2)
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mctl_ctl->addrmap[0] = rows + cols - 3;
|
||||
|
@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para)
|
|||
/* Columns */
|
||||
mctl_ctl->addrmap[2] = 0;
|
||||
switch (cols) {
|
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case 7:
|
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mctl_ctl->addrmap[3] = 0x1F1F1F00;
|
||||
mctl_ctl->addrmap[4] = 0x1F1F;
|
||||
break;
|
||||
case 8:
|
||||
mctl_ctl->addrmap[3] = 0x1F1F0000;
|
||||
mctl_ctl->addrmap[4] = 0x1F1F;
|
||||
|
@ -300,13 +307,16 @@ static void mctl_com_init(struct dram_para *para)
|
|||
reg_val = 0x3f00;
|
||||
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
|
||||
|
||||
/* TODO: half DQ, DDR4 */
|
||||
reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
|
||||
MSTR_ACTIVE_RANKS(para->ranks);
|
||||
/* TODO: DDR4 */
|
||||
reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
|
||||
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
|
||||
reg_val |= MSTR_DEVICETYPE_LPDDR3;
|
||||
if (para->type == SUNXI_DRAM_TYPE_DDR3)
|
||||
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
|
||||
if (para->bus_full_width)
|
||||
reg_val |= MSTR_BUSWIDTH_FULL;
|
||||
else
|
||||
reg_val |= MSTR_BUSWIDTH_HALF;
|
||||
writel(reg_val | BIT(31), &mctl_ctl->mstr);
|
||||
|
||||
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
|
||||
|
@ -333,7 +343,10 @@ static void mctl_com_init(struct dram_para *para)
|
|||
}
|
||||
writel(reg_val, &mctl_ctl->odtcfg);
|
||||
|
||||
/* TODO: half DQ */
|
||||
if (!para->bus_full_width) {
|
||||
writel(0x0, &mctl_phy->dx[2].gcr[0]);
|
||||
writel(0x0, &mctl_phy->dx[3].gcr[0]);
|
||||
}
|
||||
}
|
||||
|
||||
static void mctl_bit_delay_set(struct dram_para *para)
|
||||
|
@ -514,22 +527,35 @@ static void mctl_channel_init(struct dram_para *para)
|
|||
|
||||
if (readl(&mctl_phy->pgsr[0]) & 0x400000)
|
||||
{
|
||||
/*
|
||||
* Detect single rank.
|
||||
* TODO: also detect half DQ.
|
||||
*/
|
||||
/* Check for single rank and optionally half DQ. */
|
||||
if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
|
||||
(readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
|
||||
(readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
|
||||
(readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
|
||||
(readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
|
||||
para->ranks = 1;
|
||||
|
||||
if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
|
||||
(readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
|
||||
para->bus_full_width = 0;
|
||||
|
||||
/* Restart DRAM initialization from scratch. */
|
||||
mctl_core_init(para);
|
||||
return;
|
||||
}
|
||||
else {
|
||||
panic("This DRAM setup is currently not supported.\n");
|
||||
|
||||
/*
|
||||
* Check for dual rank and half DQ. NOTE: This combination
|
||||
* is highly unlikely and was not tested. Condition is the
|
||||
* same as in libdram, though.
|
||||
*/
|
||||
if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
|
||||
(readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
|
||||
para->bus_full_width = 0;
|
||||
|
||||
/* Restart DRAM initialization from scratch. */
|
||||
mctl_core_init(para);
|
||||
return;
|
||||
}
|
||||
|
||||
panic("This DRAM setup is currently not supported.\n");
|
||||
}
|
||||
|
||||
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
|
||||
|
@ -557,11 +583,8 @@ static void mctl_channel_init(struct dram_para *para)
|
|||
|
||||
static void mctl_auto_detect_dram_size(struct dram_para *para)
|
||||
{
|
||||
/* TODO: non-LPDDR3, half DQ */
|
||||
/*
|
||||
* Detect rank number by the code in mctl_channel_init. Furtherly
|
||||
* when DQ detection is available it will also be executed there.
|
||||
*/
|
||||
/* TODO: non-(LP)DDR3 */
|
||||
/* Detect rank number and half DQ by the code in mctl_channel_init. */
|
||||
mctl_core_init(para);
|
||||
|
||||
/* detect row address bits */
|
||||
|
@ -570,8 +593,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
|
|||
mctl_core_init(para);
|
||||
|
||||
for (para->rows = 13; para->rows < 18; para->rows++) {
|
||||
/* 8 banks, 8 bit per byte and 32 bit width */
|
||||
if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
|
||||
/* 8 banks, 8 bit per byte and 16/32 bit width */
|
||||
if (mctl_mem_matches((1 << (para->rows + para->cols +
|
||||
4 + para->bus_full_width))))
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -580,18 +604,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
|
|||
mctl_core_init(para);
|
||||
|
||||
for (para->cols = 8; para->cols < 11; para->cols++) {
|
||||
/* 8 bits per byte and 32 bit width */
|
||||
if (mctl_mem_matches(1 << (para->cols + 2)))
|
||||
/* 8 bits per byte and 16/32 bit width */
|
||||
if (mctl_mem_matches(1 << (para->cols + 1 +
|
||||
para->bus_full_width)))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long mctl_calc_size(struct dram_para *para)
|
||||
{
|
||||
/* TODO: non-LPDDR3, half DQ */
|
||||
u8 width = para->bus_full_width ? 4 : 2;
|
||||
|
||||
/* 8 banks, 32-bit (4 byte) data width */
|
||||
return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
|
||||
/* TODO: non-(LP)DDR3 */
|
||||
|
||||
/* 8 banks */
|
||||
return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
|
||||
}
|
||||
|
||||
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
|
||||
|
@ -625,6 +652,7 @@ unsigned long sunxi_dram_init(void)
|
|||
.ranks = 2,
|
||||
.cols = 11,
|
||||
.rows = 14,
|
||||
.bus_full_width = 1,
|
||||
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
|
||||
.type = SUNXI_DRAM_TYPE_LPDDR3,
|
||||
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
|
||||
|
|
|
@ -106,6 +106,11 @@ M: Jagan Teki <jagan@amarulasolutions.com>
|
|||
S: Maintained
|
||||
F: configs/a64-olinuxino_defconfig
|
||||
|
||||
A64-OLINUXINO-EMMC BOARD
|
||||
M: Sunil Mohan Adapa <sunil@medhas.org>
|
||||
S: Maintained
|
||||
F: configs/a64-olinuxino-emmc_defconfig
|
||||
|
||||
A80 OPTIMUS BOARD
|
||||
M: Chen-Yu Tsai <wens@csie.org>
|
||||
S: Maintained
|
||||
|
|
|
@ -1168,6 +1168,7 @@ config CMD_SDRAM
|
|||
config CMD_SF
|
||||
bool "sf"
|
||||
depends on DM_SPI_FLASH || SPI_FLASH
|
||||
default y if DM_SPI_FLASH
|
||||
help
|
||||
SPI Flash support
|
||||
|
||||
|
|
17
configs/a64-olinuxino-emmc_defconfig
Normal file
17
configs/a64-olinuxino-emmc_defconfig
Normal file
|
@ -0,0 +1,17 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL=y
|
||||
CONFIG_MACH_SUN50I=y
|
||||
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc"
|
||||
CONFIG_SUN8I_EMAC=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
|
@ -44,6 +44,7 @@ CONFIG_SF_DEFAULT_CS=1
|
|||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -42,6 +42,7 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -43,6 +43,7 @@ CONFIG_SF_DEFAULT_BUS=3
|
|||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_SPANSION=y
|
|||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PMIC=y
|
||||
|
|
|
@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -46,6 +46,7 @@ CONFIG_SYS_I2C_DW=y
|
|||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
|
|
|
@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y
|
|||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -39,6 +39,7 @@ CONFIG_SYS_I2C_DW=y
|
|||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y
|
|||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -42,6 +42,7 @@ CONFIG_DM_I2C=y
|
|||
CONFIG_SYS_I2C_DW=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
|
|
|
@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -48,6 +48,7 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
|
|
|
@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SF_DEFAULT_SPEED=100000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
|
|
|
@ -72,6 +72,7 @@ CONFIG_SPI_FLASH=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
|
|
|
@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949
|
|||
CONFIG_MMC0_CD_PIN=""
|
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||
CONFIG_SPL_SPI_SUNXI=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
|
||||
|
|
|
@ -90,6 +90,7 @@ CONFIG_SPI_FLASH_STMICRO=y
|
|||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_SPL_SPI_FLASH_MTD=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_PHY=y
|
||||
|
|
|
@ -116,7 +116,7 @@ Put this code at the bottom of your existing driver file:
|
|||
static int exynos_cs_info(struct udevice *bus, uint cs,
|
||||
struct spi_cs_info *info)
|
||||
{
|
||||
return -ENODEV;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct dm_spi_ops exynos_spi_ops = {
|
||||
|
@ -633,9 +633,9 @@ is not obvious from outside the driver. In this case you can provide a
|
|||
method for cs_info() to deal with this. If you don't provide it, then the
|
||||
device tree will be used to determine what chip selects are valid.
|
||||
|
||||
Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid.
|
||||
If you don't provide the cs_info() method, -ENODEV is assumed for all
|
||||
chip selects that do not appear in the device tree.
|
||||
Return -EINVAL if the supplied chip select is invalid, or 0 if it is valid.
|
||||
If you don't provide the cs_info() method, 0 is assumed for all chip selects
|
||||
that do not appear in the device tree.
|
||||
|
||||
|
||||
Test it
|
||||
|
|
|
@ -3,6 +3,7 @@ menu "SPI Flash Support"
|
|||
config DM_SPI_FLASH
|
||||
bool "Enable Driver Model for SPI flash"
|
||||
depends on DM && DM_SPI
|
||||
imply SPI_FLASH
|
||||
help
|
||||
Enable driver model for SPI flash. This SPI flash interface
|
||||
(spi_flash_probe(), spi_flash_write(), etc.) is then
|
||||
|
@ -26,11 +27,10 @@ config SPI_FLASH_SANDBOX
|
|||
stored in a file on the host filesystem.
|
||||
|
||||
config SPI_FLASH
|
||||
bool "Legacy SPI Flash Interface support"
|
||||
depends on SPI
|
||||
bool "SPI Flash Core Interface support"
|
||||
select SPI_MEM
|
||||
help
|
||||
Enable the legacy SPI flash support. This will include basic
|
||||
Enable the SPI flash Core support. This will include basic
|
||||
standard support for things like probing, read / write, and
|
||||
erasing through cmd_sf interface.
|
||||
|
||||
|
@ -196,4 +196,12 @@ config SPI_FLASH_MTD
|
|||
|
||||
If unsure, say N
|
||||
|
||||
config SPL_SPI_FLASH_MTD
|
||||
bool "SPI flash MTD support for SPL"
|
||||
depends on SPI_FLASH
|
||||
help
|
||||
Enable the MTD support for the SPI flash layer in SPL.
|
||||
|
||||
If unsure, say N
|
||||
|
||||
endmenu # menu "SPI Flash Support"
|
||||
|
|
|
@ -19,5 +19,5 @@ endif
|
|||
|
||||
obj-$(CONFIG_SPI_FLASH) += spi-nor.o
|
||||
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
|
||||
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
|
||||
obj-$(CONFIG_$(SPL_)SPI_FLASH_MTD) += sf_mtd.o
|
||||
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
|
||||
|
|
|
@ -77,7 +77,7 @@ extern const struct flash_info spi_nor_ids[];
|
|||
int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
|
||||
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_MTD
|
||||
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
|
||||
int spi_flash_mtd_register(struct spi_flash *flash);
|
||||
void spi_flash_mtd_unregister(void);
|
||||
#endif
|
||||
|
|
|
@ -44,7 +44,7 @@ static int spi_flash_probe_slave(struct spi_flash *flash)
|
|||
if (ret)
|
||||
goto err_read_id;
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH_MTD
|
||||
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
|
||||
ret = spi_flash_mtd_register(flash);
|
||||
#endif
|
||||
|
||||
|
@ -83,7 +83,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
|
|||
|
||||
void spi_flash_free(struct spi_flash *flash)
|
||||
{
|
||||
#ifdef CONFIG_SPI_FLASH_MTD
|
||||
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
|
||||
spi_flash_mtd_unregister();
|
||||
#endif
|
||||
spi_free_slave(flash->spi);
|
||||
|
@ -152,7 +152,7 @@ static int spi_flash_std_probe(struct udevice *dev)
|
|||
|
||||
static int spi_flash_std_remove(struct udevice *dev)
|
||||
{
|
||||
#ifdef CONFIG_SPI_FLASH_MTD
|
||||
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
|
||||
spi_flash_mtd_unregister();
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
@ -380,12 +380,12 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
|
|||
|
||||
if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
|
||||
if (fsr & FSR_E_ERR)
|
||||
dev_dbg(nor->dev, "Erase operation failed.\n");
|
||||
dev_err(nor->dev, "Erase operation failed.\n");
|
||||
else
|
||||
dev_dbg(nor->dev, "Program operation failed.\n");
|
||||
dev_err(nor->dev, "Program operation failed.\n");
|
||||
|
||||
if (fsr & FSR_PT_ERR)
|
||||
dev_dbg(nor->dev,
|
||||
dev_err(nor->dev,
|
||||
"Attempted to modify a protected sector.\n");
|
||||
|
||||
nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
|
||||
|
@ -1916,7 +1916,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
|
|||
|
||||
erasesize = 1U << erasesize;
|
||||
opcode = (half >> 8) & 0xff;
|
||||
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
|
||||
#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
|
||||
if (erasesize == SZ_4K) {
|
||||
nor->erase_opcode = opcode;
|
||||
mtd->erasesize = erasesize;
|
||||
|
|
|
@ -58,7 +58,7 @@
|
|||
* All newly added entries should describe *hardware* and should use SECT_4K
|
||||
* (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
|
||||
* scenarios excluding small sectors there is config option that can be
|
||||
* disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
|
||||
* disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS.
|
||||
* For historical (and compatibility) reasons (before we got above config) some
|
||||
* old entries may be missing 4K flag.
|
||||
*/
|
||||
|
@ -75,6 +75,7 @@ const struct flash_info spi_nor_ids[] = {
|
|||
{ INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
|
||||
{ INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
|
||||
{ INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
|
||||
{ INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_FLASH_EON /* EON */
|
||||
|
@ -128,6 +129,8 @@ const struct flash_info spi_nor_ids[] = {
|
|||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
|
||||
/* Macronix */
|
||||
|
@ -161,12 +164,16 @@ const struct flash_info spi_nor_ids[] = {
|
|||
{ INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
|
||||
{ INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
|
||||
{ INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
|
||||
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
|
||||
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
|
||||
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
|
||||
USE_FSR) },
|
||||
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
||||
{ INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
|
||||
{ INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
||||
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
||||
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
||||
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
||||
|
|
|
@ -1,5 +1,22 @@
|
|||
menuconfig SPI
|
||||
bool "SPI Support"
|
||||
help
|
||||
The "Serial Peripheral Interface" is a low level synchronous
|
||||
protocol. Chips that support SPI can have data transfer rates
|
||||
up to several tens of Mbit/sec. Chips are addressed with a
|
||||
controller and a chipselect. Most SPI slaves don't support
|
||||
dynamic device discovery; some are even write-only or read-only.
|
||||
|
||||
SPI is widely used by microcontrollers to talk with sensors,
|
||||
eeprom and flash memory, codecs and various other controller
|
||||
chips, analog to digital (and d-to-a) converters, and more.
|
||||
MMC and SD cards can be accessed using SPI protocol; and for
|
||||
DataFlash cards used in MMC sockets, SPI must always be used.
|
||||
|
||||
SPI is one of a family of similar protocols using a four wire
|
||||
interface (select, clock, data in, data out) including Microwire
|
||||
(half duplex), SSP, SSI, and PSP. This driver framework should
|
||||
work with most such devices and controllers.
|
||||
|
||||
if SPI
|
||||
|
||||
|
@ -243,6 +260,7 @@ config SPI_SIFIVE
|
|||
|
||||
config SPI_SUNXI
|
||||
bool "Allwinner SoC SPI controllers"
|
||||
default ARCH_SUNXI
|
||||
help
|
||||
Enable the Allwinner SoC SPi controller driver.
|
||||
|
||||
|
|
|
@ -198,7 +198,7 @@ static int ath79_cs_info(struct udevice *bus, uint cs,
|
|||
{
|
||||
/* Always allow activity on CS 0/1/2 */
|
||||
if (cs >= 3)
|
||||
return -ENODEV;
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -108,7 +108,7 @@ static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
|
|||
|
||||
if (cs >= priv->num_cs) {
|
||||
printf("no cs %u\n", cs);
|
||||
return -ENODEV;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -130,7 +130,7 @@ static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
|
|||
|
||||
if (cs >= priv->num_cs) {
|
||||
printf("no cs %u\n", cs);
|
||||
return -ENODEV;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -518,8 +518,22 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode)
|
|||
static int dw_spi_remove(struct udevice *bus)
|
||||
{
|
||||
struct dw_spi_priv *priv = dev_get_priv(bus);
|
||||
int ret;
|
||||
|
||||
return reset_release_bulk(&priv->resets);
|
||||
ret = reset_release_bulk(&priv->resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
ret = clk_disable(&priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_free(&priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_spi_ops dw_spi_ops = {
|
||||
|
|
|
@ -117,7 +117,7 @@ static int sandbox_cs_info(struct udevice *bus, uint cs,
|
|||
{
|
||||
/* Always allow activity on CS 0 */
|
||||
if (cs >= 1)
|
||||
return -ENODEV;
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -261,11 +261,10 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
|
|||
return ops->cs_info(bus, cs, info);
|
||||
|
||||
/*
|
||||
* We could assume there is at least one valid chip select, but best
|
||||
* to be sure and return an error in this case. The driver didn't
|
||||
* care enough to tell us.
|
||||
* We could assume there is at least one valid chip select.
|
||||
* The driver didn't care enough to tell us.
|
||||
*/
|
||||
return -ENODEV;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
|
||||
|
|
|
@ -78,7 +78,7 @@ int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
|
|||
{
|
||||
/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
|
||||
if (cs != 0)
|
||||
return -ENODEV;
|
||||
return -EINVAL;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -30,7 +30,6 @@
|
|||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
|
||||
#define CONFIG_SPI_FLASH_MTD
|
||||
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
|
|
|
@ -38,13 +38,6 @@
|
|||
#define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/* SPI flash */
|
||||
|
||||
/* MTD support */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
|
|
|
@ -190,16 +190,11 @@
|
|||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH
|
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#if defined(CONFIG_USE_SPIFLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_SIZE (64 << 10)
|
||||
#define CONFIG_ENV_OFFSET (512 << 10)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 << 10)
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#undef CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* U-Boot general configuration
|
||||
|
|
|
@ -59,7 +59,6 @@
|
|||
#if defined(CONFIG_SPL_BUILD)
|
||||
#undef CONFIG_DM_SPI
|
||||
#undef CONFIG_DM_SPI_FLASH
|
||||
#undef CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
|
||||
/* UART */
|
||||
|
|
|
@ -39,7 +39,6 @@
|
|||
#if defined(CONFIG_SPL_BUILD)
|
||||
#undef CONFIG_DM_SPI
|
||||
#undef CONFIG_DM_SPI_FLASH
|
||||
#undef CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
|
||||
/* Below values are "dummy" - only to avoid build break */
|
||||
|
|
|
@ -47,15 +47,7 @@
|
|||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE
|
||||
|
||||
#ifdef CONFIG_SPI_FLASH
|
||||
|
||||
/* SPI */
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_MTD
|
||||
/* GPIO 3-19 (21248) */
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_SPL_NAND_SUPPORT)
|
||||
#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT)
|
||||
/* Enable NAND support */
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
|
|
@ -46,11 +46,9 @@
|
|||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
|
||||
|
||||
/* SF MTD */
|
||||
#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD)
|
||||
#else
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#undef CONFIG_DM_SPI
|
||||
#undef CONFIG_DM_SPI_FLASH
|
||||
#undef CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
|
||||
/* Timer */
|
||||
|
|
|
@ -132,10 +132,6 @@
|
|||
/*
|
||||
* QSPI support
|
||||
*/
|
||||
/* Enable multiple SPI NOR flash manufacturers */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
/* QSPI reference clock */
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned int cm_get_qspi_controller_clk_hz(void);
|
||||
|
|
|
@ -458,7 +458,7 @@ struct dm_spi_ops {
|
|||
* @cs: The chip select (0..n-1)
|
||||
* @info: Returns information about the chip select, if valid.
|
||||
* On entry info->dev is NULL
|
||||
* @return 0 if OK (and @info is set up), -ENODEV if the chip select
|
||||
* @return 0 if OK (and @info is set up), -EINVAL if the chip select
|
||||
* is invalid, other -ve value on error
|
||||
*/
|
||||
int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info);
|
||||
|
|
Loading…
Reference in a new issue