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ata: ahci: Don't forget to clear upper address regs.

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In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Oleksandr Rybalko <ray@ddteam.net>
This commit is contained in:
Oleksandr Rybalko 2019-08-22 12:26:56 +02:00 • committed by Tom Rini
parent 25643a5c3e
commit 5b7a2bf318
1 changed files with 7 additions and 4 deletions
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11
drivers/ata/ahci.c
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@ -548,6 +548,7 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
{
struct ahci_ioports *pp = &(uc_priv->port[port]);
void __iomem *port_mmio = pp->port_mmio;
u64 dma_addr;
u32 port_status;
void __iomem *mem;
@ -593,10 +594,12 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
writel_with_flush((unsigned long)pp->cmd_slot,
port_mmio + PORT_LST_ADDR);
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
dma_addr = (ulong)pp->cmd_slot;
writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
dma_addr = (ulong)pp->rx_fis;
writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
#ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);