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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

Browse source 
- spi cs accessing slaves (Bin Meng)
- spi prevent overriding established bus (Marcin Wojtas)
- support speed in spi command (Marek Vasut)
- add W25N01GV spinand (Robert Marko)
- move cadence_qspi to use spi-mem (Vignesh Raghavendra)
- add octal mode (Vignesh Raghavendra)
This commit is contained in:
Tom Rini 2020-01-27 19:57:13 -05:00
commit 86e42b3629
16 changed files with 1290 additions and 239 deletions
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14
cmd/spi.c
View file

@ -28,6 +28,7 @@
static unsigned int bus;
static unsigned int cs;
static unsigned int mode;
static unsigned int freq;
static int bitlen;
static uchar dout[MAX_SPI_BYTES];
static uchar din[MAX_SPI_BYTES];
@ -45,12 +46,12 @@ static int do_spi_xfer(int bus, int cs)
str = strdup(name);
if (!str)
return -ENOMEM;
ret = spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv",
ret = spi_get_bus_and_cs(bus, cs, freq, mode, "spi_generic_drv",
str, &dev, &slave);
if (ret)
return ret;
#else
slave = spi_setup_slave(bus, cs, 1000000, mode);
slave = spi_setup_slave(bus, cs, freq, mode);
if (!slave) {
printf("Invalid device %d:%d\n", bus, cs);
return -EINVAL;
@ -106,6 +107,8 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
* We use the last specified parameters, unless new ones are
* entered.
*/
if (freq == 0)
freq = 1000000;
if ((flag & CMD_FLAG_REPEAT) == 0)
{
@ -119,7 +122,9 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
bus = CONFIG_DEFAULT_SPI_BUS;
}
if (*cp == '.')
mode = simple_strtoul(cp+1, NULL, 10);
mode = simple_strtoul(cp+1, &cp, 10);
if (*cp == '@')
freq = simple_strtoul(cp+1, &cp, 10);
}
if (argc >= 3)
bitlen = simple_strtoul(argv[2], NULL, 10);
@ -159,10 +164,11 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
U_BOOT_CMD(
sspi, 5, 1, do_spi,
"SPI utility command",
"[<bus>:]<cs>[.<mode>] <bit_len> <dout> - Send and receive bits\n"
"[<bus>:]<cs>[.<mode>][@<freq>] <bit_len> <dout> - Send and receive bits\n"
"<bus> - Identifies the SPI bus\n"
"<cs> - Identifies the chip select\n"
"<mode> - Identifies the SPI mode to use\n"
"<freq> - Identifies the SPI bus frequency in Hz\n"
"<bit_len> - Number of bits to send (base 10)\n"
"<dout> - Hexadecimal string that gets sent"
);

8
drivers/mtd/nand/spi/winbond.c
View file

@ -86,6 +86,14 @@ static const struct spinand_info winbond_spinand_table[] = {
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
SPINAND_INFO("W25N01GV", 0xAA,
NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
};
/**

3
drivers/mtd/spi/sf_internal.h
View file

@ -37,7 +37,7 @@ struct flash_info {
u16 page_size;
u16 addr_width;
u16 flags;
u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
#define SST_WRITE BIT(2) /* use SST byte programming */
@ -66,6 +66,7 @@ struct flash_info {
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
};
extern const struct flash_info spi_nor_ids[];

20
drivers/mtd/spi/spi-nor-core.c
View file

@ -251,6 +251,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
{ SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
{ SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@ -267,6 +269,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
{ SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
{ SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@ -2169,6 +2173,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
if (info->flags & SPI_NOR_OCTAL_READ) {
params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
0, 8, SPINOR_OP_READ_1_1_8,
SNOR_PROTO_1_1_8);
}
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
@ -2476,7 +2487,14 @@ int spi_nor_scan(struct spi_nor *nor)
nor->read_reg = spi_nor_read_reg;
nor->write_reg = spi_nor_write_reg;
if (spi->mode & SPI_RX_QUAD) {
if (spi->mode & SPI_RX_OCTAL) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
if (spi->mode & SPI_TX_OCTAL)
hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
SNOR_HWCAPS_PP_1_1_8 |
SNOR_HWCAPS_PP_1_8_8);
} else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)

7
drivers/spi/Kconfig
View file

@ -192,6 +192,13 @@ config MVEBU_A3700_SPI
used to access the SPI NOR flash on platforms embedding this
Marvell IP core.
config NXP_FSPI
bool "NXP FlexSPI driver"
depends on SPI_MEM
help
Enable the NXP FlexSPI (FSPI) driver. This driver can be used to
access the SPI NOR flash on platforms embedding this NXP IP core.
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32

1
drivers/spi/Makefile
View file

@ -43,6 +43,7 @@ obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_PIC32_SPI) += pic32_spi.o

150
drivers/spi/cadence_qspi.c
View file

@ -6,18 +6,21 @@
#include <common.h>
#include <clk.h>
#include <asm-generic/io.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
#include <reset.h>
#include <spi.h>
#include <spi-mem.h>
#include <linux/errno.h>
#include <linux/sizes.h>
#include "cadence_qspi.h"
#define CQSPI_STIG_READ 0
#define CQSPI_STIG_WRITE 1
#define CQSPI_INDIRECT_READ 2
#define CQSPI_INDIRECT_WRITE 3
#define CQSPI_READ 2
#define CQSPI_WRITE 3
static int cadence_spi_write_speed(struct udevice *bus, uint hz)
{
@ -35,12 +38,21 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
return 0;
}
static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
{
struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(len, idcode, 1));
return cadence_qspi_apb_command_read(reg_base, &op);
}
/* Calibration sequence to determine the read data capture delay register */
static int spi_calibration(struct udevice *bus, uint hz)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
u8 opcode_rdid = 0x9F;
unsigned int idcode = 0, temp = 0;
int err = 0, i, range_lo = -1, range_hi = -1;
@ -54,8 +66,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
cadence_qspi_apb_controller_enable(base);
/* read the ID which will be our golden value */
err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
3, (u8 *)&idcode);
err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
if (err) {
puts("SF: Calibration failed (read)\n");
return err;
@ -74,8 +85,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
cadence_qspi_apb_controller_enable(base);
/* issue a RDID to get the ID value */
err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
3, (u8 *)&temp);
err = cadence_spi_read_id(base, 3, (u8 *)&temp);
if (err) {
puts("SF: Calibration failed (read)\n");
return err;
@ -182,6 +192,7 @@ static int cadence_spi_remove(struct udevice *dev)
static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
/* Disable QSPI */
@ -190,102 +201,62 @@ static int cadence_spi_set_mode(struct udevice *bus, uint mode)
/* Set SPI mode */
cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
/* Enable Direct Access Controller */
if (plat->use_dac_mode)
cadence_qspi_apb_dac_mode_enable(priv->regbase);
/* Enable QSPI */
cadence_qspi_apb_controller_enable(priv->regbase);
return 0;
}
static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
static int cadence_spi_mem_exec_op(struct spi_slave *spi,
const struct spi_mem_op *op)
{
struct udevice *bus = dev->parent;
struct udevice *bus = spi->dev->parent;
struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
void *base = priv->regbase;
u8 *cmd_buf = priv->cmd_buf;
size_t data_bytes;
int err = 0;
u32 mode = CQSPI_STIG_WRITE;
if (flags & SPI_XFER_BEGIN) {
/* copy command to local buffer */
priv->cmd_len = bitlen / 8;
memcpy(cmd_buf, dout, priv->cmd_len);
}
if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
/* if start and end bit are set, the data bytes is 0. */
data_bytes = 0;
} else {
data_bytes = bitlen / 8;
}
debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
u32 mode;
/* Set Chip select */
cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
plat->is_decoded_cs);
if ((flags & SPI_XFER_END) || (flags == 0)) {
if (priv->cmd_len == 0) {
printf("QSPI: Error, command is empty.\n");
return -1;
}
if (din && data_bytes) {
/* read */
/* Use STIG if no address. */
if (!CQSPI_IS_ADDR(priv->cmd_len))
mode = CQSPI_STIG_READ;
else
mode = CQSPI_INDIRECT_READ;
} else if (dout && !(flags & SPI_XFER_BEGIN)) {
/* write */
if (!CQSPI_IS_ADDR(priv->cmd_len))
mode = CQSPI_STIG_WRITE;
else
mode = CQSPI_INDIRECT_WRITE;
}
switch (mode) {
case CQSPI_STIG_READ:
err = cadence_qspi_apb_command_read(
base, priv->cmd_len, cmd_buf,
data_bytes, din);
if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
if (!op->addr.nbytes)
mode = CQSPI_STIG_READ;
else
mode = CQSPI_READ;
} else {
if (!op->addr.nbytes || !op->data.buf.out)
mode = CQSPI_STIG_WRITE;
else
mode = CQSPI_WRITE;
}
switch (mode) {
case CQSPI_STIG_READ:
err = cadence_qspi_apb_command_read(base, op);
break;
case CQSPI_STIG_WRITE:
err = cadence_qspi_apb_command_write(base,
priv->cmd_len, cmd_buf,
data_bytes, dout);
case CQSPI_STIG_WRITE:
err = cadence_qspi_apb_command_write(base, op);
break;
case CQSPI_INDIRECT_READ:
err = cadence_qspi_apb_indirect_read_setup(plat,
priv->cmd_len, dm_plat->mode, cmd_buf);
if (!err) {
err = cadence_qspi_apb_indirect_read_execute
(plat, data_bytes, din);
}
case CQSPI_READ:
err = cadence_qspi_apb_read_setup(plat, op);
if (!err)
err = cadence_qspi_apb_read_execute(plat, op);
break;
case CQSPI_INDIRECT_WRITE:
err = cadence_qspi_apb_indirect_write_setup
(plat, priv->cmd_len, dm_plat->mode, cmd_buf);
if (!err) {
err = cadence_qspi_apb_indirect_write_execute
(plat, data_bytes, dout);
}
case CQSPI_WRITE:
err = cadence_qspi_apb_write_setup(plat, op);
if (!err)
err = cadence_qspi_apb_write_execute(plat, op);
break;
default:
err = -1;
break;
default:
err = -1;
break;
}
if (flags & SPI_XFER_END) {
/* clear command buffer */
memset(cmd_buf, 0, sizeof(priv->cmd_buf));
priv->cmd_len = 0;
}
}
return err;
@ -299,13 +270,17 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
int ret;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
&plat->ahbsize);
plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
plat->trigger_address = dev_read_u32_default(bus,
"cdns,trigger-address",
0);
/* Use DAC mode only when MMIO window is at least 8M wide */
if (plat->ahbsize >= SZ_8M)
plat->use_dac_mode = true;
/* All other paramters are embedded in the child node */
subnode = dev_read_first_subnode(bus);
@ -349,10 +324,14 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
return 0;
}
static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
.exec_op = cadence_spi_mem_exec_op,
};
static const struct dm_spi_ops cadence_spi_ops = {
.xfer = cadence_spi_xfer,
.set_speed = cadence_spi_set_speed,
.set_mode = cadence_spi_set_mode,
.mem_ops = &cadence_spi_mem_ops,
/*
* cs_info is not needed, since we require all chip selects to be
* in the device tree explicitly
@ -361,6 +340,7 @@ static const struct dm_spi_ops cadence_spi_ops = {
static const struct udevice_id cadence_spi_ids[] = {
{ .compatible = "cdns,qspi-nor" },
{ .compatible = "ti,am654-ospi" },
{ }
};

24
drivers/spi/cadence_qspi.h
View file

@ -24,6 +24,8 @@ struct cadence_spi_platdata {
u32 fifo_depth;
u32 fifo_width;
u32 trigger_address;
fdt_addr_t ahbsize;
bool use_dac_mode;
/* Flash parameters */
u32 page_size;
@ -53,21 +55,21 @@ struct cadence_spi_priv {
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
void cadence_qspi_apb_dac_mode_enable(void *reg_base);
int cadence_qspi_apb_command_read(void *reg_base_addr,
unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
const struct spi_mem_op *op);
int cadence_qspi_apb_command_write(void *reg_base_addr,
unsigned int cmdlen, const u8 *cmdbuf,
unsigned int txlen, const u8 *txbuf);
const struct spi_mem_op *op);
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
unsigned int rxlen, u8 *rxbuf);
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
unsigned int txlen, const u8 *txbuf);
int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op);
int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op);
int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op);
int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op);
void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable);

189
drivers/spi/cadence_qspi_apb.c
View file

@ -27,9 +27,11 @@
#include <common.h>
#include <asm/io.h>
#include <dma.h>
#include <linux/errno.h>
#include <wait_bit.h>
#include <spi.h>
#include <spi-mem.h>
#include <malloc.h>
#include "cadence_qspi.h"
@ -41,6 +43,7 @@
#define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_INST_TYPE_QUAD 2
#define CQSPI_INST_TYPE_OCTAL 3
#define CQSPI_STIG_DATA_LEN_MAX 8
@ -172,19 +175,6 @@
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
unsigned int addr_width)
{
unsigned int addr;
addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
if (addr_width == 4)
addr = (addr << 8) | addr_buf[3];
return addr;
}
void cadence_qspi_apb_controller_enable(void *reg_base)
{
unsigned int reg;
@ -201,6 +191,15 @@ void cadence_qspi_apb_controller_disable(void *reg_base)
writel(reg, reg_base + CQSPI_REG_CONFIG);
}
void cadence_qspi_apb_dac_mode_enable(void *reg_base)
{
unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_DIRECT;
writel(reg, reg_base + CQSPI_REG_CONFIG);
}
/* Return 1 if idle, otherwise return 0 (busy). */
static unsigned int cadence_qspi_wait_idle(void *reg_base)
{
@ -433,21 +432,20 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
}
/* For command RDID, RDSR. */
int cadence_qspi_apb_command_read(void *reg_base,
unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
u8 *rxbuf)
int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
{
unsigned int reg;
unsigned int read_len;
int status;
unsigned int rxlen = op->data.nbytes;
void *rxbuf = op->data.buf.in;
if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
cmdlen, rxlen);
if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
return -EINVAL;
}
reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
@ -475,34 +473,30 @@ int cadence_qspi_apb_command_read(void *reg_base,
}
/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
{
unsigned int reg = 0;
unsigned int addr_value;
unsigned int wr_data;
unsigned int wr_len;
unsigned int txlen = op->data.nbytes;
const void *txbuf = op->data.buf.out;
u32 addr;
if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
cmdlen, txlen);
/* Reorder address to SPI bus order if only transferring address */
if (!txlen) {
addr = cpu_to_be32(op->addr.val);
if (op->addr.nbytes == 3)
addr >>= 8;
txbuf = &addr;
txlen = op->addr.nbytes;
}
if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
printf("QSPI: Invalid input arguments txlen %u\n", txlen);
return -EINVAL;
}
reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
if (cmdlen == 4 || cmdlen == 5) {
/* Command with address */
reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
/* Number of bytes to write. */
reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
/* Get address */
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
cmdlen >= 5 ? 4 : 3);
writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
}
reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
if (txlen) {
/* writing data = yes */
@ -529,62 +523,36 @@ int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
}
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
unsigned int rd_reg;
unsigned int addr_value;
unsigned int dummy_clk;
unsigned int dummy_bytes;
unsigned int addr_bytes;
/*
* Identify addr_byte. All NOR flash device drivers are using fast read
* which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
* With that, the length is in value of 5 or 6. Only FRAM chip from
* ramtron using normal read (which won't need dummy byte).
* Unlikely NOR flash using normal read due to performance issue.
*/
if (cmdlen >= 5)
/* to cater fast read where cmd + addr + dummy */
addr_bytes = cmdlen - 2;
else
/* for normal read (only ramtron as of now) */
addr_bytes = cmdlen - 1;
unsigned int dummy_bytes = op->dummy.nbytes;
/* Setup the indirect trigger address */
writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
if (rx_width & SPI_RX_QUAD)
if (op->data.buswidth == 8)
/* Instruction and address at DQ0, data at DQ0-7. */
rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
else if (op->data.buswidth == 4)
/* Instruction and address at DQ0, data at DQ0-3. */
rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
/* Get address */
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
/* The remaining lenght is dummy bytes. */
dummy_bytes = cmdlen - addr_bytes - 1;
if (dummy_bytes) {
if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
#else
writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
#endif
/* Convert to clock cycles. */
dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
/* Need to minus the mode byte (8 clocks). */
dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
if (dummy_clk)
rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
@ -596,7 +564,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
/* set device size */
reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
reg |= (addr_bytes - 1);
reg |= (op->addr.nbytes - 1);
writel(reg, plat->regbase + CQSPI_REG_SIZE);
return 0;
}
@ -623,8 +591,9 @@ static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
return -ETIMEDOUT;
}
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
unsigned int n_rx, u8 *rxbuf)
static int
cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
unsigned int n_rx, u8 *rxbuf)
{
unsigned int remaining = n_rx;
unsigned int bytes_to_read = 0;
@ -685,43 +654,52 @@ failrd:
return ret;
}
int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op)
{
u64 from = op->addr.val;
void *buf = op->data.buf.in;
size_t len = op->data.nbytes;
if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
if (len < 256 ||
dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
memcpy_fromio(buf, plat->ahbbase + from, len);
}
if (!cadence_qspi_wait_idle(plat->regbase))
return -EIO;
return 0;
}
return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
}
/* Opcode + Address (3/4 bytes) */
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
if (cmdlen < 4 || cmdbuf == NULL) {
printf("QSPI: Invalid input argument, len %d cmdbuf %p\n",
cmdlen, cmdbuf);
return -EINVAL;
}
/* Setup the indirect trigger address */
writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
if (tx_width & SPI_TX_QUAD)
reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
/* Setup write address. */
reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
reg |= (addr_bytes - 1);
reg |= (op->addr.nbytes - 1);
writel(reg, plat->regbase + CQSPI_REG_SIZE);
return 0;
}
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
unsigned int n_tx, const u8 *txbuf)
static int
cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
unsigned int n_tx, const u8 *txbuf)
{
unsigned int page_size = plat->page_size;
unsigned int remaining = n_tx;
@ -793,6 +771,23 @@ failwr:
return ret;
}
int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
const struct spi_mem_op *op)
{
u32 to = op->addr.val;
const void *buf = op->data.buf.out;
size_t len = op->data.nbytes;
if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
memcpy_toio(plat->ahbbase + to, buf, len);
if (!cadence_qspi_wait_idle(plat->regbase))
return -EIO;
return 0;
}
return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
}
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
{
unsigned int reg;

996
drivers/spi/nxp_fspi.c Normal file
View file

@ -0,0 +1,996 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* NXP FlexSPI(FSPI) controller driver.
*
* Copyright (c) 2019 Michael Walle <michael@walle.cc>
* Copyright (c) 2019 NXP
*
* This driver was originally ported from the linux kernel v5.4-rc3, which had
* the following notes:
*
* FlexSPI is a flexsible SPI host controller which supports two SPI
* channels and up to 4 external devices. Each channel supports
* Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
* data lines).
*
* FlexSPI controller is driven by the LUT(Look-up Table) registers
* LUT registers are a look-up-table for sequences of instructions.
* A valid sequence consists of four LUT registers.
* Maximum 32 LUT sequences can be programmed simultaneously.
*
* LUTs are being created at run-time based on the commands passed
* from the spi-mem framework, thus using single LUT index.
*
* Software triggered Flash read/write access by IP Bus.
*
* Memory mapped read access by AHB Bus.
*
* Based on SPI MEM interface and spi-fsl-qspi.c driver.
*
* Author:
* Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
* Boris Brezillon <bbrezillon@kernel.org>
* Frieder Schrempf <frieder.schrempf@kontron.de>
*/
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <spi.h>
#include <spi-mem.h>
#include <dm.h>
#include <clk.h>
#include <linux/kernel.h>
#include <linux/sizes.h>
#include <linux/iopoll.h>
#include <linux/bug.h>
/*
* The driver only uses one single LUT entry, that is updated on
* each call of exec_op(). Index 0 is preset at boot with a basic
* read operation, so let's use the last entry (31).
*/
#define SEQID_LUT 31
/* Registers used by the driver */
#define FSPI_MCR0 0x00
#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
#define FSPI_MCR0_LEARN_EN BIT(15)
#define FSPI_MCR0_SCRFRUN_EN BIT(14)
#define FSPI_MCR0_OCTCOMB_EN BIT(13)
#define FSPI_MCR0_DOZE_EN BIT(12)
#define FSPI_MCR0_HSEN BIT(11)
#define FSPI_MCR0_SERCLKDIV BIT(8)
#define FSPI_MCR0_ATDF_EN BIT(7)
#define FSPI_MCR0_ARDF_EN BIT(6)
#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
#define FSPI_MCR0_END_CFG(x) ((x) << 2)
#define FSPI_MCR0_MDIS BIT(1)
#define FSPI_MCR0_SWRST BIT(0)
#define FSPI_MCR1 0x04
#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
#define FSPI_MCR2 0x08
#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
#define FSPI_MCR2_CLRLRPHS BIT(14)
#define FSPI_MCR2_ABRDATSZ BIT(8)
#define FSPI_MCR2_ABRLEARN BIT(7)
#define FSPI_MCR2_ABR_READ BIT(6)
#define FSPI_MCR2_ABRWRITE BIT(5)
#define FSPI_MCR2_ABRDUMMY BIT(4)
#define FSPI_MCR2_ABR_MODE BIT(3)
#define FSPI_MCR2_ABRCADDR BIT(2)
#define FSPI_MCR2_ABRRADDR BIT(1)
#define FSPI_MCR2_ABR_CMD BIT(0)
#define FSPI_AHBCR 0x0c
#define FSPI_AHBCR_RDADDROPT BIT(6)
#define FSPI_AHBCR_PREF_EN BIT(5)
#define FSPI_AHBCR_BUFF_EN BIT(4)
#define FSPI_AHBCR_CACH_EN BIT(3)
#define FSPI_AHBCR_CLRTXBUF BIT(2)
#define FSPI_AHBCR_CLRRXBUF BIT(1)
#define FSPI_AHBCR_PAR_EN BIT(0)
#define FSPI_INTEN 0x10
#define FSPI_INTEN_SCLKSBWR BIT(9)
#define FSPI_INTEN_SCLKSBRD BIT(8)
#define FSPI_INTEN_DATALRNFL BIT(7)
#define FSPI_INTEN_IPTXWE BIT(6)
#define FSPI_INTEN_IPRXWA BIT(5)
#define FSPI_INTEN_AHBCMDERR BIT(4)
#define FSPI_INTEN_IPCMDERR BIT(3)
#define FSPI_INTEN_AHBCMDGE BIT(2)
#define FSPI_INTEN_IPCMDGE BIT(1)
#define FSPI_INTEN_IPCMDDONE BIT(0)
#define FSPI_INTR 0x14
#define FSPI_INTR_SCLKSBWR BIT(9)
#define FSPI_INTR_SCLKSBRD BIT(8)
#define FSPI_INTR_DATALRNFL BIT(7)
#define FSPI_INTR_IPTXWE BIT(6)
#define FSPI_INTR_IPRXWA BIT(5)
#define FSPI_INTR_AHBCMDERR BIT(4)
#define FSPI_INTR_IPCMDERR BIT(3)
#define FSPI_INTR_AHBCMDGE BIT(2)
#define FSPI_INTR_IPCMDGE BIT(1)
#define FSPI_INTR_IPCMDDONE BIT(0)
#define FSPI_LUTKEY 0x18
#define FSPI_LUTKEY_VALUE 0x5AF05AF0
#define FSPI_LCKCR 0x1C
#define FSPI_LCKER_LOCK 0x1
#define FSPI_LCKER_UNLOCK 0x2
#define FSPI_BUFXCR_INVALID_MSTRID 0xE
#define FSPI_AHBRX_BUF0CR0 0x20
#define FSPI_AHBRX_BUF1CR0 0x24
#define FSPI_AHBRX_BUF2CR0 0x28
#define FSPI_AHBRX_BUF3CR0 0x2C
#define FSPI_AHBRX_BUF4CR0 0x30
#define FSPI_AHBRX_BUF5CR0 0x34
#define FSPI_AHBRX_BUF6CR0 0x38
#define FSPI_AHBRX_BUF7CR0 0x3C
#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
#define FSPI_AHBRX_BUF0CR1 0x40
#define FSPI_AHBRX_BUF1CR1 0x44
#define FSPI_AHBRX_BUF2CR1 0x48
#define FSPI_AHBRX_BUF3CR1 0x4C
#define FSPI_AHBRX_BUF4CR1 0x50
#define FSPI_AHBRX_BUF5CR1 0x54
#define FSPI_AHBRX_BUF6CR1 0x58
#define FSPI_AHBRX_BUF7CR1 0x5C
#define FSPI_FLSHA1CR0 0x60
#define FSPI_FLSHA2CR0 0x64
#define FSPI_FLSHB1CR0 0x68
#define FSPI_FLSHB2CR0 0x6C
#define FSPI_FLSHXCR0_SZ_KB 10
#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
#define FSPI_FLSHA1CR1 0x70
#define FSPI_FLSHA2CR1 0x74
#define FSPI_FLSHB1CR1 0x78
#define FSPI_FLSHB2CR1 0x7C
#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
#define FSPI_FLSHXCR1_WA BIT(10)
#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
#define FSPI_FLSHXCR1_TCSS(x) (x)
#define FSPI_FLSHA1CR2 0x80
#define FSPI_FLSHA2CR2 0x84
#define FSPI_FLSHB1CR2 0x88
#define FSPI_FLSHB2CR2 0x8C
#define FSPI_FLSHXCR2_CLRINSP BIT(24)
#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
#define FSPI_IPCR0 0xA0
#define FSPI_IPCR1 0xA4
#define FSPI_IPCR1_IPAREN BIT(31)
#define FSPI_IPCR1_SEQNUM_SHIFT 24
#define FSPI_IPCR1_SEQID_SHIFT 16
#define FSPI_IPCR1_IDATSZ(x) (x)
#define FSPI_IPCMD 0xB0
#define FSPI_IPCMD_TRG BIT(0)
#define FSPI_DLPR 0xB4
#define FSPI_IPRXFCR 0xB8
#define FSPI_IPRXFCR_CLR BIT(0)
#define FSPI_IPRXFCR_DMA_EN BIT(1)
#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
#define FSPI_IPTXFCR 0xBC
#define FSPI_IPTXFCR_CLR BIT(0)
#define FSPI_IPTXFCR_DMA_EN BIT(1)
#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
#define FSPI_DLLACR 0xC0
#define FSPI_DLLACR_OVRDEN BIT(8)
#define FSPI_DLLBCR 0xC4
#define FSPI_DLLBCR_OVRDEN BIT(8)
#define FSPI_STS0 0xE0
#define FSPI_STS0_DLPHB(x) ((x) << 8)
#define FSPI_STS0_DLPHA(x) ((x) << 4)
#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
#define FSPI_STS0_ARB_IDLE BIT(1)
#define FSPI_STS0_SEQ_IDLE BIT(0)
#define FSPI_STS1 0xE4
#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
#define FSPI_STS1_AHB_ERRID(x) (x)
#define FSPI_AHBSPNST 0xEC
#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
#define FSPI_AHBSPNST_ACTIVE BIT(0)
#define FSPI_IPRXFSTS 0xF0
#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
#define FSPI_IPRXFSTS_FILL(x) (x)
#define FSPI_IPTXFSTS 0xF4
#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
#define FSPI_IPTXFSTS_FILL(x) (x)
#define FSPI_RFDR 0x100
#define FSPI_TFDR 0x180
#define FSPI_LUT_BASE 0x200
#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
#define FSPI_LUT_REG(idx) \
(FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
/* register map end */
/* Instruction set for the LUT register. */
#define LUT_STOP 0x00
#define LUT_CMD 0x01
#define LUT_ADDR 0x02
#define LUT_CADDR_SDR 0x03
#define LUT_MODE 0x04
#define LUT_MODE2 0x05
#define LUT_MODE4 0x06
#define LUT_MODE8 0x07
#define LUT_NXP_WRITE 0x08
#define LUT_NXP_READ 0x09
#define LUT_LEARN_SDR 0x0A
#define LUT_DATSZ_SDR 0x0B
#define LUT_DUMMY 0x0C
#define LUT_DUMMY_RWDS_SDR 0x0D
#define LUT_JMP_ON_CS 0x1F
#define LUT_CMD_DDR 0x21
#define LUT_ADDR_DDR 0x22
#define LUT_CADDR_DDR 0x23
#define LUT_MODE_DDR 0x24
#define LUT_MODE2_DDR 0x25
#define LUT_MODE4_DDR 0x26
#define LUT_MODE8_DDR 0x27
#define LUT_WRITE_DDR 0x28
#define LUT_READ_DDR 0x29
#define LUT_LEARN_DDR 0x2A
#define LUT_DATSZ_DDR 0x2B
#define LUT_DUMMY_DDR 0x2C
#define LUT_DUMMY_RWDS_DDR 0x2D
/*
* Calculate number of required PAD bits for LUT register.
*
* The pad stands for the number of IO lines [0:7].
* For example, the octal read needs eight IO lines,
* so you should use LUT_PAD(8). This macro
* returns 3 i.e. use eight (2^3) IP lines for read.
*/
#define LUT_PAD(x) (fls(x) - 1)
/*
* Macro for constructing the LUT entries with the following
* register layout:
*
* ---------------------------------------------------
* | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
* ---------------------------------------------------
*/
#define PAD_SHIFT 8
#define INSTR_SHIFT 10
#define OPRND_SHIFT 16
/* Macros for constructing the LUT register. */
#define LUT_DEF(idx, ins, pad, opr) \
((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
(opr)) << (((idx) % 2) * OPRND_SHIFT))
#define POLL_TOUT 5000
#define NXP_FSPI_MAX_CHIPSELECT 4
struct nxp_fspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
unsigned int ahb_buf_size;
unsigned int quirks;
bool little_endian;
};
static const struct nxp_fspi_devtype_data lx2160a_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
.quirks = 0,
.little_endian = true, /* little-endian */
};
struct nxp_fspi {
struct udevice *dev;
void __iomem *iobase;
void __iomem *ahb_addr;
u32 memmap_phy;
u32 memmap_phy_size;
struct clk clk, clk_en;
const struct nxp_fspi_devtype_data *devtype_data;
};
/*
* R/W functions for big- or little-endian registers:
* The FSPI controller's endianness is independent of
* the CPU core's endianness. So far, although the CPU
* core is little-endian the FSPI controller can use
* big-endian or little-endian.
*/
static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
{
if (f->devtype_data->little_endian)
out_le32(addr, val);
else
out_be32(addr, val);
}
static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
{
if (f->devtype_data->little_endian)
return in_le32(addr);
else
return in_be32(addr);
}
static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
{
switch (width) {
case 1:
case 2:
case 4:
case 8:
return 0;
}
return -ENOTSUPP;
}
static bool nxp_fspi_supports_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
struct nxp_fspi *f;
struct udevice *bus;
int ret;
bus = slave->dev->parent;
f = dev_get_priv(bus);
ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
if (op->addr.nbytes)
ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
if (op->dummy.nbytes)
ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
if (op->data.nbytes)
ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
if (ret)
return false;
/*
* The number of address bytes should be equal to or less than 4 bytes.
*/
if (op->addr.nbytes > 4)
return false;
/*
* If requested address value is greater than controller assigned
* memory mapped space, return error as it didn't fit in the range
* of assigned address space.
*/
if (op->addr.val >= f->memmap_phy_size)
return false;
/* Max 64 dummy clock cycles supported */
if (op->dummy.buswidth &&
(op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
return false;
/* Max data length, check controller limits and alignment */
if (op->data.dir == SPI_MEM_DATA_IN &&
(op->data.nbytes > f->devtype_data->ahb_buf_size ||
(op->data.nbytes > f->devtype_data->rxfifo - 4 &&
!IS_ALIGNED(op->data.nbytes, 8))))
return false;
if (op->data.dir == SPI_MEM_DATA_OUT &&
op->data.nbytes > f->devtype_data->txfifo)
return false;
return true;
}
/* Instead of busy looping invoke readl_poll_timeout functionality. */
static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
u32 mask, u32 delay_us,
u32 timeout_us, bool c)
{
u32 reg;
if (!f->devtype_data->little_endian)
mask = (u32)cpu_to_be32(mask);
if (c)
return readl_poll_timeout(base, reg, (reg & mask),
timeout_us);
else
return readl_poll_timeout(base, reg, !(reg & mask),
timeout_us);
}
/*
* If the slave device content being changed by Write/Erase, need to
* invalidate the AHB buffer. This can be achieved by doing the reset
* of controller after setting MCR0[SWRESET] bit.
*/
static inline void nxp_fspi_invalid(struct nxp_fspi *f)
{
u32 reg;
int ret;
reg = fspi_readl(f, f->iobase + FSPI_MCR0);
fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
/* w1c register, wait unit clear */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
WARN_ON(ret);
}
static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
const struct spi_mem_op *op)
{
void __iomem *base = f->iobase;
u32 lutval[4] = {};
int lutidx = 1, i;
/* cmd */
lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
op->cmd.opcode);
/* addr bytes */
if (op->addr.nbytes) {
lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
LUT_PAD(op->addr.buswidth),
op->addr.nbytes * 8);
lutidx++;
}
/* dummy bytes, if needed */
if (op->dummy.nbytes) {
lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
/*
* Due to FlexSPI controller limitation number of PAD for dummy
* buswidth needs to be programmed as equal to data buswidth.
*/
LUT_PAD(op->data.buswidth),
op->dummy.nbytes * 8 /
op->dummy.buswidth);
lutidx++;
}
/* read/write data bytes */
if (op->data.nbytes) {
lutval[lutidx / 2] |= LUT_DEF(lutidx,
op->data.dir == SPI_MEM_DATA_IN ?
LUT_NXP_READ : LUT_NXP_WRITE,
LUT_PAD(op->data.buswidth),
0);
lutidx++;
}
/* stop condition. */
lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
/* unlock LUT */
fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
/* fill LUT */
for (i = 0; i < ARRAY_SIZE(lutval); i++)
fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
/* lock LUT */
fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
}
#if CONFIG_IS_ENABLED(CONFIG_CLK)
static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
{
int ret;
ret = clk_enable(&f->clk_en);
if (ret)
return ret;
ret = clk_enable(&f->clk);
if (ret) {
clk_disable(&f->clk_en);
return ret;
}
return 0;
}
static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
{
clk_disable(&f->clk);
clk_disable(&f->clk_en);
}
#endif
/*
* In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
* register and start base address of the slave device.
*
* (Higher address)
* -------- <-- FLSHB2CR0
* | B2 |
* | |
* B2 start address --> -------- <-- FLSHB1CR0
* | B1 |
* | |
* B1 start address --> -------- <-- FLSHA2CR0
* | A2 |
* | |
* A2 start address --> -------- <-- FLSHA1CR0
* | A1 |
* | |
* A1 start address --> -------- (Lower address)
*
*
* Start base address defines the starting address range for given CS and
* FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
*
* But, different targets are having different combinations of number of CS,
* some targets only have single CS or two CS covering controller's full
* memory mapped space area.
* Thus, implementation is being done as independent of the size and number
* of the connected slave device.
* Assign controller memory mapped space size as the size to the connected
* slave device.
* Mark FLSHxxCR0 as zero initially and then assign value only to the selected
* chip-select Flash configuration register.
*
* For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
* memory mapped size of the controller.
* Value for rest of the CS FLSHxxCR0 register would be zero.
*
*/
static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
{
u64 size_kb;
/* Reset FLSHxxCR0 registers */
fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
/* Assign controller memory mapped space as size, KBytes, of flash. */
size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
4 * chip_select);
dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
}
static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
{
u32 len = op->data.nbytes;
/* Read out the data directly from the AHB buffer. */
memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
}
static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
const struct spi_mem_op *op)
{
void __iomem *base = f->iobase;
int i, ret;
u8 *buf = (u8 *)op->data.buf.out;
/* clear the TX FIFO. */
fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
/*
* Default value of water mark level is 8 bytes, hence in single
* write request controller can write max 8 bytes of data.
*/
for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
/* Wait for TXFIFO empty */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
FSPI_INTR_IPTXWE, 0,
POLL_TOUT, true);
WARN_ON(ret);
fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
}
if (i < op->data.nbytes) {
u32 data = 0;
int j;
/* Wait for TXFIFO empty */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
FSPI_INTR_IPTXWE, 0,
POLL_TOUT, true);
WARN_ON(ret);
for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
memcpy(&data, buf + i + j, 4);
fspi_writel(f, data, base + FSPI_TFDR + j);
}
fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
}
}
static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
const struct spi_mem_op *op)
{
void __iomem *base = f->iobase;
int i, ret;
int len = op->data.nbytes;
u8 *buf = (u8 *)op->data.buf.in;
/*
* Default value of water mark level is 8 bytes, hence in single
* read request controller can read max 8 bytes of data.
*/
for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
/* Wait for RXFIFO available */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
FSPI_INTR_IPRXWA, 0,
POLL_TOUT, true);
WARN_ON(ret);
*(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
*(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
/* move the FIFO pointer */
fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
}
if (i < len) {
u32 tmp;
int size, j;
buf = op->data.buf.in + i;
/* Wait for RXFIFO available */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
FSPI_INTR_IPRXWA, 0,
POLL_TOUT, true);
WARN_ON(ret);
len = op->data.nbytes - i;
for (j = 0; j < op->data.nbytes - i; j += 4) {
tmp = fspi_readl(f, base + FSPI_RFDR + j);
size = min(len, 4);
memcpy(buf + j, &tmp, size);
len -= size;
}
}
/* invalid the RXFIFO */
fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
/* move the FIFO pointer */
fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
}
static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
{
void __iomem *base = f->iobase;
int seqnum = 0;
int err = 0;
u32 reg;
reg = fspi_readl(f, base + FSPI_IPRXFCR);
/* invalid RXFIFO first */
reg &= ~FSPI_IPRXFCR_DMA_EN;
reg = reg | FSPI_IPRXFCR_CLR;
fspi_writel(f, reg, base + FSPI_IPRXFCR);
fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
/*
* Always start the sequence at the same index since we update
* the LUT at each exec_op() call. And also specify the DATA
* length, since it's has not been specified in the LUT.
*/
fspi_writel(f, op->data.nbytes |
(SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
(seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
base + FSPI_IPCR1);
/* Trigger the LUT now. */
fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
/* Wait for the completion. */
err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
/* Invoke IP data read, if request is of data read. */
if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
nxp_fspi_read_rxfifo(f, op);
return err;
}
static int nxp_fspi_exec_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
struct nxp_fspi *f;
struct udevice *bus;
int err = 0;
bus = slave->dev->parent;
f = dev_get_priv(bus);
/* Wait for controller being ready. */
err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
WARN_ON(err);
nxp_fspi_prepare_lut(f, op);
/*
* If we have large chunks of data, we read them through the AHB bus
* by accessing the mapped memory. In all other cases we use
* IP commands to access the flash.
*/
if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
op->data.dir == SPI_MEM_DATA_IN) {
nxp_fspi_read_ahb(f, op);
} else {
if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
nxp_fspi_fill_txfifo(f, op);
err = nxp_fspi_do_op(f, op);
}
/* Invalidate the data in the AHB buffer. */
nxp_fspi_invalid(f);
return err;
}
static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
struct spi_mem_op *op)
{
struct nxp_fspi *f;
struct udevice *bus;
bus = slave->dev->parent;
f = dev_get_priv(bus);
if (op->data.dir == SPI_MEM_DATA_OUT) {
if (op->data.nbytes > f->devtype_data->txfifo)
op->data.nbytes = f->devtype_data->txfifo;
} else {
if (op->data.nbytes > f->devtype_data->ahb_buf_size)
op->data.nbytes = f->devtype_data->ahb_buf_size;
else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
}
return 0;
}
static int nxp_fspi_default_setup(struct nxp_fspi *f)
{
void __iomem *base = f->iobase;
int ret, i;
u32 reg;
#if CONFIG_IS_ENABLED(CONFIG_CLK)
/* disable and unprepare clock to avoid glitch pass to controller */
nxp_fspi_clk_disable_unprep(f);
/* the default frequency, we will change it later if necessary. */
ret = clk_set_rate(&f->clk, 20000000);
if (ret)
return ret;
ret = nxp_fspi_clk_prep_enable(f);
if (ret)
return ret;
#endif
/* Reset the module */
/* w1c register, wait unit clear */
ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
WARN_ON(ret);
/* Disable the module */
fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
/* Reset the DLL register to default value */
fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
/* enable module */
fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
base + FSPI_MCR0);
/*
* Disable same device enable bit and configure all slave devices
* independently.
*/
reg = fspi_readl(f, f->iobase + FSPI_MCR2);
reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
fspi_writel(f, reg, base + FSPI_MCR2);
/* AHB configuration for access buffer 0~7. */
for (i = 0; i < 7; i++)
fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
/*
* Set ADATSZ with the maximum AHB buffer size to improve the read
* performance.
*/
fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
/* prefetch and no start address alignment limitation */
fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
base + FSPI_AHBCR);
/* AHB Read - Set lut sequence ID for all CS. */
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
return 0;
}
static int nxp_fspi_probe(struct udevice *bus)
{
struct nxp_fspi *f = dev_get_priv(bus);
f->devtype_data =
(struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
nxp_fspi_default_setup(f);
return 0;
}
static int nxp_fspi_claim_bus(struct udevice *dev)
{
struct nxp_fspi *f;
struct udevice *bus;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
bus = dev->parent;
f = dev_get_priv(bus);
nxp_fspi_select_mem(f, slave_plat->cs);
return 0;
}
static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
{
#if CONFIG_IS_ENABLED(CONFIG_CLK)
struct nxp_fspi *f = dev_get_priv(bus);
int ret;
nxp_fspi_clk_disable_unprep(f);
ret = clk_set_rate(&f->clk, speed);
if (ret)
return ret;
ret = nxp_fspi_clk_prep_enable(f);
if (ret)
return ret;
#endif
return 0;
}
static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
{
/* Nothing to do */
return 0;
}
static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
{
struct nxp_fspi *f = dev_get_priv(bus);
#if CONFIG_IS_ENABLED(CONFIG_CLK)
int ret;
#endif
fdt_addr_t iobase;
fdt_addr_t iobase_size;
fdt_addr_t ahb_addr;
fdt_addr_t ahb_size;
f->dev = bus;
iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
if (iobase == FDT_ADDR_T_NONE) {
dev_err(bus, "fspi_base regs missing\n");
return -ENODEV;
}
f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
if (ahb_addr == FDT_ADDR_T_NONE) {
dev_err(bus, "fspi_mmap regs missing\n");
return -ENODEV;
}
f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
f->memmap_phy_size = ahb_size;
#if CONFIG_IS_ENABLED(CONFIG_CLK)
ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
if (ret) {
dev_err(bus, "failed to get fspi_en clock\n");
return ret;
}
ret = clk_get_by_name(bus, "fspi", &f->clk);
if (ret) {
dev_err(bus, "failed to get fspi clock\n");
return ret;
}
#endif
dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
return 0;
}
static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
.adjust_op_size = nxp_fspi_adjust_op_size,
.supports_op = nxp_fspi_supports_op,
.exec_op = nxp_fspi_exec_op,
};
static const struct dm_spi_ops nxp_fspi_ops = {
.claim_bus = nxp_fspi_claim_bus,
.set_speed = nxp_fspi_set_speed,
.set_mode = nxp_fspi_set_mode,
.mem_ops = &nxp_fspi_mem_ops,
};
static const struct udevice_id nxp_fspi_ids[] = {
{ .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
{ }
};
U_BOOT_DRIVER(nxp_fspi) = {
.name = "nxp_fspi",
.id = UCLASS_SPI,
.of_match = nxp_fspi_ids,
.ops = &nxp_fspi_ops,
.ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct nxp_fspi),
.probe = nxp_fspi_probe,
};

6
drivers/spi/spi-mem.c
View file

@ -123,6 +123,12 @@ static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx)
return 0;
break;
case 8:
if ((tx && (mode & SPI_TX_OCTAL)) ||
(!tx && (mode & SPI_RX_OCTAL)))
return 0;
break;
default:
break;

71
drivers/spi/spi-uclass.c
View file

@ -224,7 +224,32 @@ int spi_chip_select(struct udevice *dev)
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
{
struct dm_spi_ops *ops;
struct spi_cs_info info;
struct udevice *dev;
int ret;
/*
* Ask the driver. For the moment we don't have CS info.
* When we do we could provide the driver with a helper function
* to figure out what chip selects are valid, or just handle the
* request.
*/
ops = spi_get_ops(bus);
if (ops->cs_info) {
ret = ops->cs_info(bus, cs, &info);
} else {
/*
* We could assume there is at least one valid chip select.
* The driver didn't care enough to tell us.
*/
ret = 0;
}
if (ret) {
printf("Invalid cs %d (err=%d)\n", cs, ret);
return ret;
}
for (device_find_first_child(bus, &dev); dev;
device_find_next_child(&dev)) {
@ -259,7 +284,6 @@ int spi_cs_is_valid(unsigned int busnum, unsigned int cs)
int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
{
struct spi_cs_info local_info;
struct dm_spi_ops *ops;
int ret;
if (!info)
@ -268,24 +292,7 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
/* If there is a device attached, return it */
info->dev = NULL;
ret = spi_find_chip_select(bus, cs, &info->dev);
if (!ret)
return 0;
/*
* Otherwise ask the driver. For the moment we don't have CS info.
* When we do we could provide the driver with a helper function
* to figure out what chip selects are valid, or just handle the
* request.
*/
ops = spi_get_ops(bus);
if (ops->cs_info)
return ops->cs_info(bus, cs, info);
/*
* We could assume there is at least one valid chip select.
* The driver didn't care enough to tell us.
*/
return 0;
return ret == -ENODEV ? 0 : ret;
}
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
@ -316,6 +323,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
{
struct udevice *bus, *dev;
struct dm_spi_slave_platdata *plat;
struct spi_slave *slave;
bool created = false;
int ret;
@ -371,19 +379,20 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
slave->dev = dev;
}
plat = dev_get_parent_platdata(dev);
slave = dev_get_parent_priv(dev);
/* get speed and mode from platdata when available */
if (plat->max_hz) {
speed = plat->max_hz;
mode = plat->mode;
/*
* In case the operation speed is not yet established by
* dm_spi_claim_bus() ensure the bus is configured properly.
*/
if (!slave->speed) {
ret = spi_claim_bus(slave);
if (ret)
goto err;
}
ret = spi_set_speed_mode(bus, speed, mode);
if (ret)
goto err;
*busp = bus;
*devp = dev_get_parent_priv(dev);
*devp = slave;
debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp);
return 0;
@ -452,6 +461,9 @@ int spi_slave_ofdata_to_platdata(struct udevice *dev,
case 4:
mode |= SPI_TX_QUAD;
break;
case 8:
mode |= SPI_TX_OCTAL;
break;
default:
warn_non_spl("spi-tx-bus-width %d not supported\n", value);
break;
@ -467,6 +479,9 @@ int spi_slave_ofdata_to_platdata(struct udevice *dev,
case 4:
mode |= SPI_RX_QUAD;
break;
case 8:
mode |= SPI_RX_OCTAL;
break;
default:
warn_non_spl("spi-rx-bus-width %d not supported\n", value);
break;

21
drivers/spi/ti_qspi.c
View file

@ -60,6 +60,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_SETUP0_ADDR_SHIFT (8)
#define QSPI_SETUP0_DBITS_SHIFT (10)
#define TI_QSPI_SETUP_REG(priv, cs) (&(priv)->base->setup0 + (cs))
/* ti qspi register set */
struct ti_qspi_regs {
u32 pid;
@ -275,8 +277,8 @@ static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
*((unsigned int *)offset) += len;
}
static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
u8 data_nbits, u8 addr_width,
static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
u8 opcode, u8 data_nbits, u8 addr_width,
u8 dummy_bytes)
{
u32 memval = opcode;
@ -296,7 +298,7 @@ static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
writel(memval, &priv->base->setup0);
writel(memval, TI_QSPI_SETUP_REG(priv, cs));
}
static int ti_qspi_set_mode(struct udevice *bus, uint mode)
@ -317,13 +319,15 @@ static int ti_qspi_set_mode(struct udevice *bus, uint mode)
static int ti_qspi_exec_mem_op(struct spi_slave *slave,
const struct spi_mem_op *op)
{
struct dm_spi_slave_platdata *slave_plat;
struct ti_qspi_priv *priv;
struct udevice *bus;
u32 from = 0;
int ret = 0;
bus = slave->dev->parent;
priv = dev_get_priv(bus);
u32 from = 0;
int ret = 0;
slave_plat = dev_get_parent_platdata(slave->dev);
/* Only optimize read path. */
if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
@ -335,8 +339,9 @@ static int ti_qspi_exec_mem_op(struct spi_slave *slave,
if (from + op->data.nbytes > priv->mmap_size)
return -ENOTSUPP;
ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
op->addr.nbytes, op->dummy.nbytes);
ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
op->data.buswidth, op->addr.nbytes,
op->dummy.nbytes);
ti_qspi_copy_mmap((void *)op->data.buf.in,
(void *)priv->memory_map + from, op->data.nbytes);
@ -390,7 +395,7 @@ static int ti_qspi_release_bus(struct udevice *dev)
writel(0, &priv->base->dc);
writel(0, &priv->base->cmd);
writel(0, &priv->base->data);
writel(0, &priv->base->setup0);
writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
return 0;
}

8
include/linux/mtd/spi-nor.h
View file

@ -47,9 +47,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
@ -70,9 +74,13 @@
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */

5
include/spi.h
View file

@ -30,6 +30,8 @@
#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */
#define SPI_RX_DUAL BIT(12) /* receive with 2 wires */
#define SPI_RX_QUAD BIT(13) /* receive with 4 wires */
#define SPI_TX_OCTAL BIT(14) /* transmit with 8 wires */
#define SPI_RX_OCTAL BIT(15) /* receive with 8 wires */
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
@ -561,7 +563,8 @@ int spi_chip_select(struct udevice *slave);
* @bus: SPI bus to search
* @cs: Chip select to look for
* @devp: Returns the slave device if found
* @return 0 if found, -ENODEV on error
* @return 0 if found, -EINVAL if cs is invalid, -ENODEV if no device attached,
* other -ve value on error
*/
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);

6
test/dm/spi.c
View file

@ -77,10 +77,10 @@ static int dm_test_spi_find(struct unit_test_state *uts)
/* We should be able to add something to another chip select */
ut_assertok(sandbox_sf_bind_emul(state, busnum, cs_b, bus, node,
"name"));
ut_assertok(spi_get_bus_and_cs(busnum, cs_b, speed, mode,
ut_asserteq(-EINVAL, spi_get_bus_and_cs(busnum, cs_b, speed, mode,
"spi_flash_std", "name", &bus, &slave));
ut_assertok(spi_cs_info(bus, cs_b, &info));
ut_asserteq_ptr(info.dev, slave->dev);
ut_asserteq(-EINVAL, spi_cs_info(bus, cs_b, &info));
ut_asserteq_ptr(NULL, info.dev);
/*
* Since we are about to destroy all devices, we must tell sandbox