mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Fixes for 2020.04
----------------- - DM : mx6sabresd - mx6ul_14x14_evk: fix video - mx8qxp; fix console for booting - sync DTS with kernel (imx6sx) - drop obsolete woodburn (mx35) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/660550811 -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCXme08A8cc2JhYmljQGRl bnguZGUACgkQ9PVl5Jpo76b41QCdFJlz/cPf27UtVZo5OXrZ9ADd/ecAnileL1GL zyFoQYCs8dE4DpusOnML =llSt -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20200310' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.04 ----------------- - DM : mx6sabresd - mx6ul_14x14_evk: fix video - mx8qxp; fix console for booting - sync DTS with kernel (imx6sx) - drop obsolete woodburn (mx35) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/660550811
This commit is contained in:
Tom Rini
commit
3a1cb95308
46 changed files with 602 additions and 1204 deletions
|
|
@ -598,15 +598,6 @@ config TARGET_X600
|
|||
select PL011_SERIAL
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_WOODBURN
|
||||
bool "Support woodburn"
|
||||
select CPU_ARM1136
|
||||
|
||||
config TARGET_WOODBURN_SD
|
||||
bool "Support woodburn_sd"
|
||||
select CPU_ARM1136
|
||||
select SUPPORT_SPL
|
||||
|
||||
config TARGET_FLEA3
|
||||
bool "Support flea3"
|
||||
select CPU_ARM1136
|
||||
|
|
@ -1880,7 +1871,6 @@ source "board/birdland/bav335x/Kconfig"
|
|||
source "board/toradex/colibri_pxa270/Kconfig"
|
||||
source "board/variscite/dart_6ul/Kconfig"
|
||||
source "board/vscom/baltos/Kconfig"
|
||||
source "board/woodburn/Kconfig"
|
||||
source "board/xilinx/Kconfig"
|
||||
source "board/xilinx/zynq/Kconfig"
|
||||
source "board/xilinx/zynqmp/Kconfig"
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX6SX_PINFUNC_H
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
&qspi2 {
|
||||
num-cs = <2>;
|
||||
|
||||
flash0: n25q256a@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
};
|
||||
|
||||
flash1: n25q256a@1 {
|
||||
compatible = "jedec,spi-nor";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
//
|
||||
// Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
|
||||
#include "imx6sx-sdb.dtsi"
|
||||
|
||||
|
|
@ -117,15 +113,19 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
flash1: n25q256a@1 {
|
||||
flash1: n25q256a@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
reg = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -136,3 +136,20 @@
|
|||
®_soc {
|
||||
vin-supply = <&sw1a_reg>;
|
||||
};
|
||||
|
||||
®_vdd1p1 {
|
||||
vin-supply = <&vgen6_reg>;
|
||||
};
|
||||
|
||||
®_vdd2p5 {
|
||||
vin-supply = <&vgen6_reg>;
|
||||
};
|
||||
|
||||
®_can_stby {
|
||||
/* Transceiver EN/STBY is active low on RevB board */
|
||||
gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
//
|
||||
// Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
|
|
@ -20,11 +16,12 @@
|
|||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
backlight_display: backlight-display {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
|
|
@ -40,95 +37,118 @@
|
|||
label = "Volume Up";
|
||||
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
vcc_sd3: regulator-vcc-sd3 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_vcc_sd3>;
|
||||
regulator-name = "VCC_SD3";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vcc_sd3: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_vcc_sd3>;
|
||||
regulator-name = "VCC_SD3";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1>;
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1>;
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg2>;
|
||||
regulator-name = "usb_otg2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_otg2_vbus: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg2>;
|
||||
regulator-name = "usb_otg2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
reg_psu_5v: regulator-psu-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "PSU-5V0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_psu_5v: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "PSU-5V0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
reg_lcd_3v3: regulator-lcd-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd-3v3";
|
||||
gpio = <&gpio3 27 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_lcd_3v3: regulator@4 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "lcd-3v3";
|
||||
gpio = <&gpio3 27 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
reg_peri_3v3: regulator-peri-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_peri_3v3>;
|
||||
regulator-name = "peri_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_peri_3v3: regulator@5 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_peri_3v3>;
|
||||
regulator-name = "peri_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
reg_enet_3v3: regulator-enet-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_3v3>;
|
||||
regulator-name = "enet_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_enet_3v3: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <6>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_3v3>;
|
||||
regulator-name = "enet_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
reg_pcie_gpio: regulator-pcie-gpio {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie_reg>;
|
||||
regulator-name = "MPCIE_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_lcd_5v: regulator-lcd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd-5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_can_en: regulator-can-en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "can-en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_can_stby: regulator-can-stby {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "can-stby";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
|
|
@ -146,6 +166,19 @@
|
|||
mux-int-port = <2>;
|
||||
mux-ext-port = <6>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "sii,43wvf1g";
|
||||
backlight = <&backlight_display>;
|
||||
dvdd-supply = <®_lcd_3v3>;
|
||||
avdd-supply = <®_lcd_5v>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
|
|
@ -158,8 +191,9 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-supply = <®_enet_3v3>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
|
|
@ -184,6 +218,20 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
xceiver-supply = <®_can_stby>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcan2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_can_stby>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -212,34 +260,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie>;
|
||||
reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
vpcie-supply = <®_pcie_gpio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd>;
|
||||
lcd-supply = <®_lcd_3v3>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display0 {
|
||||
bits-per-pixel = <16>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <33500000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hback-porch = <89>;
|
||||
hfront-porch = <164>;
|
||||
vback-porch = <23>;
|
||||
vfront-porch = <10>;
|
||||
hsync-len = <10>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
port {
|
||||
display_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -365,6 +401,8 @@
|
|||
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
|
||||
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
|
||||
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
|
||||
/* phy reset */
|
||||
MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -391,6 +429,20 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
|
||||
MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
|
||||
MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpio_keysgrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
|
||||
|
|
@ -453,6 +505,18 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie: pciegrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie_reg: pciereggrp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_peri_3v3: peri3v3grp {
|
||||
fsl,pins = <
|
||||
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -31,7 +31,7 @@
|
|||
u-boot,dm-pre-reloc;
|
||||
|
||||
display0: display@0 {
|
||||
bits-per-pixel = <16>;
|
||||
bits-per-pixel = <24>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
|
|
|
|||
|
|
@ -69,6 +69,10 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc1 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&pinctrl_usdhc2 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -153,8 +153,6 @@
|
|||
|
||||
&fec1 {
|
||||
fsl,magic-packet;
|
||||
fsl,rgmii_rxc_dly;
|
||||
fsl,rgmii_txc_dly;
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <®_ethphy>;
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@
|
|||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <10>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
obj-y += cpu.o iomux.o misc.o lowlevel_init.o
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||
obj-$(CONFIG_AHAB_BOOT) += ahab.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o
|
||||
|
|
|
|||
|
|
@ -477,6 +477,11 @@ static struct clk_root_map root_array[] = {
|
|||
};
|
||||
#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
|
||||
static struct clk_root_map root_array[] = {
|
||||
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
|
||||
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
|
|
|
|||
|
|
@ -30,6 +30,9 @@
|
|||
#include <miiphy.h>
|
||||
#include <lcd.h>
|
||||
#include <led.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/regulator.h>
|
||||
#include <power/da9063_pmic.h>
|
||||
#include <splash.h>
|
||||
#include <video_fb.h>
|
||||
|
||||
|
|
@ -438,6 +441,56 @@ static void aristainetos_bootmode_settings(void)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DM_PMIC_DA9063)
|
||||
/*
|
||||
* On the aristainetos2c boards the PMIC needs to be initialized,
|
||||
* because the Ethernet PHY uses a different regulator that is not
|
||||
* setup per hardware default. This does not influence the other versions
|
||||
* as this regulator isn't used there at all.
|
||||
*
|
||||
* Unfortunately we have not yet a interface to setup all
|
||||
* values we need.
|
||||
*/
|
||||
static int setup_pmic_voltages(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int off;
|
||||
int ret;
|
||||
|
||||
off = fdt_path_offset(gd->fdt_blob, "pmic0");
|
||||
if (off < 0) {
|
||||
printf("%s: No pmic path offset\n", __func__);
|
||||
return off;
|
||||
}
|
||||
|
||||
ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Could not find PMIC\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
|
||||
pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
|
||||
ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
|
||||
if (ret < 0) {
|
||||
printf("%s: error %d get register\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
ret &= 0xf0;
|
||||
ret |= 0x09;
|
||||
pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
|
||||
pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
|
||||
pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int setup_pmic_voltages(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
int x, y;
|
||||
|
|
@ -457,6 +510,9 @@ int board_late_init(void)
|
|||
else
|
||||
env_set("board_type", ARI_BT_7);
|
||||
|
||||
if (setup_pmic_voltages())
|
||||
printf("Error setup PMIC\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -64,29 +64,11 @@ int dram_init(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
|
||||
static iomux_v3_cfg_t const fec1_rst_pads[] = {
|
||||
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
|
||||
ARRAY_SIZE(fec1_rst_pads));
|
||||
|
||||
gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
setup_iomux_fec();
|
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
|
||||
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
|
||||
return set_clk_enet(ENET_125MHZ);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
i.MX8QXP MEK BOARD
|
||||
M: Peng Fan <peng.fan@nxp.com>
|
||||
M: Fabio Estevam <festevam@gmail.com>
|
||||
S: Maintained
|
||||
F: board/freescale/imx8qxp_mek/
|
||||
F: include/configs/imx8qxp_mek.h
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#include <mmc.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
#include <input.h>
|
||||
|
|
@ -76,23 +75,6 @@ static iomux_v3_cfg_t const uart4_pads[] = {
|
|||
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const enet_pads[] = {
|
||||
IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
};
|
||||
|
||||
/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
|
||||
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
|
||||
|
|
@ -259,10 +241,6 @@ static void setup_iomux_eimnor(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(enet_pads);
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
|
|
@ -340,26 +318,6 @@ static void setup_gpmi_nand(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static void setup_fec(void)
|
||||
{
|
||||
if (is_mx6dqp()) {
|
||||
/*
|
||||
* select ENET MAC0 TX clock from PLL
|
||||
*/
|
||||
imx_iomux_set_gpr_register(5, 9, 1, 1);
|
||||
enable_fec_anatop_clock(0, ENET_125MHZ);
|
||||
}
|
||||
|
||||
setup_iomux_enet();
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_fec();
|
||||
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
int rev = nxp_board_rev();
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
#include <mmc.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/mxc_hdmi.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/io.h>
|
||||
|
|
@ -44,9 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
|
|
@ -73,31 +69,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
|
|||
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const enet_pads[] = {
|
||||
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
/* AR8031 PHY Reset */
|
||||
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(enet_pads);
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
|
|
@ -495,13 +466,6 @@ int overwrite_console(void)
|
|||
return 1;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_iomux_enet();
|
||||
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
static void setup_usb(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
#include <fsl_esdhc_imx.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <netdev.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze100_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
|
|
@ -102,35 +101,11 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
|
|||
};
|
||||
#endif
|
||||
|
||||
static iomux_v3_cfg_t const fec_pads[] = {
|
||||
MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
|
||||
/* Power up LAN8720 PHY */
|
||||
gpio_request(ETH_PHY_POWER, "eth_pwr");
|
||||
gpio_direction_output(ETH_PHY_POWER , 1);
|
||||
udelay(15000);
|
||||
}
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
|
|
@ -179,12 +154,6 @@ int power_init_board(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_iomux_fec();
|
||||
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
MX7DSABRESD BOARD
|
||||
M: Adrian Alonso <adrian.alonso@nxp.com>
|
||||
M: Fabio Estevam <festevam@gmail.com>
|
||||
S: Maintained
|
||||
F: board/freescale/mx7dsabresd
|
||||
F: include/configs/mx7dsabresd.h
|
||||
|
|
|
|||
|
|
@ -1,25 +0,0 @@
|
|||
if TARGET_WOODBURN
|
||||
|
||||
config SYS_BOARD
|
||||
default "woodburn"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx35"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "woodburn"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_WOODBURN_SD
|
||||
|
||||
config SYS_BOARD
|
||||
default "woodburn"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx35"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "woodburn_sd"
|
||||
|
||||
endif
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
WOODBURN BOARD
|
||||
M: Stefano Babic <sbabic@denx.de>
|
||||
S: Maintained
|
||||
F: board/woodburn/
|
||||
F: include/configs/woodburn.h
|
||||
F: configs/woodburn_defconfig
|
||||
|
||||
WOODBURN_SD BOARD
|
||||
#M: -
|
||||
S: Maintained
|
||||
F: include/configs/woodburn_sd.h
|
||||
F: configs/woodburn_sd_defconfig
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y := woodburn.o
|
||||
obj-y += lowlevel_init.o
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
BOOT_FROM sd
|
||||
|
||||
/* DDR2 init */
|
||||
DATA 4 0xB8001010 0x00000304
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/lowlevel_macro.S>
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
core_init
|
||||
|
||||
init_aips
|
||||
|
||||
init_max
|
||||
|
||||
init_m3if
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -1,251 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* Based on flea3.c and mx35pdk.c
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux-mx35.h>
|
||||
#include <i2c.h>
|
||||
#include <power/pmic.h>
|
||||
#include <fsl_pmic.h>
|
||||
#include <mc13892.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <netdev.h>
|
||||
#include <spl.h>
|
||||
|
||||
#define CCM_CCMR_CONFIG 0x003F4208
|
||||
|
||||
#define ESDCTL_DDR2_CONFIG 0x007FFC3F
|
||||
|
||||
/* For MMC */
|
||||
#define GPIO_MMC_CD 7
|
||||
#define GPIO_MMC_WP 8
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void board_setup_sdram(void)
|
||||
{
|
||||
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
|
||||
|
||||
/* Initialize with default values both CSD0/1 */
|
||||
writel(0x2000, &esdc->esdctl0);
|
||||
writel(0x2000, &esdc->esdctl1);
|
||||
|
||||
mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
|
||||
13, 10, 2, 0x8080);
|
||||
}
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t fec_pads[] = {
|
||||
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
|
||||
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
|
||||
MX35_PAD_FEC_RX_DV__FEC_RX_DV,
|
||||
MX35_PAD_FEC_COL__FEC_COL,
|
||||
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
|
||||
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
|
||||
MX35_PAD_FEC_TX_EN__FEC_TX_EN,
|
||||
MX35_PAD_FEC_MDC__FEC_MDC,
|
||||
MX35_PAD_FEC_MDIO__FEC_MDIO,
|
||||
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
|
||||
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
|
||||
MX35_PAD_FEC_CRS__FEC_CRS,
|
||||
MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
|
||||
MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
|
||||
MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
|
||||
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
|
||||
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
|
||||
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
|
||||
};
|
||||
|
||||
/* setup pins for FEC */
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
int woodburn_init(void)
|
||||
{
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
|
||||
/* initialize PLL and clock configuration */
|
||||
writel(CCM_CCMR_CONFIG, &ccm->ccmr);
|
||||
|
||||
/* Set-up RAM */
|
||||
board_setup_sdram();
|
||||
|
||||
/* enable clocks */
|
||||
writel(readl(&ccm->cgr0) |
|
||||
MXC_CCM_CGR0_EMI_MASK |
|
||||
MXC_CCM_CGR0_EDIO_MASK |
|
||||
MXC_CCM_CGR0_EPIT1_MASK,
|
||||
&ccm->cgr0);
|
||||
|
||||
writel(readl(&ccm->cgr1) |
|
||||
MXC_CCM_CGR1_FEC_MASK |
|
||||
MXC_CCM_CGR1_GPIO1_MASK |
|
||||
MXC_CCM_CGR1_GPIO2_MASK |
|
||||
MXC_CCM_CGR1_GPIO3_MASK |
|
||||
MXC_CCM_CGR1_I2C1_MASK |
|
||||
MXC_CCM_CGR1_I2C2_MASK |
|
||||
MXC_CCM_CGR1_I2C3_MASK,
|
||||
&ccm->cgr1);
|
||||
|
||||
/* Set-up NAND */
|
||||
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
|
||||
|
||||
/* Set pinmux for the required peripherals */
|
||||
setup_iomux_fec();
|
||||
|
||||
/* setup GPIO1_4 FEC_ENABLE signal */
|
||||
imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
|
||||
gpio_direction_output(4, 1);
|
||||
imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
|
||||
gpio_direction_output(9, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Set the stack pointer. */
|
||||
asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
|
||||
|
||||
/* Initialize MUX and SDRAM */
|
||||
woodburn_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
preloader_console_init();
|
||||
timer_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Booting from NOR in external mode */
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return woodburn_init();
|
||||
}
|
||||
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
ret = pmic_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
p = pmic_get("FSL_PMIC");
|
||||
|
||||
/*
|
||||
* Set switchers in Auto in NORMAL mode & STANDBY mode
|
||||
* Setup the switcher mode for SW1 & SW2
|
||||
*/
|
||||
pmic_reg_read(p, REG_SW_4, &val);
|
||||
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
|
||||
(SWMODE_MASK << SWMODE2_SHIFT)));
|
||||
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
|
||||
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
|
||||
/* Set SWILIMB */
|
||||
val |= (1 << 22);
|
||||
pmic_reg_write(p, REG_SW_4, val);
|
||||
|
||||
/* Setup the switcher mode for SW3 & SW4 */
|
||||
pmic_reg_read(p, REG_SW_5, &val);
|
||||
val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
|
||||
(SWMODE_MASK << SWMODE3_SHIFT));
|
||||
val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
|
||||
(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
|
||||
pmic_reg_write(p, REG_SW_5, val);
|
||||
|
||||
/* Set VGEN1 to 3.15V */
|
||||
pmic_reg_read(p, REG_SETTING_0, &val);
|
||||
val &= ~(VGEN1_MASK);
|
||||
val |= VGEN1_3_15;
|
||||
pmic_reg_write(p, REG_SETTING_0, val);
|
||||
|
||||
pmic_reg_read(p, REG_MODE_0, &val);
|
||||
val |= VGEN1EN;
|
||||
pmic_reg_write(p, REG_MODE_0, val);
|
||||
udelay(2000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FSL_ESDHC_IMX)
|
||||
struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t sdhc1_pads[] = {
|
||||
MX35_PAD_SD1_CMD__ESDHC1_CMD,
|
||||
MX35_PAD_SD1_CLK__ESDHC1_CLK,
|
||||
MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
|
||||
MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
|
||||
MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
|
||||
MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
|
||||
};
|
||||
|
||||
/* configure pins for SDHC1 only */
|
||||
imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
|
||||
|
||||
/* MMC Card Detect on GPIO1_7 */
|
||||
imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
|
||||
gpio_direction_input(GPIO_MMC_CD);
|
||||
|
||||
/* MMC Write Protection on GPIO1_8 */
|
||||
imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
|
||||
gpio_direction_input(GPIO_MMC_WP);
|
||||
|
||||
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
return !gpio_get_value(GPIO_MMC_CD);
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
int rev = 0;
|
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
|
||||
}
|
||||
|
|
@ -87,7 +87,10 @@ CONFIG_PHY=y
|
|||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_DM_PMIC=y
|
||||
# CONFIG_SPL_PMIC_CHILDREN is not set
|
||||
CONFIG_DM_PMIC_DA9063=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_DA9063=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_PWM=y
|
||||
CONFIG_PWM_IMX=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,4 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_ICACHE_OFF=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_IMXRT=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80002000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
|
|
|
|||
|
|
@ -97,3 +97,8 @@ CONFIG_DM_VIDEO=y
|
|||
# CONFIG_VIDEO_BPP32 is not set
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_VIDEO_IPUV3=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_RGMII=y
|
||||
|
|
|
|||
|
|
@ -81,6 +81,11 @@ CONFIG_SF_DEFAULT_MODE=0
|
|||
CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_MDIO=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
|
|
|
|||
|
|
@ -61,3 +61,6 @@ CONFIG_DM_USB=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ CONFIG_SPI_FLASH_STMICRO=y
|
|||
CONFIG_PHYLIB=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_DM_PMIC=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@ CONFIG_ENV_OFFSET=0xC0000
|
|||
CONFIG_DM_GPIO=y
|
||||
CONFIG_TARGET_MX7DSABRESD=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
# CONFIG_ARMV7_VIRT is not set
|
||||
CONFIG_IMX_RDC=y
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@ CONFIG_ENV_OFFSET=0xC0000
|
|||
CONFIG_DM_GPIO=y
|
||||
CONFIG_TARGET_MX7DSABRESD=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
# CONFIG_ARMV7_VIRT is not set
|
||||
CONFIG_IMX_RDC=y
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
|
|
|
|||
|
|
@ -1,51 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_TARGET_WOODBURN=y
|
||||
CONFIG_SYS_TEXT_BASE=0xA0000000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="woodburn U-Boot > "
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_PARTITION_UUIDS is not set
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xA0080000
|
||||
CONFIG_ENV_ADDR_REDUND=0xA00A0000
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_MXC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_TARGET_WOODBURN_SD=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||
CONFIG_SPL_TEXT_BASE=0x10002300
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="woodburn U-Boot > "
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_PARTITION_UUIDS is not set
|
||||
# CONFIG_SPL_PARTITION_UUIDS is not set
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xA0080000
|
||||
CONFIG_ENV_ADDR_REDUND=0xA00A0000
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_MXC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
|
|
@ -499,7 +499,7 @@ static int lpuart_serial_probe(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
} else {
|
||||
dev_warn(dev, "Failed to get per clk: %d\n", ret);
|
||||
debug("%s: Failed to get per clk: %d\n", __func__, ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,12 @@
|
|||
#undef CONFIG_BOOTM_NETBSD
|
||||
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define USDHC1_BASE_ADDR 0x5B010000
|
||||
#define USDHC2_BASE_ADDR 0x5B020000
|
||||
#define USDHC3_BASE_ADDR 0x5B030000
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
|
@ -63,11 +68,9 @@
|
|||
"panel=NULL\0" \
|
||||
"console=ttyLP0\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=imx8qm-rom7720-a1.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@
|
|||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon\0" \
|
||||
"console=ttyLP0\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
|
|
@ -104,7 +104,7 @@
|
|||
"echo wait for boot; " \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
|
|
|
|||
|
|
@ -66,7 +66,6 @@
|
|||
"ramdisk_addr_r=0x13000000\0" \
|
||||
"ramdiskaddr=0x13000000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"console=" CONSOLE_DEV ",115200\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
|
|
|
|||
|
|
@ -75,12 +75,4 @@
|
|||
#define CONFIG_POWER_PFUZE100
|
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
#endif /* __MX6SABREAUTO_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -62,13 +62,4 @@
|
|||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
|
||||
#endif
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
|
||||
#endif /* __MX6SABRESD_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -32,13 +32,6 @@
|
|||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration for the woodburn board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include "woodburn_common.h"
|
||||
|
||||
/* Set TEXT at the beginning of the NOR flash */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,195 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration for the woodburn board.
|
||||
*/
|
||||
|
||||
#ifndef __WOODBURN_COMMON_CONFIG_H
|
||||
#define __WOODBURN_COMMON_CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_MX35
|
||||
#define CONFIG_MX35_HCLK_FREQ 24000000
|
||||
#define CONFIG_SYS_FSL_CLK
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
|
||||
|
||||
/* This is required to setup the ESDC controller */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
|
||||
/* PMIC Controller */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_FSL
|
||||
#define CONFIG_POWER_FSL_MC13892
|
||||
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
|
||||
#define CONFIG_RTC_MC13XXX
|
||||
|
||||
/* mmc driver */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
|
||||
/*
|
||||
* UART (console)
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Command definition
|
||||
*/
|
||||
|
||||
#define CONFIG_NET_RETRY_COUNT 100
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
|
||||
|
||||
/*
|
||||
* Ethernet on SOC (FEC)
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
|
||||
IRAM_BASE_ADDR - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
|
||||
CONFIG_SYS_GBL_DATA_OFFSET)
|
||||
|
||||
/*
|
||||
* MTD Command for mtdparts
|
||||
*/
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
/* Monitor at beginning of flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
|
||||
/*
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
|
||||
/* A non-standard buffered write algorithm */
|
||||
|
||||
/*
|
||||
* NAND FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_NAND_MXC_V1_1
|
||||
#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/*
|
||||
* Default environment and default scripts
|
||||
* to update uboot and load kernel
|
||||
*/
|
||||
|
||||
#define CONFIG_HOSTNAME "woodburn"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip_sta=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
|
||||
"addip=if test -n ${ipdyn};then run addip_dyn;" \
|
||||
"else run addip_sta;fi\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=ttymxc0,${baudrate}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
|
||||
"loadaddr=80800000\0" \
|
||||
"kernel_addr_r=80800000\0" \
|
||||
"hostname=" CONFIG_HOSTNAME "\0" \
|
||||
"bootfile=" CONFIG_HOSTNAME "/uImage\0" \
|
||||
"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
|
||||
"net_self=if run net_self_load;then " \
|
||||
"run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
|
||||
"else echo Images not loades;fi\0" \
|
||||
"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
|
||||
"update=protect off ${uboot_addr} +80000;" \
|
||||
"erase ${uboot_addr} +80000;" \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
"else echo Error updating u-boot !;" \
|
||||
"echo Board without bootloader !!;" \
|
||||
"fi;" \
|
||||
"else echo U-Boot not downloaded..exiting;fi\0" \
|
||||
"bootcmd=run net_nfs\0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration for the woodburn board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include "woodburn_common.h"
|
||||
|
||||
/* Set TEXT in RAM */
|
||||
|
||||
/*
|
||||
* SPL
|
||||
*/
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
|
||||
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
|
||||
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,10 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
|
||||
|
|
@ -275,6 +271,11 @@
|
|||
#define IMX6SX_PLL6_BYPASS 262
|
||||
#define IMX6SX_PLL7_BYPASS 263
|
||||
#define IMX6SX_CLK_SPDIF_GCLK 264
|
||||
#define IMX6SX_CLK_CLK_END 265
|
||||
#define IMX6SX_CLK_LVDS2_SEL 265
|
||||
#define IMX6SX_CLK_LVDS2_OUT 266
|
||||
#define IMX6SX_CLK_LVDS2_IN 267
|
||||
#define IMX6SX_CLK_ANACLK2 268
|
||||
#define IMX6SX_CLK_MMDC_P1_IPG 269
|
||||
#define IMX6SX_CLK_CLK_END 270
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue