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https://github.com/AsahiLinux/u-boot
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Merge branch 'master' of git://git.denx.de/u-boot-usb
- dwc3 and cdns3 bug fixes
This commit is contained in:
commit
d792b63feb
4 changed files with 19 additions and 16 deletions
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@ -883,6 +883,8 @@ M: Marek Vasut <marex@denx.de>
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S: Maintained
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T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git
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F: drivers/usb/
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F: common/usb.c
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F: common/usb_kbd.c
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USB xHCI
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M: Bin Meng <bmeng.cn@gmail.com>
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@ -10,6 +10,7 @@
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* Peter Chen <peter.chen@nxp.com>
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*/
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#include <cpu_func.h>
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#include <linux/usb/composite.h>
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#include <linux/iopoll.h>
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@ -622,15 +622,19 @@ static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
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/* Set dwc3 usb2 phy config */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg |= DWC3_GUSB2PHYCFG_PHYIF;
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reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
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switch (hsphy_mode) {
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case USBPHY_INTERFACE_MODE_UTMI:
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reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
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reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
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DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
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reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
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DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
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break;
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case USBPHY_INTERFACE_MODE_UTMIW:
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reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
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reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
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DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
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reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
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DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
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break;
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default:
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break;
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@ -162,18 +162,14 @@
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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#define DWC3_GUSB2PHYCFG_PHYIF BIT(3)
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/* Global USB2 PHY Configuration Mask */
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
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/* Global USB2 PHY Configuration Offset */
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
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DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
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DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
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#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
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#define USBTRDTIM_UTMI_8_BIT 9
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#define USBTRDTIM_UTMI_16_BIT 5
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#define UTMI_PHYIF_16_BIT 1
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#define UTMI_PHYIF_8_BIT 0
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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