Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS for host controllers which do not
support 64-bit addressing.
Ported from Linux kernel commit
6554400d6f66 ("scsi: ufs: core: Add UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS")
with ufs_scsi_buffer_aligned() based on U-Boot generic bounce buffer.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Tested-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Use BIT() macro for quirks, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Some devices have limited DMA capabilities and require that the
buffers passed to them fit specific properties. Add new optional
callback which can be used at driver level to indicate whether a
buffer alignment is suitable for the device DMA or not. This is
a pass-through callback from block uclass to drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Some devices have limited DMA capabilities and require that the
buffers passed to them fit specific properties. Add new optional
callback which can be used at driver level to indicate whether a
buffer alignment is suitable for the device DMA or not, and
trigger use of generic bounce buffer implementation to help use
of unsuitable buffers at the expense of performance degradation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Move the macro into blk-uclass.c , since it is only used there.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move part_create_block_devices() to blk uclass and unexpose
the function. This can now be internal to the block uclass.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This patch introduces EVT_DM_POST_INIT_R event type for handling hooks
after relocation.
Fixes: 55171aedda ("dm: Emit the arch_cpu_init_dm() even only before relocation")
Suggested-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
Fixed missing event name in event.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
replace info logs with debug logs
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Waiting 150us TC bit couldn't be enough.
If TFA lets 16 bits in USART fifo, we has to wait 16 times 87 us (time
of 10 bits (1 byte in most use cases) at a baud rate of 115200).
Fixes: b4dbc5d65a ("serial: stm32: Wait TC bit before performing initialization")
Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
To disabled a clock in clock tree initialization for a mux of STM32MP15,
the selected clock source index is set with the latest possible index for
the number of bit used. Today this valid configuration cause a error
in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock
is not needed for the used ETH PHY without crystal:
no parents defined for clk id 123
This patch change the level of this message to avoid this trace for
valid clock tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Select the same mac divider for SGMII too as the one being used for
QSGMII.
Enable full rate divider configuration support for J721E_WIZ_10G for
SGMII.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Enhance the AM65 CPSW NUSS driver to perform a MDIO reset using a GPIO
line. Logic is also added to perform a pre and post delay around reset
using the optional 'reset-delay-us' and 'reset-post-delay-us' properties.
This is similar to the reset being performed in the Linux kernel. The
reset is done once when the CPSW MDIO bus is being initialized.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
The PSIL endpoint data for J721E currently covers only the MCU domain
CPSW0 instance. Add the data for the MAIN domain CPSW0 as well to allow
the MAIN domain Ethernet ports to be usable on any platform using J721E
SoC.
Additionally, since J721E's PSIL endpoint data is applicable to J7200
SoC as well, the MAIN CPSW0 instance on J7200 will also be usable now.
Signed-off-by: Suman Anna <s-anna@ti.com>
[s-vadapalli@ti.com: Update commit message indicating support for J7200]
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
The MVTWSI controller can act either as a master or slave device. When
acting as a master, the FSM is driven by the CPU. As a slave, the FSM is
driven by the bus directly. In what is (apparently) a safety mechanism,
if the bus transitions our FSM in any improper way, the FSM goes to a
"bus error" state (0x00). I could find no documented or experimental way
to get the FSM out of this state, except for a controller reset.
Since U-Boot only uses the MVTWSI controller as a bus master, this
feature only gets in the way: we do not care what happened on the bus
previously as long as the bus is ready for a new transaction. So, when
trying to start a new transaction, check for this state and reset the
controller if necessary.
Note that this should not be confused with the "deblocking" technique
(used by the `i2c reset` command), which involves pulsing SCL repeatedly
if SDA is found to be held low, in an attempt to force the bus back to
an idle state. This patch only resets the controller in case something
else had previously upset it, and (in principle) results in no
externally-observable change in behavior.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
The current gpio-uclass design uses name field in struct gpio_dev_priv as
an indicator that GPIO is claimed by consumer. This overloads the function
of name field and does not work well for named pins not configured as GPIO
pins.
Introduce separate bitfield array as the claim indicator.
This unbreaks dual-purpose AF and GPIO operation on STM32MP since commit
2c38f7c318 ("pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name")
where any pin which has already been configured as AF could no longer be
claimed as dual-purpose GPIO. This is important for pins like STM32 MMCI
st,cmd-gpios .
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new DM driver supporting FTPCI100 IP used in SoC designs.
This implementation is not based on the old non-DM ftpci100 code
dropped from U-Boot.
Enable the driver in sandbox_defconfig to test compilability.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
This function only ever returns 0, but may not assign the second
parameter. Same thing for device_find_next_child(). Do not assign
ret to stop proliferation of this misuse.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This is merely a dummy driver that makes sure the DWC3 XHCI driver
finds its reset and PHY controllers. We rely on iBoot to set up
the PHY for us.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
The Apple hardware supports 64-bit prefetchable memory windows so
enable CONFIG_SYS_PCI_64BIT. This fixes BAR assignments for the
Broadcom Ethernet controller used in some of the desktop machines.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
With the commit 4fcba5d556 ("regulator: implement basic reference
counter"), keeping regulator enablement in balance become more important.
Disable vqmmc-supply before signal voltage is changed to keep regulator
enable counter in balance.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # P895 Tegra 3;
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
Reviewed-by: Marek Vasut <marex@denx.de>
With the commit 4fcba5d556 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.
This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.
Could not get PHY for ethernet@fe010000: addr 0
Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.
Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.
Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.
Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Meng Li <Meng.Li@windriver.com>
At present vidconsole_measure() tests ops->select_font before calling
ops->measure, which would result in a null dereference when the console
driver provides no ops for measure.
Fixes: b828ed7d79 ("console: Allow measuring the bounding box of text")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Once all the other drivers got torn down in preparation for the OS
to start, tear down the clock controller last. The clock controller
must be torn down last as some of the clock which get turned off
might have still been needed during the teardown stage of the other
drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.
The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.
Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.
ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Fix this by including support for UART clocks in SPL.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix use of wrong clk selection for CLK_PWM1 on RK3568.
Fixes: 4a262feba3 ("rockchip: rk3568: add clock driver")
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
533ad9dc avoided an overflow but causes compilation
failure on 32bit boards (eg. veyron speedy)
this commit uses div_u64 which has a fallback codepath
for 32bit platforms
Signed-off-by: Alvaro Fernando García <alvarofernandogarcia@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4 ("pci: pcie_dw_rockchip: release
resources on failing probe").
Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.
Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.
Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ftwdt010_wdt_start() has to call ftwdt010_wdt_reset() after setting-up
the timeout in the same fashion ftwdt010_wdt_expire_now() does it.
Without this patch the "wdt start <ms>" command does not actually start
the watchdog timer until the "wdt reset" command is executed.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
At present this feature is enabled in SPL if a bloblist is available.
Some platforms may not want to use this, so add an option to allow the
feature to be disabled.
Note that the feature unfortunately only fills in part of the
video-handoff information, so causes failures on x86 platforms. For now,
disable it there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
Drop the duplication and add a single rule which can handle SPL as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use the correct function here, since there may be multiple IDE devices
available.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This name is a little confusing since it suggests that it sets up the
sibling block device. In fact it sets up a bootdev for it. Rename the
function to make this clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
When USB finds no devices it currently returns -EPERM which bootstd does
not understand. This causes other bootdevs of the same priority to be
skipped.
Fix this by returning the correct error code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now all linker symbols are declared as type char[]. Though we can
reference the address via both the array name 'var' and its address
'&var'. It's better to unify them to avoid confusing developers.
This patch converts all '&var' linker symbol refrences to the most
commonly used format 'var'.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
It is not a parse error to have a default value of "0" for a "hex" type
entry, instead of "0x0". However, "0" and "0x0" are not treated the
same even by the tools themselves. Correct this by changing the default
value from "0" to "0x0" for all hex type questions that had the
incorrect default. Fix one instance (in two configs) of a default of "0"
being used on a hex question to be "0x0". Remove the cases where a
defconfig had set a value of "0x0" to be used as the default had been
"0".
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If an error message contains a function name, it should match the name of
the function throwing the message.
Fixes: 7739d93d82 ("pci: Match region flags using a mask")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We know that "pa" is non-NULL so it's nicer to just return zero instead
of return !pa. This has no effect on runtime behavior.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The "oftree_count" is the number of entries which have been set in
the oftree_list[] array. If all the entries have been initialized then
this off by one would result in reading one element beyond the end
of the array.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The ec_command_inptr() function returns negative error codes or
the number of bytes that it was able to read. The cros_ec_get_sku_id()
function should return negative error codes. Right now it returns
positive error codes or negative byte counts.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Both the Linux kernel and libbsd agree that strlcpy() should always
return strlen(src) and not include the NUL termination. The incorrect
U-Boot implementation makes it impossible to check the return value for
truncation, and breaks code written with the usual implementation in
mind (for example, fdtdec_add_reserved_memory() was subtly broken).
I reviewed all callers of strlcpy() and strlcat() and fixed them
according to my understanding of the intended function.
This reverts commit d3358ecc54 and adds
related fixes.
Fixes: d3358ecc54 ("lib: string: Fix strlcpy return value")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Provide armffa command showcasing the use of the U-Boot FF-A support
armffa is a command showcasing how to invoke FF-A operations.
This provides a guidance to the client developers on how to
call the FF-A bus interfaces. The command also allows to gather secure
partitions information and ping these partitions. The command is also
helpful in testing the communication with secure partitions.
For more details please refer to the command documentation [1].
A Sandbox test is provided for the armffa command.
[1]: doc/usage/cmd/armffa.rst
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support
Features of the sandbox FF-A support:
- Introduce an FF-A emulator
- Introduce an FF-A device driver for FF-A comms with emulated Secure World
- Provides test methods allowing to read the status of the inspected ABIs
The sandbox FF-A emulator supports only 64-bit direct messaging.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add Arm FF-A support implementing Arm Firmware Framework for Armv8-A v1.0
The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1]
describes interfaces (ABIs) that standardize communication
between the Secure World and Normal World leveraging TrustZone
technology.
This driver uses 64-bit registers as per SMCCCv1.2 spec and comes
on top of the SMCCC layer. The driver provides the FF-A ABIs needed for
querying the FF-A framework from the secure world.
The driver uses SMC32 calling convention which means using the first
32-bit data of the Xn registers.
All supported ABIs come with their 32-bit version except FFA_RXTX_MAP
which has 64-bit version supported.
Both 32-bit and 64-bit direct messaging are supported which allows both
32-bit and 64-bit clients to use the FF-A bus.
FF-A is a discoverable bus and similar to architecture features.
FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed
by the PSCI driver.
Clients are able to probe then use the FF-A bus by calling the DM class
searching APIs (e.g: uclass_first_device).
The Secure World is considered as one entity to communicate with
using the FF-A bus. FF-A communication is handled by one device and
one instance (the bus). This FF-A driver takes care of all the
interactions between Normal world and Secure World.
The driver exports its operations to be used by upper layers.
Exported operations:
- ffa_partition_info_get
- ffa_sync_send_receive
- ffa_rxtx_unmap
Generic FF-A methods are implemented in the Uclass (arm-ffa-uclass.c).
Arm specific methods are implemented in the Arm driver (arm-ffa.c).
For more details please refer to the driver documentation [2].
[1]: https://developer.arm.com/documentation/den0077/latest/
[2]: doc/arch/arm64.ffa.rst
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Move the ethernet gadget driver registration and removal from ethernet
bind and unbind callbacks into driver DM probe and remove callbacks.
This way, when the driver is bound, which is triggered deliberately
using 'bind' command, the USB ethernet gadget driver is instantiated
and bound to the matching UDC. In reverse, when the driver is unbound,
which is again triggered deliberately using 'unbind' command, the USB
ethernet gadget driver instance is removed.
Effectively, this now behaves like running either 'ums' or 'dfu' or
any other commands utilizing USB gadget functionality.
This also drops use of usb_gadget_release() and moves the use of
usb_gadget_initialize() into usb_ether_init() used only by legacy
platforms that do not use 'bind' command properly yet. Those have
no place in drivers.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Move the driver probe function above the driver structure, so it
can be placed alongside other related functions, like upcoming
remove function. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
These functions here are only ever called once since drop of non-DM
networking code. Inline them. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
If a driver cannot be bound, provide the driver name in the debug
message. Now the debug message may look like this:
(virtio-pci.l#0): virtio-rng driver not configured
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds support for MediaTek MT7988.
MT7988 features MediaTek NETSYS v3, including three GMACs, and two
of them supports 10Gbps USXGMII.
MT7988 embeds a MT7531 switch (not MCM) which supports accessing
internal registers through MMIO instead of MDIO.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
register must be set to connect the SGMII phy to GMAC2.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Existing SGMII support of mtk-eth is actually a MediaTek-specific
2.5Gbps high-speed SGMII (HSGMII) which does not support
auto-negotiation mode.
This patch adds SGMII 1Gbps auto-negotiation mode and rename the
existing HSGMII to 2500basex.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
mt7531_mmd_ind_read and mt753x_switch_init are defined without static.
Since they're not used outside this file, we should add them back.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
fixup to add static qualifier
The original direct MDIO clause 45 access via SoC is missing the
data output. This patch adds it back to ensure MDIO clause 45 can
work properly for external PHYs.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Not all switches requires 1 second delay after deasserting reset.
MT7531 requires only maximum 200ms.
This patch defines dedicated reset wait time for each switch chip, and will
significantly improve the boot time for boards using MT7531.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
So far the switch is initialized in probe stage and is connected to PSE
unconditionally. This will cause all packets being flooded to PSE and may
cause PSE hang before entering linux.
This patch changes the connection between switch and PSE:
- Still initialize switch in probe stage, but disconnect it with PSE
- Connect switch with PSE on eth start
- Disconnect on eth stop
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The original mediatek pinctrl functions for driving configuration
'mtk_pinconf_drive_set_*' do not return -ENOSUPP even if input
parameters are not supported.
This patch fixes the return value in those functions.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
There exists a situation of the mediatek pinctrl driver that may return
wrong pin function value for the pinmux driver:
- All pin function arrays are defined without const
- Some pin function arrays contain all-zero value, e.g.:
static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
- These arrays will be put into .bss section during compilation
- .bss section has no "a" attribute and does not exist in the final binary
file after objcopy.
- FDT binary blob is appended to the u-boot binary, which occupies the
.bss section.
- During board_f stage, .bss has not been initialized, and contains the
data of FDT, which is not full-zero data.
- pinctrl driver is initialized in board_f stage, and it will get wrong
data if another driver is going to set default pinctrl.
Since pinmux information and soc data are only meant to be read-only, thus
should be declared as const. This will force all pinctrl data being put
into .rodata section. Since .rodata has "a" attribute, even the all-zero
data will be allocated and filled with correct value in to u-boot binary.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
MT7981 actually uses MediaTek I2C controller v3 instead of v1.
This patch adds support for I2C controller v3 fix fixes the I2C usability
for MT7981.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch add missing return value check for allocating the driver's
private data. -ENOMEM will be returned if malloc() fails.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch ensures driver private data being fully initialized in
_debug_uart_init which is not covered by .priv_auto ops.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Stefan Roese <sr@denx.de>
In u-boot we don't use IRQ. Instead, we poll busy bit in SPI_STATUS.
However these IRQ enable bits may be set in previous boot stage (BootROM).
If we leave these bits not cleared, although u-boot has disabled IRQ and
nothing will happen, the linux kernel may encounter panic during
initializing the spim driver due to IRQ event happens before IRQ handler
is properly setup.
This patch clear IRQ bits to prevent this from happening.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
We don't really need to switch clk rate during operating SPIM controller.
Get clk rate only once at driver probing.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add rtl8169 NIC device ID and reorder the device ID.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
For RISC-V architeture, hardware maintain the dcache coherency.
Software do not flush the cache. So even cache-line size larger
than descriptor size, driver can work.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
While compiling rtl8169.c, There are many "make pointer from
integer without a cast" compile warnings. fix them with
adding cast.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.
Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
As the Designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
JH7110) contain Designware i2c and PCI but do not use ACPI,
This file cannot be compiled. So add a new Kconfig for
designware_i2c_pci.c, which depends on ACPIGEN
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
- Add a little more info to 'cbsysinfo' command
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEUEWE0gAMrH0ckwrwqSElQ6ZwxhQFAmTIbdEACgkQqSElQ6Zw
xhSTCg//TESlLII0mIDIP/Ahoac0qBcALRLPiZNzIG8cUtETsLblwQ4ndCyRNohI
EbRAWdZasVB0mn1wpLX58FjeCpz7u73pS+RIdY4YnkGWCebGO1E04fRPWk1euT6N
PsJSfQ4WUXbPOsP89AVDmYQ7KgbdgW7CcN4iRp931h5+Xy2OMjMNlHrBE/iXToaL
wsGU+WM+KPjqt/Z79goyWSm997wXyLzM844f14/Cv+GnZUsaLKDMdW4S7eyM7OSk
tqkTyq/L5Yf15G3gzVBZzXk5PgcfoXugOelfr5m+yQLUIXJIR5c+yptqwKuQ4MM/
PEuL7+3ytodpG1lEVtqAxg08/AQYGr6CpTMXPOZXbsaaQYQcVG/V28eMchgQF/YD
3lE0ZKSv/t6Ar6iRwKsZE5f+8DslnGip5W41mEBEIgSYyt7yXO0p+cQxkPcArK1E
qyQIESmiPF3GaWarAtNWyoASVFLtIXiUaSne2lnvKP4vNlM36/rB72Ii6OX7sSZZ
Xm4yEBeDpNqMQ99QjQurSFOzwQY+BULlNL36h4mWZALKNONWhXL0N/0JcWFJBl+t
ha84lQwr+u/7J+ZSjNNNH4bXJOYyuZBFDl27btSgHN046iJioobf8jgbbx2WxQ5P
khbcYliKf678Xi/HCQD3CyYmyCYw5VHlUTyQlbgCeC6GQumZwnY=
=s8Ab
-----END PGP SIGNATURE-----
Merge tag 'x86-pull-20230801' of https://source.denx.de/u-boot/custodians/u-boot-x86
- MTRR fixes for x86 boards
- Add a little more info to 'cbsysinfo' command
- bochs: remove the x86 limitation
- correct kconfig text for PCI default FB size
- kconfig: drop the superfluous PCI dependency
- set up default FB size for Bochs
-----BEGIN PGP SIGNATURE-----
iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCZMj+xA4cYWd1c3RAZGVu
eC5kZQAKCRBM6ATMmsalXPovAJ9DU0H3Xm9LmrPZE4NzmmkfKJ/99QCfTlDfIkZI
dVilMWOHsRX1SgMS6YM=
=KYKc
-----END PGP SIGNATURE-----
Merge tag 'video-20230801' of https://source.denx.de/u-boot/custodians/u-boot-video
- dm video cosmetic style fix
- bochs: remove the x86 limitation
- correct kconfig text for PCI default FB size
- kconfig: drop the superfluous PCI dependency
- set up default FB size for Bochs
Perform removal of DSS if kconfigs VIDEO_REMOVE or SPL_VIDEO_REMOVE is
set by user. Otherwise if above Kconfigs are not selected, it is assumed
that user wants splash screen to be displayed until linux kernel boots
up. In such scenario, leave the power domain of DSS as "on" so that
splash screen stays intact until kernel boots up.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Change remove method of DSS video driver to disable video port instead
of performing a soft reset, as soft reset takes longer duration. Video
port is disabled by setting enable bit of video port to 0.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
At present the uclass stored frame buffer size is set to a hard
coded value, but we can calculate the correct value based on what
is configured.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
Set up a default frame buffer size of 8MiB for Bochs for non-x86
architecturs as PCI is normally not enumerated before relocation
on these architectures.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
PCI is always selected by X86 architecture hence "X86 && PCI" does
not make it better.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
There is an example in the VIDEO_PCI_DEFAULT_FB_SIZE help text to
tell people how to calculate its value but the resolution given
does not match the value. Fix it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that the driver is legacy free, remove the x86 dependency so
that it can be used on non-x86 architectures.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
At present the driver uses IO instructions to access the legacy
VGA IO ports, which unfortunately limits the driver to work only
on x86. It turns out the IO instruction is not necessary as Bochs
VGA card remaps the legacy VGA IO ports (0x3c0 -> 0x3df) to its
memory mapped register space from offset 0x400.
Update the driver to use MMIO access for VGA IO port.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
bochs_vga_write() takes 'index' as one argument, but never uses it.
While we are here, use macros instead of magic numbers for the
VGA IO port register name and value.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
The driver does not call any MTRR APIs.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
Some coding convention fixes for video_post_bind().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
has full control with MTRR programming (e.g.: U-Boot without any blob
that does all low-level initialization on its own, or using FSP2 which
does not touch MTRR), but this is not the case with FSP. FSP programs
some MTRRs during its execution but U-Boot does not have the settings
saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
corrupt what was already programmed previously.
Correct this to use mtrr_set_next_var() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
has full control with MTRR programming (e.g.: U-Boot without any blob
that does all low-level initialization on its own, or using FSP2 which
does not touch MTRR), but this is not the case with FSP. FSP programs
some MTRRs during its execution but U-Boot does not have the settings
saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
corrupt what was already programmed previously.
Correct this to use mtrr_set_next_var() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
has full control with MTRR programming (e.g.: U-Boot without any blob
that does all low-level initialization on its own, or using FSP2 which
does not touch MTRR), but this is not the case with FSP. FSP programs
some MTRRs during its execution but U-Boot does not have the settings
saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
corrupt what was already programmed previously.
Correct this to use mtrr_set_next_var() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Update dwc3 generic driver and update support for rk3568/rk3328;
- Add boards:
rk3566: Pine64 Quartz64-A/B, SOQuartz on Model A/Blade/CM4-IO
rk3568: Radxa E25 Carrier Board
rk3588: Radxa ROCK5A
- Fixes and updates for chromebook veryon/jerry/speedy;
- SPI support fixes for rk3399/rk3568/rk3588;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
Handle USB480M clock ID in set_rate() and set_parent()
to allow the dt assigned-clocks and assigned-clock-parents
work on rk3328.dtsi
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
USB2.0 Host and OTG controllers in RK3328 are using USB2PHY.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Like Rockchip RK3568, the RK3328 also have single node to
represent the glue and ctrl for USB 3.0.
So, use the driver data to use single ctrl for RK3328 DWC3.
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A quick power cycle of a LDO regulator during dw-mmc signal voltage
change has shown that SD-card does not always get recognized.
Linux driver use an enable_time of 400us for LDO regulators. Apply a
500us delay when a LDO regulator is enabled to fix possible issues.
Fixes: 94afc1cb46 ("power: regulator: rk8xx: update the driver for rk808 and rk818")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: elaine.zhang<elaine.zhang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.
Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
RK3568 share glue and ctrl in a single node. Use glue_get_ctrl_dev to
return the glue node as the ctrl node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
When dr_mode is peripheral or otg and U-Boot has not been built with
DM_USB_GADGET support, booting such device may end up with:
dwc3_glue_bind_common: subnode name: usb@fcc00000
Error binding driver 'dwc3-generic-wrapper': -6
Some drivers failed to bind
initcall sequence 00000000effbca08 failed at call 0000000000a217c8 (err=-6)
### ERROR ### Please RESET the board ###
Instead fail gracfully with ENODEV to allow board continue booting.
dwc3_glue_bind_common: subnode name: usb@fcc00000
dwc3_glue_bind_common: unsupported dr_mode 3
Also use CONFIG_IS_ENABLED(USB_HOST) and change switch to if statements
to improve readability of the code.
Fixes: 446e3a205b ("dwc3-generic: Handle the PHYs, the clocks and the reset lines")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
The current error check for device_find_first_child is not working as
expected, the documentation for device_find_first_child mention:
@devp: Returns first child device, or NULL if none
Return: 0
Change to return early when there is no child node to avoid any possible
null pointer dereference.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense.
Fixes: 32f5e9e5c1 ("nvme: pci: Enable for SPL")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Resync some of the K3 DTS files with the kernel, and pull in some
required related updates to keep drivers in sync with the dts files
now. Bring in some incremental fixes on top of one of the series I
applied recently as well as updating the iot2050 platform. Also do a
few small updates to the K2 platforms.
- Enable pcie support for rk3568;
- Add boards:
rk3399: Radxa ROCK 4SE;
rk3328: Orange Pi R1 Plus, Orange Pi R1 Plus LTS
rk3568: FriendlyARM NanoPi R5S/R5C, Hardkernel ODROID-M1
rk3588: Edgeble Neu6B
- support OP-TEE with binman;
- support Winbond SPI flash;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
The TI AM654 timer is compatible with the omap-timer implementation,
so add it to the compatible id list.
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Maxime Ripard <mripard@kernel.org>
Tested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Cc: Francesco Dolcini <francesco@dolcini.it>
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
The dwc_ahci driver use platform specific defines, place the platform
specific code behind a ifdef CONFIG_ARCH_OMAP2PLUS to allow build and
use of the driver on Rockchip platform.
Fixes: 02a4b42979 ("drivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
The commit 12df2c182ccb ("regulator: dt-bindings: fixed-regulator: allow
gpios property") in linux v6.3-rc1 added support for use of either a
gpios or gpio prop with a fixed-regulator.
This adds support for the new gpios prop to the fixed-regulator driver.
gpios prop is used by vcc3v3-pcie-regulator on Radxa ROCK 3 Model A.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Root Complex BARs default to claim the full 1 GiB memory region on
RK3568, leaving no space for any attached device.
Fix this by disable the unused BAR 0 and BAR 1 of the RC.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.
Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.
Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Get the config region to use from the reg prop. Also update the
referenced region index used in comment.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add dev_read_addr_size_index_ptr function with the same functionality as
dev_read_addr_size_index, but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip boot blocks are written per 4 x 512 byte sectors per page.
Each page must have a page address (PA) pointer in OOB to the next page.
Pages are written in a pattern depending on the NAND chip ID.
This logic used to build a page pattern table is not fully disclosed and
is not easy to fit in the MTD framework.
The formula in rk_nfc_write_page_hwecc() function is not correct.
Make hwecc and raw behavior identical.
Generate boot block page address and pattern for hwecc in user space
and copy PA data to/from the already reserved last 4 bytes before EEC
in the chip->oob_poi data layout.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This just needs some extra clocks enabled, and different registers
configured. Copied from Linux, just like the original submitter
of this driver did for rk3568.
Tested on Pinephone Pro.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Approved DT binding has the port mode register in the
"phys" property. Get it from there instead of the custom
"cpsw-phy-sel" property.
This will allow us to keep DT in sync with Linux.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
The approved DT property for MAC efuse (ROM) address is
"ti,syscon-efuse".
Use that and drop custom property "mac_efuse".
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node, like the SK-AM62 Device
Tree does.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
The adin phy has extended registers that can be accessed using
adin_ext_read and adin_ext_write. These registers can be read directly
using the mdio command using readext and writext. For example:
=> mdio rx ethernet@428a0000 0xff23
Reading from bus ethernet@428a0000
PHY at address 0:
65315 - 0xe01
Signed-off-by: Nate Drude <nate.d@variscite.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Copy and tweak the required code from the linux kernel.
Only the KSZ9893 has been tested.
Signed-off-by: Karsten Wiese <karsten.wiese@protechna.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
drivers/core/device.c will call `device_free()` after xhci_register
already frees the private device data. This can cause a crash later
during the boot process, observed on aarch64 RPi4b as a synchronous
exception. All callers of xhci_register use priv_auto, so this won't
lead to memory leaks.
Signed-off-by: Richard Habeeb <richard.habeeb@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This watchdog driver applies to the following
mcf families:
- mcf52x2 (5271 5275 5282)
- mcf532x (5329 5373)
- mcf523x (5235)
Cpu's not listed for each family does not have WDT module.
Note, after some attempts testing by qemu on 5208 i
finally abandoned, watchdog seems not implemented properly.
The driver has been tested in a real M5282EVM.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
---
Changes for v2:
- remove unnecessary hardcoded timeouts
- remove unnecessary hw_watchdog_xxx stuff
- rewrite wdog module reg calculation
- using IS_ENABLED() where possible
Changes for v3:
- remove hardcoded 4s test
In some designs the MAX313xx RTC may need calibration to cope with
oscillator inaccuracies. Provide read8/write8 ops so that the registers
can be accessed. Because the driver covers a range of MAX313xx variants
no attempt is made to ensure the register is valid.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Commit 62649165cb ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned")
fixed cache alignment for systems with a D-CACHE.
However it introduced some performance regressions [1] on system
flashing huge images, such as Android.
On AM62x SK EVM, we also observe such performance penalty:
Sending sparse 'super' 1/2 (768793 KB) OKAY [ 23.954s]
Writing 'super' OKAY [ 75.926s]
Sending sparse 'super' 2/2 (629819 KB) OKAY [ 19.641s]
Writing 'super' OKAY [ 62.849s]
Finished. Total time: 182.474s
The reason for this is that we use an arbitrary small buffer
(info->blksz * 100) for transferring.
Fix it by using a bigger buffer (info->blksz * FASTBOOT_MAX_BLK_WRITE)
as suggested in the original's patch review [2].
With this patch, performance impact is mitigated:
Sending sparse 'super' 1/2 (768793 KB) OKAY [ 23.912s]
Writing 'super' OKAY [ 15.780s]
Sending sparse 'super' 2/2 (629819 KB) OKAY [ 19.581s]
Writing 'super' OKAY [ 17.192s]
Finished. Total time: 76.569s
[1] https://lore.kernel.org/r/20221118121323.4009193-1-gary.bisson@boundarydevices.com
[2] https://lore.kernel.org/r/all/43e4c17c-4483-ec8e-f843-9b4c5569bd18@seco.com/
Fixes: 62649165cb ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
This driver considers that a node with an empty label is the top.
But the led class has changed, if a label is not provided for a led,
the label is filed with the node name. So we update this driver
to use a wrapper to manage the top led node.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit of a
challenge.
The backing memory for sec_proxy is regular memory, and all sec proxy
does is to trigger a burst of all 60 bytes of data over to the target
thread backing ring accelerator. It doesn't do a memory scrub when
it moves data out in the burst. When we transmit multiple messages,
remnants of previous message is also transmitted which results in
some random data being set in TISCI fields of messages that have been
expanded forward.
The entire concept of backward compatibility hinges on the fact that
the unused message fields remain 0x0 allowing for 0x0 value to be
specially considered when backward compatibility of message extension
is done.
So, instead of just writing the completion register, we continue
to fill the message buffer up with 0x0 (note: for partial message
involving completion, we already do this).
This allows us to scale and introduce ABI changes back also work with
other boot stages that may have left data in the internal memory.
While at this, drop the unused accessor function.
Fixes: f9aa41023b ("mailbox: Introduce K3 Secure Proxy Driver")
Signed-off-by: Nishanth Menon <nm@ti.com>
This reverts commit d927d1a808, reversing
changes made to c07ad9520c.
These changes do not pass CI currently.
Signed-off-by: Tom Rini <trini@konsulko.com>
Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support
Features of the sandbox FF-A support:
- Introduce an FF-A emulator
- Introduce an FF-A device driver for FF-A comms with emulated Secure World
- Provides test methods allowing to read the status of the inspected ABIs
The sandbox FF-A emulator supports only 64-bit direct messaging.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Provide armffa command showcasing the use of the U-Boot FF-A support
armffa is a command showcasing how to invoke FF-A operations.
This provides a guidance to the client developers on how to
call the FF-A bus interfaces. The command also allows to gather secure
partitions information and ping these partitions. The command is also
helpful in testing the communication with secure partitions.
For more details please refer to the command documentation [1].
[1]: doc/usage/cmd/armffa.rst
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add Arm FF-A support implementing Arm Firmware Framework for Armv8-A v1.0
The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1]
describes interfaces (ABIs) that standardize communication
between the Secure World and Normal World leveraging TrustZone
technology.
This driver uses 64-bit registers as per SMCCCv1.2 spec and comes
on top of the SMCCC layer. The driver provides the FF-A ABIs needed for
querying the FF-A framework from the secure world.
The driver uses SMC32 calling convention which means using the first
32-bit data of the Xn registers.
All supported ABIs come with their 32-bit version except FFA_RXTX_MAP
which has 64-bit version supported.
Both 32-bit and 64-bit direct messaging are supported which allows both
32-bit and 64-bit clients to use the FF-A bus.
FF-A is a discoverable bus and similar to architecture features.
FF-A bus is discovered using ARM_SMCCC_FEATURES mechanism performed
by the PSCI driver.
Clients are able to probe then use the FF-A bus by calling the DM class
searching APIs (e.g: uclass_first_device).
The Secure World is considered as one entity to communicate with
using the FF-A bus. FF-A communication is handled by one device and
one instance (the bus). This FF-A driver takes care of all the
interactions between Normal world and Secure World.
The driver exports its operations to be used by upper layers.
Exported operations:
- ffa_partition_info_get
- ffa_sync_send_receive
- ffa_rxtx_unmap
Generic FF-A methods are implemented in the Uclass (arm-ffa-uclass.c).
Arm specific methods are implemented in the Arm driver (arm-ffa.c).
For more details please refer to the driver documentation [2].
[1]: https://developer.arm.com/documentation/den0077/latest/
[2]: doc/arch/arm64.ffa.rst
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
-----BEGIN PGP SIGNATURE-----
iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmS+Xv0cHGV1Z2VuLmhy
aXN0ZXZAY29sbGFib3JhLmNvbQAKCRAesx4CDqwvyMgxB/9BTjFfVaglu5+m/kiw
XEVSJSwe1H3sc5vFlMUYTSAOSF/mzdZIZHXC6THkCU1yfzu9AZXhp4mfRUiNTwth
w8bvYXm4ZjSxcGPVxVqfThN8iT/SWLpaUC8j7TosP1VKYwzpGmqLyO+ZLu7IwdH+
/wyXFuYtVQVxmSC6SMNAD5eNtS4O6pufat5e5EkhR2atZ/rhhAYmb9zv3RFuCuSM
bxqM+4/FqpENaIdMOPk7EbB3S1C5MsJS2b+s1oIRRLfItlLjpQG4nZnuJGRlL/Bg
mcqYYgHrAnFbLXVOEe5WxMKR1E2fMbtKSlJGpoYO9rSdQRzxGuyRrDm9M77GH2pJ
0Q/F
=DT1v
-----END PGP SIGNATURE-----
Merge tag 'u-boot-at91-fixes-2023.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-atmel fixes for the 2023.07 cycle:
This small fixes set includes the LTO configs for the boards that had
the SPL size up to the limit (sama5d2-based), such that more code can be
added. It also includes a fix for mmc non-removable.
If the device attached to the MMC bus is not removable, set force card-detect
bit to bypass card detection procedure, so card detection pin can be used for
other purposes.
It's also a workaround for SAMA5D2 who doesn't drive CMD if using GPIO for card
detection.
Signed-off-by: Zixun LI <zli@ogga.fr>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Drop the PLL part in SYSCRG driver and separate to be a single
PLL driver of which the compatible is "starfive,jh7110-pll".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This is required since user may want to either call the remove method
of video driver and reset the display or not call the remove method
to continue displaying until next stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
U-boot proper can use frame buffer address passed from SPL to reserve
the memory area used by framebuffer set in SPL so that splash image
set in SPL continues to get displayed while u-boot proper is running.
Put the framebuffer address and size in a bloblist to make them
available at u-boot proper, if in u-boot proper CONFIG_VIDEO is defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add method to reserve video framebuffer information using blob,
received from previous stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.
Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.
Signed-off-by: Bryan Brattlof <bb@ti.com>
For once this adds USB support for two SoCs: the H616 and the F1C100s
series. The rest is support for LPDDR3 DRAM chips on H616 boards.
Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s
board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that
works for Mikhail, and doesn't regress on my DDR3 boards.
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZLqHzgAKCRDKSWXLKUoM
IcdEAKCSgy0lMxb1c0adCjpkQR9x63oKbQCdGiioU+W+0moznHdI7+W2UptNt3w=
=Uzn8
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.10-rc1 v2
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
This enables implementing custom logic after a bitstream was loaded
into the fpga.
Signed-off-by: Christian Taedcke <christian.taedcke@weidmueller.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/20230720072724.11516-1-christian.taedcke-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
If there is no incoming package than axiemac_recv will return -1 which
in turn leads to printing `eth_rx: recv() returned error -1` error
message in eth_rx function. But missing a package is not an fatal error,
so return -EAGAIN in that case would be more suitable.
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230719065337.69280-1-bigunclemax@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Dll reset is needed only for ZynqMP platforms, add condition in tuning
to call arasan_zynqmp_dll_reset() just for ZynqMP platforms.
On other platforms like Versal NET, If this condition is not added, we
see PLM error messages when dll reset smc is called.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.
Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.
Add read_delay initialization for Versal NET also.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
As per spec MDC must not exceed 2.5MHz, read the pclk clock
from the device tree and update the MDC clock divisor.
GEM devices support larger clock divisors and have a different
range of divisors. Program the MDIO clock divisors based on
the clock rate of the pclk clock.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230619034922.24019-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
status and ecc_status are of unsigned type where they are compared for
negative value. This is pointed by below sparse warning. Change datatype
to int to fix this.
warning: comparison of unsigned expression in '< 0' is always false
[-Wtype-limits]
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614090359.10809-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
When one of the functions does not support super speed, the composite
driver forces the gadget to high speed. But the speed is never
configured in the cdns3 gadget driver. So configure the speed
in cdns3_gadget_udc_start just like in the kernel.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Remove the regulator_set_enable() call from device probe which
resolves a regulator imbalance. This is unnecessary as
regulator_set_enable() will be called when ehci_register calls the
init_after_reset hook.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Now that the Allwinner USB PHY driver supports the H616 quirk, let's
enable support for USB ports on that SoC.
We connect the compatible string to a new struct describing the SoCs USB
PHY properties, and unblock the PHY driver selection in Kconfig.
A later patch will enable USB support in the H616 boards' defconfigs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The H616 USB PHY is some kind of special snowflake: Only port2 works out
of the box, but all other ports need some help from this port2 to work
correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be
enabled, and the SIDDQ bit in the PMU PHY control register needs to be
cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be
ungated. Don't ask ....
Follow the respective Linux patch (b45c6d80325b) and add a quirk bit,
triggering the special sequence as outlined above, for PHYs other than
PHY2: ungate this one special clock, and clear the SIDDQ bit. We also
pick the clock and reset from PHY2 and enable them as well.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.
Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.
Port of Linux patch 8dd256bae653.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.
Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.
Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
The Allwinner F1C100s implements a single USB PHY, connected to its MUSB
OTG controller. The USB PHY is of the simpler, older type (like the A10),
the only real difference is that it's indeed only one PHY.
Add a struct describing those F1C100s USB PHY properties, and connect it
to the new compatible string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
In its of_xlate() function, the Allwinner USB PHY driver compares the
args_count variable against the number of implemented USB PHYs, although
this is the *number of arguments* to the DT phandle property. Per the DT
binding for this PHY device, this number is always one, so this check
will always fail if the particular SoC implements exactly one USB PHY.
So far this affected only the V3s (which has USB support disabled), but
the F1C100s also sports one PHY only.
Fix that check to compare args_count against exactly 1, and the args[0]
content (requested PHY number) against the number of implemented PHYs.
This fixes USB operation on the Allwinner V3s and allows to enable USB
on the Allwinner F1C100s SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The behaviour of dev_read_addr_size() is surprising as it does not
handle #address-cells and #size-cells but instead hardcodes the values
based on sizeof(fdt_addr_t).
This is different from dev_read_addr_size_index() and
dev_read_addr_size_name() both of which do read the cell sizes from the
device tree.
Since dev_read_addr_size() is only used by a single driver and this
driver is broken when CONFIG_FDT_64BIT does not match the address size
in the device tree, fix the function to behave like all of the other
similarly named functions. Drop the property name argument as the only
caller passes "reg" and this is the expected property name matching the
other similarly named functions.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry
Tested-by: Simon Glass <sjg@chromium.org> # chromebook_bob
of_property_match_string calls of_find_property to search for the
string property.
If the device node does not exist, of_find_property returns NULL, and
of_property_match_string returns -EINVAL, which is correct.
However, if the device node exists, but the property is not found,
of_find_property still returns NULL, but it will place -FDT_ERR_NOTFOUND
in the *lenp variable.
of_property_match_string does not use the lenp parameter, thus this error
case is being lost, and treated as if the node is NULL, and returns
-EINVAL, which is incorrect.
The callers of of_property_match_string treat the error differently if
the return value is -EINVAL or -ENOENT, e.g. in dwc3 driver:
ret = generic_phy_get_by_name(dev, "usb3-phy", &phy);
if (!ret) {
ret = generic_phy_init(&phy);
if (ret)
return ret;
} else if (ret != -ENOENT && ret != -ENODATA) {
debug("could not get phy (err %d)\n", ret);
return ret;
} else {
phy.dev = NULL;
}
So the caller drivers will just consider the property missing if -ENOENT
is returned, versus the case of -EINVAL, which means something else.
To fix this situation, changed the code to call the of_find_property
with the right third argument to catch this error code and treat it
accordingly.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Set MMC clock when reverting to safe bus mode and speed
in case current MMC mode fails. Otherwise, trying out
the other modes may fail as well.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
[hp: fallback to legacy_speed]
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When tuning command (CMD21) fails with command error, call
mmc_send_stop_transmission() to send stop command (CMD12).
Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Add dev_dbg() message in case tuning abort fails
Move tuning opcode check from mmc_abort_tuning()]
Reviewed-by: Peng Fan <peng.fan@nxp.com>
If a tuning command times out, the card could still be processing it,
which will cause problems for recovery. The eMMC specification section
6.6 Data transfer mode (cont’d) claims that CMD12 can be used to stop
CMD21:
"
The relationship between the various data transfer modes is summarized (see Figure 27):
- All data read commands can be aborted any time by the stop command (CMD12).
The data transfer will terminate and the Device will return to the Transfer State.
The read commands are: ... send tuning block (CMD21) ....
"
Add a function that does that.
Based on Linux commit [1] and [2].
[1] e711f0309109 ("mmc: mmc: Introduce mmc_abort_tuning()")
[2] 21adc2e45f4e ("mmc: Improve function name when aborting a tuning
cmd")
Reviewed-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update commit message, quote relevant part of the specification.
Rename to mmc_send_stop_transmission().
Remove tuning opcode check, this is controller driver specific.
Deduplicate part of mmc_read_blocks() using this function.]
Reviewed-by: Peng Fan <peng.fan@nxp.com>
For MMC/eMMC, the MMC_CMD_STOP_TRANSMISSION response is R1 for read
transfers and R1b for write transfers per JEDEC Standard No. 84-B51
Page 126 . The response is R1b unconditionally per Physical Layer
Simplified Specification Version 9.00.
Correct the response type and add a comment about it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When CONFIG_CMD_MMC and CONFIG_MMC are disabled, still some compilation
errors are seen as below due to unresolved symbols.
drivers/dfu/dfu_mmc.o: in function `mmc_block_op':
drivers/dfu/dfu_mmc.c:32: undefined reference to `find_mmc_device'
drivers/dfu/dfu_mmc.c:54: undefined reference to `mmc_get_blk_desc'
drivers/dfu/dfu_mmc.c:67: undefined reference to `mmc_get_blk_desc'
drivers/dfu/dfu_mmc.c:70: undefined reference to `mmc_get_blk_desc'
drivers/dfu/dfu_mmc.o: in function `dfu_fill_entity_mmc':
drivers/dfu/dfu_mmc.c:369: undefined reference to `find_mmc_device'
drivers/dfu/dfu_mmc.c:376: undefined reference to `mmc_init'
drivers/dfu/dfu_mmc.c:403: undefined reference to `mmc_get_blk_desc'
gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-ld.bfd: line 4:
31661 Segmentation fault (core dumped) $CC --sysroot=$LIBC
--no-warn-rwx-segment "$@"
Makefile:1760: recipe for target 'u-boot' failed
make: *** [u-boot] Error 139
make: *** Deleting file 'u-boot'
Add dependency of CONFIG_MMC for CONFIG_DFU_MMC config to fix the errors.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Bochs is convenient with QEMU on x86 since it does not require a video
BIOS. Add a driver for it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Move from using debug() to log_debug() so that we don't have to use the
__func__ parameter and can access other logging features.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The ACPI tables are special in that they are passed to EFI as a separate
piece, independent of other tables.
Also they can be spread over two areas of memory, e.g. with QEMU we end
up with tables kept in high memory as well.
Add new global_data fields to hold this information and update the bdinfo
command to show the table areas.
Move the rom_table_end variable into the loop that uses it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In some cases the video ROM may have been enabled previously, such as by
a previous firmware stage. Use the correct address in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A hex value is expected for the VGA mode. Add a 0x prefix, since the #
construct is not supported in SPL. We don't want to add it, due to
code-size constraints.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When video is set up in SPL, U-Boot proper needs to use the correct
parameters so it can write to the display.
Put these in a bloblist so they are available to U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e.
SPL. Add a Kconfig option for this, adjust the Makefile rules and use
CONFIG_IS_ENABLED() where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When running the ROM the code is not very helpful when something goes
wrong. Add a little more debugging and some logging of return values to
improve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow PCI autoconfig to be handled in SPL, so that we can set it up
correctly for boards which need to do this before U-Boot proper. This
includes qemu-x64_64 which needs to set up the video device while in
32-bit mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When scanning fails it is useful to be able to decode what went wrong. Add
some debugging for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Once the ACPI tables have been set up, record their address so that it is
possible to list them with 'acpi list'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is always zero in the source tree, so drop it.
While we are here, add a comment to _X86EMU_env since the symbol is
actually defined twice, which can cause confusion when building.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Kconfig for this is currently inside a particular board. Move it into
the correct place and allow use in SPL, so that video can be used there
if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It seems better to call this a 'bootdev' since this is name used in the
documentation. The older 'Bootdevice' name is no-longer used and may cause
confusion with the 'bootdevice' environment variable.
Update throughout to use bootdev.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of using the hard-coded value of 0x1f, use 'TASK_TAG'
macro instead to construct the ucd_req_ptr->header.dword_0
This is in sync with what the Linux UFS driver does, i.e.
set the byte0 equal to TASK_TAG (see [1]).
Setting it to a fixed value of 0x1f is wrong as we define
TASK_TAG as 0 inside u-boot ufs framework. So, instead we
should use the macro value directly.
[1]. https://github.com/torvalds/linux/blob/master/drivers/ufs/core/ufshcd.c#L2705
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
This driver considers that a node with an empty label is the top.
But the led class has changed, if a label is not provided for a led,
the label is filed with the node name. So we update this driver
to use a wrapper to manage the top led node.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
The different CPSW sub-system Ethernet ports have different PHY mode
control registers. In order to allow the modes to get configured
independently only the register for the port in question must be
accessed, otherwise we would just be re-configuring the mode for port 1,
while leaving all others at their power-on defaults. Fix this issue by
adding a port-number based offset to the mode control base register
address based on the fact that the control registers for the different
ports are spaced exactly 0x4 bytes apart.
Fixes: 9d0dca1199 ("net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
scmi_to_linux_errno() is set to return an appropriate errno
which corresponds to a given SCMI status code.
But the current implementation always returns the same value.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Without CONFIG_CLK, the build fails with the following message:
LD u-boot
aarch64-none-linux-gnu-ld.bfd: drivers/firmware/scmi/scmi_agent-uclass.o: \
in function `scmi_bind_protocols':
.../drivers/firmware/scmi/scmi_agent-uclass.c:79: undefined reference to \
`_u_boot_list_2_driver_2_scmi_clock'
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
This was brought in in 2016 and a number of changes have been made since
then. There does not seem to be much change in functionality, but it is
a good idea to update from time to time.
Bring in the latest version:
5736b15 ("re-add perlin noise again")
Add a few necessary functions, with dummies in some cases. Update the tests
as there are subtle changes in rendering, perhaps not for the better.
Signed-off-by: Simon Glass <sjg@chromium.org>
For laying out text accurately it is necessary to know the width and
height of the text. Add a measure() method to the console API, so this
can be supported.
Add an implementation for truetype and a base implementation for the
normal console.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is sometimes necessary to highlight some text in a different colour.
Add an easy way to do this and then restore the original console colours.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present livetree can only be used for the control FDT. It is useful
to be able to use the ofnode API for other FDTs, e.g. those used by
the upcoming configuration editor.
We already have most of the support present, and tests can be marked with
the UT_TESTF_OTHER_FDT flag to use another FDT as a special case. But
with this change, the functionality becomes more generally available.
Plumb in the require support.
Signed-off-by: Simon Glass <sjg@chromium.org>
The putc_xy() method is supposed to return the amount of space used. The
existing implementation erroneously adds the previous sub-pixel position
to the returned value. This spaces out the characters very slightly more
than it should. It is seldom noticeable but it does make accurate
measurement of the text impossible.
Fix this minor but long-standing bug.
Fixes: a29b012037 ("video: Add a console driver that uses TrueType fonts")
Signed-off-by: Simon Glass <sjg@chromium.org>
This is useful when the background colour must be written before text
is updated, to avoid strange display artifacts.
Add a function for this, using the existing code from the truetype
console.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there are various restrictions on the use of livetree:
- It is only available once the tree is unflattened, i.e. after relocation
- It is designed to be used with the control FDT
- It can (in principle) be used with other FDTs, but only if they are
unflattened first; this is not supported
Add a few checks to make sure that any tree that is created is actually
valid. Otherwise it can be confusing when nodes and properties cannot
actually be accessed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Devices do not necessarily have nodes attached to them, since they can be
created from platdata. In SPL a devicetree may in fact not exist at all.
Check the node before using it. This avoids failure when OF_CHECKS is
enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 5fc7cf8c8e ("gpio: add gpio-hog support")
Reviewed-by: Heiko Schocher <hs@denx.de>
Use proper register base and access method to access GRF registers.
GRF registers start at a completely different base, and need special
access method, that sets the change mask in the 16 MSBs.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
If phy is not defined in DT (eg. on rk3399), generic_phy_get_by_name
will return -ENODATA. Handle that case correctly.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
pllref_clk is unused after being retrieved. fin needs to be set
to dsi->ref clock's rate for the following calculation to work.
Otherwise fin is undefined, and calculation return bogus number
based on undefined variable.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
&priv->phy is always true. Compiler warns about this loudly.
Use a propper check for phy device allocation. Without this fix
using this driver with SoC that doesn't use external phy (eg. RK3399)
doesn't work.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
These must be read from timings->flags, like other DSI HOST drivers do.
And they must not be inverted either. Low means low.
Without this fix, panel drivers that set *SYNC_LOW produce corrupted
output on screen (shifted horizontally and vertically by back porch
distance).
Signed-off-by: Ondrej Jirman <megi@xff.cz>
The intermediate value could overflow for large periods and levels.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The driver is for panels based on the Himax HX8394 controller, such as the
HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface.
This panel is used in Pinephone Pro.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Anatolij Gustschin <agust@denx.de>
Some callers expect to call this with NULL font name to select the
default font (eg. boot/scene.c). Without handling the NULL condition
U-Boot crashes instead of displaying a bootflow GUI menu.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Anatolij Gustschin <agust@denx.de>
There are some newer clocks added to the kernel recently,
so to fix prepare for resycing the device trees, update
the clock list. Since there are some minor changes to
the USB clocks, update which USB clocks are enabled
to match with the upstream kernel as well.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Extend the RX timeout value to 10s, because when authentication is failed
the ELE needs long time (>2s for 28M image) to return the result. Print
rx wait info per 1s.
Also correct TX and RX status registers in debug.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
If cs gpio is requested with ACTIVE_HIGH flag, it will
be pulled low(i.e. active). This is not what we expected.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
XTX changed full company name from "XTX Technology (Shenzhen) Limited
to "XTX Technology Limited" since 2020,So remove "(Shenzhen)".
Signed-off-by: Bruce Suen <bruce_suen@163.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
According to Documentation/devicetree/bindings/spi/spi-gpio.yaml
from Linux, the recommended spio-gpio properties are:
sck-gpios, miso-gpios and mosi-gpios.
gpio-sck, gpio-mosi and gpio-miso are considered deprecated.
Currently, U-Boot only supports the deprecated properties.
Allow the soft_spi driver to support both the new and old properties.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Current code expects that SPI_TX_BYTE is single bit mode
but it is wrong. It indicates byte program mode,
not single bit mode.
If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
the default transfer bus width is single bit.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC
for common features and IP blocks. Use this config instead of each chip
config as the Kconfig dependency for Broadcom HSSPI driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for an optional external chip-select gpio.
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Remove the platform data header because its content is only used by the
driver.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Rename the flush function into pl022_spi_flush to avoid conflicting
types with previous declaration of the function in stdio.h header.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Align the compatible property with the kernel device tree binding [1]
by removing the '-spi' suffix.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml
Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and
a generic local bus controller (Device Bus Controller) that share common
pins.
With a board design that incorporates both a NAND flash and uses
the Device Bus (in our case for an SRAM) accessing the Device Bus device
fails unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
HW_UARTDBG_FR) has been used to assess if there is still data pending
to be sent via UART.
This approach is problematic, as it may happen that serial is in the
middle of transmission (so the TX FIFO is NOT full anymore) and this
test returns true infinitely. As a result, for example in _serial_flush()
DM serial function we are locked in endless while().
The fix here is to test explicitly if the TX FIFO is empty.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Before this change, building this driver for SPL with enabled SPL_DM_SERIAL
was problematic, as '-Wunused-const-variable=' warning was visible.
Now, the code is only considered when u-boot proper is build.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In the imx8m power domain kernel driver, there is an extra udelay(5)
prior to requesting the domain to power up:
https://github.com/torvalds/linux/blob/v6.3/drivers/soc/imx/gpcv2.c#L347-L375
Haven't observed any issues due to the lack of this delay in U-Boot yet,
but better to align it with the kernel driver implementation.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
DM_GPIO depends on GPIO to be enabled but select will cause that DM_GPIO is
selected without GPIO which ends up in compilation error:
undefined reference to `dm_gpio_set_value'
undefined reference to `dm_gpio_get_value'
undefined reference to `dm_gpio_free'
undefined reference to `gpio_request_by_name'
Signed-off-by: Michal Simek <michal.simek@amd.com>
[trini: Fix configs which had relied on these select's]
Signed-off-by: Tom Rini <trini@konsulko.com>
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The regulator core can return different codes which are not considered
a real error for this function.
Return success in such cases.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Simplify the subsystem by renaming `dev_pdata` to just `plat`.
No functional change, just trivial renaming.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Some devices share a regulator supply, when the first one will request
regulator disable, the second device will have it's supply cut off before
graciously shutting down. Hence there will be timeouts and other failed
operations.
Implement a reference counter mechanism similar with what is done in
Linux, to keep track of enable and disable requests, and only disable the
regulator when the last of the consumers has requested shutdown.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
GPIOD_ACTIVE_LOW is not enough to configure a GPIO as an output, we need
GPIOD_IS_OUT as well.
Fixes: b252d79b09 ("usb: dwc3: Add support to reset usb ULPI phy")
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Using CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y and CONFIG_OF_LIVE=y triggers
a Data Abort exception from unaligned memory access when the pinctrl
driver iterate node properties, e.g. for UART2 on RK3568.
setting mux of GPIO0-24 to 1
setting mux of GPIO0-24 to 1
"Synchronous Abort" handler, esr 0x96000021
elr: 000000000000e554 lr : 000000000000e54c
x 0: 0000000000000a5c x 1: 0000000000000a5c
x 2: 0000000000000007 x 3: 0000000000000065
x 4: 0000000000000007 x 5: 0000000000022d4e
x 6: 0000000000000a7c x 7: 00000000000227a4
x 8: 0000000000021cf0 x 9: 0000000000000a7c
x10: 0000000000021cf0 x11: 0000000000021cf0
x12: 00000000003fda1c x13: 0000000000000007
x14: 00000000003fd9ec x15: 000000000001c0ff
x16: 0000000007000000 x17: 00000000fdccd028
x18: 00000000003fde20 x19: 0000000000000018
x20: 0000000000020670 x21: 0000000000000000
x22: 00000000003fdb00 x23: 00000000003fef90
x24: 0000000000020688 x25: 0000000000000000
x26: 0000000000000001 x27: 00000000003ffc50
x28: 0000000000000000 x29: 00000000003fda60
Code: b94083e1 97ffd508 93407c01 37f81260 (f9401038)
Resetting CPU ...
Fix this by replacing the loop to access node properties with use of
ofnode_for_each_prop instead of the current ifdef.
Also continue to next prop instead of aborting at first sign of an
unknown property.
This fixes the Data Abort exception and also pinconf of e.g. pull and
drive in SPL, e.g. for UART2 on RK3568.
setting mux of GPIO0-24 to 1
setting mux of GPIO0-24 to 1
setting pull of GPIO0-24 to 5
setting mux of GPIO0-25 to 1
setting mux of GPIO0-25 to 1
setting pull of GPIO0-25 to 5
Fixes: e7ae4cf27a ("pinctrl: rockchip: Add common rockchip pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The support for #address-cells=2 has a loophole: if the reg is actually 0,
but the #address-cells is actually 1, like in such case below:
syscon {
#address-cells = <1>;
phy {
reg = <0 0x10>;
};
};
then the second u32 of the 'reg' is the size, not the address.
The code should check for the parent's #address-cells value, and not
assume that if the first u32 is 0, then the #address-cells is 2, and the
reg property is something like
reg = <0 0xff00 0x10>;
Fixed this by looking for the #address-cells value and retrieving the
reg address only if this is ==2.
To avoid breaking anything I also kept the check `if reg==0` as some DT's
may have a wrong #address-cells as parent and even if this commit is
correct, it might break the existing wrong device-trees.
Fixes: d538efb9ad ("phy: rockchip: inno-usb2: Add support #address_cells = 2")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch adds Power controller driver support for Amlogic
A1 family using secure monitor calls. The power domains register
only can access in secure world.
Signed-off-by: Alexey Romanov <avromanov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230531093156.29240-4-avromanov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Based on Linux kernel commit:
dabad1ff85611 (pinctrl: meson: add pinctrl driver support for Meson-A1 SoC)
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230505125639.3605-5-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Fix the write to the HPRT register which treat W1C fields
as if they were mere RW. This leads to unintended clearing of such fields
This bug was found during the testing on Simics model. Referring to
specification DesignWare Cores USB 2.0 Hi-Speed On-The-Go (OTG)
Databook (3.30a)"5.3.4.8 Host Port Control and Status Register (HPRT)", the
HPRT.PrtPwr is cleared by this mistake. In the Linux driver (contrary to
U-Boot), HPRT is always read using dwc2_read_hprt0 helper function which
clears W1C bits. So after write back those bits are zeroes.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
At first SPI transfers, multiple chip selects can be
enabled simultaneously. This is due to chip select
polarity, which is not properly initialized for all
channels. This patch fixes the issue.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
In lan78xx_read_otp() we want to know if sig is LAN78XX_OTP_INDICATOR_1
or LAN78XX_OTP_INDICATOR_2. In the case of matching the first one we
set offset to itself, and clang warns about this. Rework the logic so
that if sig is the second indicator we adjust the offset as today and if
it does not match the first indicator we return -EINVAL
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP
for SPL which is required to auto configure the PCIe devices.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Add a generic API to support loading of SPL payload from any supported
filesystem on a given partition of a block device.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Move header to include to allow external code
to get the internal bdev structures to access
block device operations.
as at it, just add the UCLASS_NVMXIP string
so we get the correct output in partitions
listing.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
To avoid spurious chars, BRR register must only be written when
USART is disabled.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
In case there is still chars from previous bootstage to transmit, wait
for TC (Transmission Complete) bit to be set which ensure that the last
data written in the USART_TDR has been transmitted out of the shift
register.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The '_' character is discouraged in the node name, this patch adds the
new prefix of regulator subnode, with the '-' character, in STM32MP1 driver
to support the new naming rule in Linux kernel device trees.
It is a preliminary patch before Linux device tree synchronization
for STMicroelectronics boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
With MTD support in driver model, the direct call of mtdparts_init
should be avoided and replaced by mtd_probe_devices.
With the modificaton when MTDIDS/MTDPARTS are empty the OF fallback
with partition describe in device tree is correctly performed,
introduced by commit dc339bf784 ("mtd: add support for parsing
partitions defined in OF").
With this patch the dependency with CONFIG_CMD_MTDPARTS is removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This patch targets the last remaining commands left to sync to their
latest form - mainly the mc_get_version() API.
Besides this, remove any macro which is now of no help.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path IO APIs to their latest form, this means the layout
of each command is created based on structures which clearly describe
the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path Soft Parser APIs to their latest form, this
means the layout of each command is created based on structures which
clearly describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path Network Interface APIs to their latest form, this
means the layout of each command is created based on structures which
clearly describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Resource Container APIs to their latest form, this means
the layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path MAC APIs to their latest form, this means the
layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sync the Data Path Buffer Pool APIs to their latest form, this means the
layout of each command is created based on structures which clearly
describe the endianness of each field rather than some macros.
The command version is kept in place, meaning that the minimum MC
version accepted is not changed in any way.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There are multiple MC APIs which were added years ago but they are not
used at all in the u-boot source code. Remove all these APIs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The rtl8169 driver uses calls to dm_pci_bus_to_phys,
which are compiled under CONFIG_PCI.
Without CONFIG_PCI, this happens:
drivers/net/rtl8169.o: in function `rtl_recv_common':
drivers/net/rtl8169.c:555: undefined reference to `dm_pci_bus_to_phys'
It is only natural that this driver depends on CONFIG_PCI then.
The device does not work connected in another way anyway, and the driver
does not assume anything else at this moment.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Export the already existing DPNI and DPMAC counters through the newly
added callbacks.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The ldpaa_eth driver already had a DPMAC statistics dump, this patch
extends the list of stats and adds a bit more structure to the code.
For a bit more context, the DPAA2 u-boot software architecture uses a
default network interface object - a DPNI - which, at runtime, will get
connected to the currently used DPMAC object.
Each time the .stop() eth callback is called, the DPMAC is destroyed
thus any previous counters will get lost.
As a preparation for the next patches, we add a software kept set of
DPMAC counters which will get updated before each destroy operation
takes place.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The ldpaa_eth driver already had a DPNI statistics dump, this patch
extends the list of stats and adds a bit more structure to the code.
For a bit more context, the DPAA2 u-boot software architecture uses a
default network interface object - a DPNI - which, at runtime, will get
connected to the currently used DPMAC object.
Each time the .stop() eth callback is called, the DPNI is reset to its
original state, including its counters.
As a preparation for the next patches, we add a software kept set of
DPNI counters which will get updated before each reset operation takes
place.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In order to simplify code, dpni_statistics can be written as a union.
Using the raw accessors we can just loop through all the statistics from
a page without trying to access each an every one independently.
Make this change to a union.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver source is partly copied from
the Linux PCI driver and modified to enable usage in U-Boot (e.g.
simplified and interrupt support removed).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Pali Rohár <pali@kernel.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort
Subsystem. It includes a buffer manager, blender, an audio mixer and a
DisplayPort source controller (transmitter). The DisplayPort controller can
source data from memory (non-live input) or the stream (live input). The
DisplayPort controller is responsible for managing the link and physical
layer functionality. The controller packs audio/video data into transfer
units and sends them over the main link. The link rate and lane counts can
be selected based on the application bandwidth requirements. The
DisplayPort pipeline consists of the DisplayPort direct memory access (DMA)
for fetching data from memory. The DisplayPort DMA controller (DPDMA)
supports up to six input channels as non-live input.
This driver supports the DisplayPort Subsystem and implements
1)640x480 resolution
2)RGBA8888 32bpp format
3)DPDMA channel 3 for Graphics
4)Non-live input
5)Fixed 5.4G link rate
6)Tested on ZCU102 board
There will be additional work to configure GT lines based on DT, higher
resolutions, support for more compressed video formats, spliting code to
more files, add support for EDID, audio support, using clock framework for
all clocks and in general code clean up.
Codevelop-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5c1567b63d0280dacc7efba2998857c399c25358.1684312924.git.michal.simek@amd.com
Add support for RGBA8888 32bpp format where pixels are picked in
32-bit integers, where the colors are stored in memory such that
R is at lowest address, G after that, B after that, and A last.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aa1de54b7d4ff46df6858f76d52634e0c5c71a4a.1684312924.git.michal.simek@amd.com
Store the driver data in the data section to make the data usable before
relocation. Additionally mark the driver data static to restrict the
access.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20230523124215.30915-5-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Move the permission to change a config object message from
zynqmp_pmufw_load_config_object function to zynqmp_pmufw_node function
to simplify the code and check the permission only if required.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20230523124215.30915-4-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Remove the redundant child device bind from the driver bind function and
rely on the post_bind of the class which calls the same function.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20230523124215.30915-2-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Return a common -EACCES error value instead of a positive private error
value XST_PM_NO_ACCESS (2002) in zynqmp_pmufw_load_config_object
function if the config object is not loadable to simplify the error
checking.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20230523124215.30915-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Add fallthrough statement in switch case to fix the sparse warning.
In function 'zynqmp_clk_get_rate': warning: this statement may
fall through [-Wimplicit-fallthrough=]
Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20230519113816.22083-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
In case RX error occurs, and the RD_RFE bit is set, the descriptor
is never returned back to the queue. Make sh_eth_recv_start return
zero length in this case so that the descriptor can be released
and pushed back to the list. Also return the more appropriate
-EAGAIN instead of -EINVAL if the descriptor is not ready yet.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
U-Boot writes to RX packets when constructing replies.
This can cause stale cached data to be written to RX
buffer while we're receiving a packet. This causes RX
packet corruption because we invalidate the cache right
before processing the packet. Invalidate packet buffer
cache when preparing RX descriptor as well. This seems
to fix RX packet drops with high RX traffic.
While at it flush the descriptors right before enabling
RX/TX in sh_eth_tx_desc_init/sh_eth_rx_desc_init callbacks
when they are ready instead of flushing after allocation.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The common code is now capable of handling reset GPIO associated
with PHY. Drop the local ad-hoc code in favor of common code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The common code is now capable of handling reset GPIO associated
with PHY. Drop the local ad-hoc code in favor of common code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
These two properties are used by various DTs in place of
current reset-assert-us/reset-deassert-us , handle both .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
In case a new PHY is created and DM_ETH_PHY is enabled, bind a
generic PHY driver from ETH_PHY uclass to the PHY to have a
matching DM representation of that PHY.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The phy_connect_dev() is legacy API, now that there are no users,
make it internal to phy.c and unpublish it from headers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use new U-Boot phy_connect() API which also supports fixed PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use new U-Boot phy_connect() API which also supports fixed PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use new U-Boot phy_connect() API which also supports fixed PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use new U-Boot phy_connect() API which also supports fixed PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use new U-Boot phy_connect() API which also supports fixed PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Use new U-Boot phy_connect() API which also supports fixed PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The eth_phy_reset() is not used outside of this file, staticize it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This patch adds 4-byte address mode support. Because traditional access
based on FIFO/shift register, it's complex to specify information like
opcode, address length, dummy bytes etc to flash. Replace the traditional
access by spi-mem layer which is essential to make 4-byte address mode
support possible.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Support RPC SPI on R-Car Gen4 R8A779F0 S4 and R8A779G0 V4H SoCs.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Squash S4 and V4H patches, fix brackets around STRTIM2]
Enable support for parsing and auto discovery of parameters for
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
tables as per JESD216 standard.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Make SFDP the default unconditionally
Move strobe delay setting code into extra function and reflect the latest
setting in datasheet (R-Car Gen3 v2.20, R-Car V3U v0.50).
i.e. STRTIM[2:0] should be set to 110 (RCar M3-W) or 111 (Other products)
This is also a preparation for new R-Car Gen4 SoC which has 4-bits STRTIM
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Fix for RZ/A1
In the FWU Multi Bank Update feature, the information about the
updatable images is stored as part of the metadata, on a separate
region. Add a driver for reading from and writing to the metadata
when the updatable images and the metadata are stored on a raw
MTD region.
The code is divided into core under drivers/fwu-mdata/ and some helper
functions clubbed together under lib/fwu_updates/
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
The common code can now read, verify and fix meta-data copies
while exposing one consistent structure to users.
Only the .read_mdata() and .write_mdata() callbacks of fwu_mdata_ops
are needed. Get rid of .get_mdata() .update_mdata() .get_mdata_part_num()
.read_mdata_partition() and .write_mdata_partition() and also the
corresponding wrapper functions.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Instead of each i/f having to implement their own meta-data verification
and storage, move the logic in common code. This simplifies the i/f code
much simpler and compact.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Use cached values and avoid parsing and scanning through partitions
everytime for meta-data partitions because they can't change after bootup.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
AVB[01]_{MAGIC,MDC,MDIO,TXCREFCLK} are registered as both
PINMUX_SINGLE(fn) and PINMUX_IPSR_GPSR(fn) in the pinmux_data array.
The latter are correct, hence remove the former.
Without this fix, the Ethernet PHY is not operational on the MDIO bus.
Ported from Linux kernel commit a145c9a8674ac8fbfa1595276e1b6cbfc5139038 .
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Fixes: 741a7370fc3b8b54 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6fd217b71e83ba9a8157513ed671a1fa218b23b6.1674824958.git.geert+renesas@glider.be
---
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: LUU HOAI <hoai.luu.ub@renesas.com>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>
This is a remnant from when the USB controller driver managed
the reset signal itself. A patch from the very end of 2018 changed
this driver to delegate reset (and clock) management to the proper
control unit driver, but left this unused define behind.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This clock doesn't seem needed but appears in a phandle list used by
ehci-generic.c to bulk enable it. The phandle list comes from linux,
where it is needed for suspend/resume to work [1].
My tests give the same results with or without this patch, but Marek
Vasut found it weird to declare an empty clk_ops [2].
So I adapted the code from linux 6.1-rc8 so that it hopefully works
if it ever has some user. For now, without real use, it seems to
at least not give any errors when called.
Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
[2] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Christoph Fritz <chf.fritz@googlemail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
arch/arm/dts/rk3399.dtsi has a node
usb_host0_ehci: usb@fe380000 {
compatible = "generic-ehci";
with clocks:
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
<&u2phy0>;
The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0
has class UCLASS_PHY.
u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
Since clk_get_bulk() only looks for devices with UCLASS_CLK,
it fails with -ENODEV and then ehci_usb_probe() aborts.
The consequence is peripherals connected to a USB 2 port (e.g. in a
Rock Pi 4 the white port, nearer the edge) not being detected.
They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig,
because ohci_usb_probe() does not abort when one clk_get_by_index()
fails, but then they work in USB 1 mode.
rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock
list in:
commit b5d1c57299734f5b54035ef2e61706b83041f20c
Author: William wu <wulf@rock-chips.com>
Date: Wed Dec 21 18:41:05 2016 +0800
arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
[...]
Suspend concerns don't apply to U-Boot, and the problem with U-Boot
failing to probe EHCI doesn't apply to linux, because in linux
rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider
when called by rockchip_usb2phy_probe().
So I can think of a few alternative solutions:
1- Change ehci_usb_probe() to make it more similar to
ohci_usb_probe(), and survive failure to get one clock. Looks a
little harder, and I don't know whether it could break something if
it ignored a clock that was important for something else than
suspend.
2- Change rk3399.dtsi effectively reverting the linux commit
b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi
from linux and seems fragile at the next synchronisation.
3- Change the clock list in rk3399-u-boot.dtsi or somewhere else.
This survives .dts* sync but may survive "too much" and miss some
change from linux that we might want.
4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode.
This would need to be made for all boards using rk3399. In a
simple test reading one file from USB storage it gave 769.5 KiB/s
instead of 20.5 MiB/s with solution 2.
5- Trying to replicate linux and have usb2phy somehow provide a clk,
or have a separate clock device for usb2phy in addition to the phy
device.
This patch tries to implement option 5 as Marek Vasut requested in
December 5th. Options 1 and 3 didn't get through [2][3].
It just registers usb2phy as a clock driver (device_bind_driver()
didn't work but device_bind_driver_to_node() did), without any
specific operations, so that ehci-generic.c finds it and is happy. It
worked in my tests on a Rock Pi 4 B+ (rk3399).
Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
[2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/
[3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/
Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Christoph Fritz <chf.fritz@googlemail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # rk3399, rk3328, rv1126
The `musb_register` function returns some ERR_PTR(...) on failure,
not NULL, so update the check here appropriately.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
According to the dm_serial_ops documentation, pending() should:
> @return number of waiting characters, 0 for none, -ve on error
And:
> It is acceptable to return 1 if an indeterminant number
> of characters is waiting.
With the current implementation, we have:
* FIFO is full -> pending() returns 0
* FIFO is partially used -> pending() returns 1
* FIFO is empty -> pending() returns 1
This is not the same as what the documentation requires.
Moreover, since [1], arm reset now flushes all console devices
(including serial) before the cpu gets reset.
Because of the flawed logic:
=> reset # user calls reset
flush() is called
_serial_flush() is called
ops->pending(dev, false) # never returns false
# board hangs indefinitely without resetting.
Fix it by using AML_UART_TX_EMPTY instead of AML_UART_TX_FULL.
[1] commit c5f4cdb8eb ("console: Use flush() before panic and reset"),
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230606-fix-meson-serial-pending-v1-1-6a54d4a01f76@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
In the current implementation, in case of I2C arbitration lost, a retry is
attempted; the message counter and pointer are reset to the original values
and the I2C xfer process is restart from the beginning.
However the message counter and message pointer are respectively
decremented and incremented by one before attempting any transfer, causing
the 1st transfer not to be actually retried (in case of a single transfer,
nothing is actually retried at all).
This patch fixes this: in case of retry, the 1st transfer is also retried.
Tested on a ZynqMP Kria board, with upstream older u-boot, but the involved
file and underlying logic seem basically the same.
Signed-off-by: Andrea Merello <andrea.merello@iit.it>
Failure can happen when i2c is used without initializing pinctrl properly,
which U-Boot happily allows in SPL. Without this fix, further I2C access would
fail, even after proper pinctrl initialization.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for j721s2-wiz-10g device to use clock-names interface
instead of explicitly defining clock nodes within device tree node.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Compiling with gcc 13 results in an error:
drivers/axi/axi-emul-uclass.c:16:5: warning: conflicting types for
‘axi_sandbox_get_emul’ due to enum/integer mismatch; have
‘int(struct udevice *, ulong, enum axi_size_t, struct udevice **)’
{aka ‘int(struct udevice *, long unsigned int, enum axi_size_t,
struct udevice **)’} [-Wenum-int-mismatch]
16 | int axi_sandbox_get_emul(struct udevice *bus, ulong address,
| ^~~~~~~~~~~~~~~~~~~~
In file included from drivers/axi/axi-emul-uclass.c:14:
./arch/sandbox/include/asm/axi.h:48:5: note: previous declaration of
‘axi_sandbox_get_emul’ with type ‘int(struct udevice *, ulong, uint,
struct udevice **)’ {aka ‘int(struct udevice *, long unsigned int,
unsigned int, struct udevice **)’}
48 | int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length,
| ^~~~~~~~~~~~~~~~~~~~
Adjust the header definition to match the implementation.
Define the size parameter as constant.
Fixes: 9a8bcabd8a ("axi: Add AXI sandbox driver and simple emulator")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The "Message not acknowledged" error message is missing a line feed,
leading to the console log getting garbled and joined together with
whatever the next output is in case this error happens:
"ti_sci system-controller@44043000: Message not acknowledgedAuthentication failed!"
Fix ths by adding the missing linefeed character.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Buffers created through DEFINE_(CACHE_)ALIGN_BUFFER are actually
pointers to the real underlying buffer. Using sizeof(...) is
not appropriate in this case.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
As per [1], dfu_alt_info is mentioned to be as semicolon separated
string of information on each alternate and the parsing logic in
the dfu.c is based on this.
Typically, the dfu_alt_info_* is defined in .h files as preprocessor
macros with 'alt' info separated by semicolon.
But when dfu_alt_info_* is added in the environment files(.env)
the script at "scripts/env2string.awk" converts a newline to space.
Thus adding a space character after semicolon. This results in
incorrect parsing in dfu.c which is based on the information that
'alt' info are only semicolon separated.
One option is to add dfu_alt_info_* variable in .env in single line.
But there is possiblity for it to exceed the line length limit.
So update the parsing logic to remove leading space characters
before adding to the dfu list.
[1]: https://u-boot.readthedocs.io/en/latest/usage/dfu.html
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
This fixes an error with trying to link against do_bootm() when
CONFIG_CMD_BOOTM is disabled.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
It seems like the header inclusion guard for the Exynos pinctrl header
was misspelled.
Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.
Signed-off-by: Tom Rini <trini@konsulko.com>
The PCIe controller on the M2 Pro/Max is different from the one
found on earlier Apple SoCs. Some registers moved and te meaning
of the bits in some other registers changed. But they are still
similar enough to handle both controllers in the same driver.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Add trivial driver for the MXS AUART IP. This is the other UART IP
present in i.MX23 and i.MX28, used to drive the non-DUART ports.
Signed-off-by: Marek Vasut <marex@denx.de>
The rank setting flow should be updated to support multi
fsp config.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add 625M bypass clock that may be used DRAM 625M
bypass mode support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
change the ddr saved info to the last 16KB of the OCRAM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
There will be build error if CONFIG_SYSRESET is enabled, so guard
the reset_cpu with condition check here
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Move imx8 sci header file to include/firmware/imx, then we could
use build macro to reuse some i.MX8 drivers for i.MX9, such as
drivers/cpu/imx8_cpu.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
The TMU used on iMX93 is IP revision 2.1 which is different with previous
revision used on iMX8MQ. So add a new FLAG V4 for this revision to
distinguish the operations.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Stop polluting the architecture directory with driver specific code,
move it into driver where it should be. Split the code slightly so
the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout
and programming are in their separate functions, and called in case
of matching SoC.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Use dev_(dev, ...) for all printing and debug logging, since this
already includes the device name. Drop device name where duplicate.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Use the same prop as linux to control the use of fifo or dma mode. Also
add a u-boot,spl-sfc-no-dma prop to control the same in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:
## Checking hash(es) for Image atf-2 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-2' image node
spl_load_simple_fit: can't load image loadables index 1 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Add a device tree property, u-boot,spl-fifo-mode, to control when the
rockchip_sdhci driver should disable the use of DMA and fallback on PIO
mode. Same device tree property is used by the rockchip_dw_mmc driver.
In commit 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") the DMA mode was disabled using a CONFIG
option on RK3588. Revert that and instead disable DMA using the device
tree property for all RK3588 boards, also apply similar workaround for
all RK3399 boards.
Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
The workaround to limit number of blocks to read in a single command
should only be applied to RK3568 and RK3588. Change to be more strict
when to apply the workaround.
Fixes: 2cc6cde647 ("mmc: rockchip_sdhci: Limit number of blocks read in a single command")
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
Add support for rk3588 phy variant.
The PHY clock is fixed at 100MHz.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[kever.yang@rock-chips.com: update pcie pll parameters]
Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[eugen.hristev@collabora.com: squashed, tidy up]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Some variants of the PHY have more than just one reset.
To cover all cases, request the rests in bulk rather than just
the reset at index 0.
Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for max_link_speed specified in the PCI DT binding.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[eugen.hristev@collabora.com: port to latest API, set default correctly,
align to 80 chars]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: switch to dev_read_u32_default]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The current DT bindings for the rk3588 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This approach has been implemented already in Linux, by commit :
f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
Hence, implement a similar approach using the lookup table, and adapt
the existing reset driver to work with SoCs using lookup table.
The file rst-rk3588.c has been copied as much as possible from Linux.
Adapt the clk rk3588 driver as well to bind the reset driver with the
lookup table.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fixes: 226fce6108 ("phy: Track power-on and init counts in uclass")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Add initial support for the rk3588 PHY variant.
The lookup for the host-port reg inside the struct now does a do {} while()
instead of a while() {} in order to allow a first check for reg == 0.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Co-developed-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
phy-supply is now handled at uclass level. Remove it from the drivers that
implement it at the driver level.
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Some phys require a phy-supply property that is a phandle to a regulator
that needs to be enabled for phy operations.
Implement basic supply lookup, enable and disabling, if DM_REGULATOR is
available.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se:
use regulator_set_enable_if_allowed and disable if power_on ops fails]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Define SPL_USB_ETH_RNDIS symbol to make it possible to select USB
gadget ethernet support in SPL and U-Boot separately in Kconfig .
Make use of the new symbols in gadget Makefile and move the rndis.o
just below the now merged USB_ETHER symbol in Makefile.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
To avoid piling up all the various Kconfig symbols in one place, i.e.
common/spl/Kconfig, move the USB Kconfig symbols into drivers/usb/ .
This commit moves SPL_USB_GADGET and related symbols. Fix typo and
rename SPL_USB_GADGET to "USB Gadget Support in SPL" .
Update the gadget Makefile to match the symbol changes.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
To avoid piling up all the various Kconfig symbols in one place, i.e.
common/spl/Kconfig, move the USB Kconfig symbols into drivers/usb/ .
This commit moves SPL_USB_STORAGE and matching SYS_USB_FAT_BOOT_PARTITION .
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
To avoid piling up all the various Kconfig symbols in one place, i.e.
common/spl/Kconfig, move the USB Kconfig symbols into drivers/usb/ .
This commit moves SPL_USB_HOST and updates help text of both USB_HOST
and SPL_USB_HOST .
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Merge in a long-standing fix for some exynos platforms, correct a
Kconfig description, fix some env issues, fix an issue in
devfdt_get_addr_size_index_ptr and look for "panel-timings" not
"panel-timing" per upstream binding.
For the devfdt_get_addr_size_index_ptr() function use
map_sysmem() function as cast for the return for use in
sandbox.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
In case where a single timing resolution is implemented in the
device-tree, the property is named "panel-timing", as specify
in Linux kernel binding file:
Documentation/devicetree/bindings/display/panel/panel-common.yaml
# Display Timings
panel-timing:
description:
Most display panels are restricted to a single resolution and
require specific display timings. The panel-timing subnode expresses those
timings.
$ref: panel-timing.yaml#
display-timings:
description:
Some display panels support several resolutions with different timings.
The display-timings bindings supports specifying several timings and
optionally specifying which is the native mode.
$ref: display-timings.yaml#
Fixes: 0347cc7732 ("drivers: core: ofnode: Add panel timing decode.")
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This reverts commit a034ec06ff.
Commit 4a3ea75de4 ("Revert "mmc: sdhci: set to INT_DATA_END when
there are data"") reverted the alternative fix that was added for
Exynos 4 devices, causing an error when trying to boot from an sdcard:
<...>
Loading Environment from MMC... sdhci_send_command: Timeout for status update!
mmc fail to send stop cmd
<...>
Re-add the quirk to allow booting from sdcards again.
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Make it clear that this is the SPL option to avoid potential confusion
when the description for CONFIG_SPL_VIDEO is the same as that for
CONFIG_VIDEO.
Signed-off-by: John Keeping <john@metanate.com>
flash_get_size() will get the flash size from the device itself and go
through all erase regions to read protection status. However, the device
mappable region (eg: devicetree reg property) might be lower than the
device full size which means that the above cycle will result in a data
bus exception. This change fixes it by reading the 'addr_size' during
probe() and also use that as one possible upper limit.
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
This reverts commit e097847286. The
commit wrongly divides the dummy bytes by dummy bus width to calculate
the dummy bytes. The framework already converts the dummy cycles to the
number of bytes and the controller use the SPI flash command to
determine the dummy cycles via the address width.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230427065355.7413-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This causes crashes on some boards, e.g. rockpro64. In any case, we
should not do it.
Check the usb_started flag to avoid this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Tom Rini <trini@konsulko.com>
This should be declared in a header file so that type-checking works
correctly.
Add a single declaration to usb.h and remove the others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siemsen@linaro.org/
Notable difference: this version avoids allocating a 'struct clk'
for each clock source, as this is problematic before relocation.
Instead, it uses the same approach as existing Renesas R-Car Gen2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car
clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3.
This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing
recursion into the drivers/clk/reneasas directory, without bringing in
the R-Car support code. The support code contains platform specific
access (TMU_BASE) which is not needed on other Renesas devices such as
RZ/N1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Probing LPC can cause PCI enumeration to take place, which significantly
increases pre-relocation memory usage. Also, LPC is somtimes enabled
directly by SPL.
Adjust the logic to probe the LPC only after relocation. This allows
chromebook_link64 to start up without a much larger
CONFIG_SYS_MALLOC_F_LEN value.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The 'tiny' SPI nor functions have the same name as their big brothers,
which can be confusing. Use different names so it is clear which
version is in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero
error. Check for this and return a proper error instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.
With this, chromebook_link64 makes it through SPL.
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot sets up devices ready for use, but coreboot does not. Enable this
so that NVMe works OK from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot is the second-stage bootloader, PCI is already set up. We
cannot read the regions from the device tree. There is no point anyway,
since PCI devices have already been allocated according to the regions
and it is not safe for U-Boot to make any changes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fixes: f2ebaaa9f3 ("pci: Handle failed calloc in decode_regions()")
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
When coreboot does not pass a UART in its sysinfo struct, there is no
easy way to find it out.
Since coreboot does not actually init the serial device when serial is
disabled, it is not possible to make it add this information to the
sysinfo table.
Add a way to obtain this information from the DBG2 ACPI table, which is
normally set up by coreboot.
For now this only supports a memory-mapped 16550-style UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We have several Kconfig options for ACPI, but all relate to specific
functions, such as generating tables and AML code.
Add a new option which controls including basic ACPI library code,
including the lib/acpi directory. This will allow us to add functions
which are available even if table generation is not supported.
Adjust the command to avoid a build error when ACPIGEN is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If U-Boot is not the first-stage bootloader the keyboard may already be
set up. Make sure to flush any data before trying to reset it. This
avoids a long timeout / hang.
Add some comments and a log category while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
The CRU is being probed with a default set of assigned clocks, which
are not implemented in the driver at all.
Hence, when clk_set_defaults is called, it fails with ENOENT.
This would not be a problem, as the CRU still handles all the required
clocks, and the assigned clocks are default configs which are preprogrammed
or not required for Uboot operations.
However, the rockchip reset driver is being bound by the same DT node
as CRU, as the reset driver has no DT node.
But, when probing the reset node, it will call again the clk_set_defaults
for the CRU node, and failing because of missing those specific clocks
in the rk3588 clock driver.
To avoid this, simply implement a basic set/get that will just return
success and the default corresponding rate for the required assigned clocks.
As those clocks were not supported in Uboot, not required for Uboot
operations, there is no need to do any different kind of initialization.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Fix line spacing aligment in bind function
Fixes: 760188c1aa ("rockchip: reset: support a (common) rockchip reset drivers")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Implement a resource release mechanism on failing probe.
Without this, a strange situation can happen e.g. when init port fails,
or attempting to get the PHY fails, because the gpios have been
requested first, and if the user tries to do 'pci enum' again, the
driver will fail with 'can't find reset gpios' even if the gpios are
there, just because they were blocked by a previous probe attempt.
It is only natural to release the acquired resources if the probe fails,
just for consistency if nothing else.
This way on subsequent probe attempts, the user will get the same error
message, and not something different that doesn't make sense.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so fix some
debug strings with fdt_addr_t to be able to handle both sizes.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_ptr instead of the devfdt_get_addr function in
the various files in the drivers directory that cast to a pointer.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index
function in the various files in the drivers directory that cast to
a pointer.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_index_ptr instead of the dev_read_addr_index function
in the various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use devfdt_get_addr_index_ptr and devfdt_get_addr_size_index_ptr
function in the spi-aspeed-smc.c file. Also fix dev_dbg to be able
to handle both sizes. As we are there also streamline the error
response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Add dev_read_addr_index_ptr function with the
same functionality as dev_read_addr_index,
but instead a return pointer is given.
Use map_sysmem() function as cast for the return.
Make same fix for dev_read_addr_ptr() function.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add devfdt_get_addr_size_index_ptr function with the same
functionality as devfdt_get_addr_size_index, but instead
a return pointer is given.
Suggested-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so convert regmap_init_mem_plat() input to handel both. The
syscon class driver also makes use of the regmap_init_mem_plat()
function, but has no way of knowing the format of the
device-specific platform data. In case of odd reg structures other
then that the syscon class driver assumes the regmap must be
filled in the individual syscon driver before pre-probe.
Also fix the ARRAY_SIZE divider in the syscon class driver.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_spi.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a base variable with uintptr_t size in the
rk_pwm.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expect 64-bit data from the device tree parser,
so use a regs variable with uintptr_t size in the
dw-apb-timer.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip-saradc.c file.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size,
1KB write size and 40 bit ecc support
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
The MTD framework reserves 1 or 2 bytes for the bad block marker
depending on the bus size. The rockchip_nfc driver currently only
supports a 8 bit bus, but reserves standard 2 bytes for the BBM.
The first free OOB byte is therefore OOB2 at offset 2.
Page address(PA) bytes are moved to the last 4 positions before
ECC. Update the description for U-boot.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add flash_node to the rockchip_nfc driver chip structure in order
to find the partitions in the add_mtd_partitions_of() function.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
The MTD framework in U-boot is not identical for drivers ported
from Linux. The rockchip_nfc driver was ported with OOB ops functions
while the framework expects a layout structure per chip.
Fix by adding a structure with OOB data and remove unused functions.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
The compatible string for rk3308 has as fallback string
"rockchip,rv1108-nfc". As there is no logic in probe priority between
the SoC orientated string and the fall back, so remove the compatible
string "rockchip,rk3308-nfc" from the driver.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
The fdt_addr_t and phys_addr_t size have been decoupled.
A 32bit CPU can expext 64-bit data from the device tree parser,
so use dev_read_addr_ptr in the rockchip_nfc.c file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Request the reset gpio of the rgmii-id phy as output to be consistent
with the eth-phy-uclass driver.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Add minimal support for 8125B version.
Changes are based on the Linux driver.
Tested on Radxa Rock 5B Rk3588 board.
Connection to a laptop worked fine in 100 Mbps mode.
1000 Mbps mode is not working at the moment.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
dp83867 driver only supports sgmii and not all the newer protocols.
Drop the usage of the generic phy_interface_is_sgmii function and just
matchup to the specific mode supported.
Reported-by: Tom Rini <trini@konsulko.com>
Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Suggested-by: Marek Behún <kabel@kernel.org>
Link: https://lore.kernel.org/all/b82ac325-4818-8e72-054b-640268dbf806@mailbox.org/
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Introduce reboot, boot and continue commands support to
TCP fastboot by moving existing UDP logic into the common module.
Signed-off-by: Dmitrii Merkurev <dimorinny@google.com>
Cc: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Сс: Joe Hershberger <joe.hershberger@ni.com>
Сс: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Known limitations are
1. fastboot reboot doesn't work (answering OK but not rebooting)
2. flashing isn't supported (TCP transport only limitation)
The command syntax is
fastboot tcp
Signed-off-by: Dmitrii Merkurev <dimorinny@google.com>
Cc: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Сс: Joe Hershberger <joe.hershberger@ni.com>
Сс: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rtl8211e_startup() is an exact copy of genphy_startup(). Use that
instead of duplicating it.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Read the phy mode of the external phy from the device tree if available
and check that it is a RGMII variant.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Without that patch it lost track to the node to scan
speed and duplex.
Patch was created by Marek Vasut, just tested by me.
Signed-off-by: Elmar Psilog <epsi@gmx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
In the process of adopting CONFIG_DM_ETH on the DPAA2 based platforms,
interfaces which were previously defined as "xgmii" were transitioned to
be defined as "xfi" in the DTS.
See the commit below for reference:
commit 87274918f2 ("arm: dts: ls2088ardb: add DPMAC and PHY nodes")
Then Vladimir's commit replaced all occurrences of "xfi" with
"10gbase-r" in an effort to make U-Boot work with the same device tree
as Linux.
commit 77b11f7604 ("net: replace the "xfi" phy-mode with "10gbase-r"")
These changes to the phy_interface_t of an Ethernet port meant that the
mc_fixup_mac_addrs() function was no longer capable to properly fixup
the MAC addresses. The problem arises from the fact that the hardcoded
information about an interface (wriop_get_enet_if()) was no longer
matching any actual device.
For example, the function tried to search for "DPMAC1@xgmii1" by name
using eth_get_dev_by_name() when only "DPMAC1@10gbase-r" was available.
This function removes the need to rely on the hardcoded information by
iterating through all the UCLASS_ETH devices which are DPAA2 and request
a fixup for each of them.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Export the ldpaa_eth_get_dpmac_id() function so that it can be used from
other drivers, especially by fsl-mc which will need it the next patch.
Also, create a macro for the Ethernet ldpaa driver name and export it as
well.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Add a port_probe function to configure the phy. This leads to
earlier link negotiation so the port is more likely to be ready
when used.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
We don't do anything useful with the master dev, so remove the variable.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
packet tagging is not used for this driver so we do not need to
call dsa_set_tagging.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Instead of inhibiting parameter RAM relacation, take
into account the configured one.
It means INIT_TRX command cannot be used and must be done
manually as explained in the microcode patch application note.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
This allows the Layerscape PCIe RC driver to use the upstream
style binding (two "reg" entries instead of four).
It is similar to the previous commit e10da1f985
("pci: layerscape: add official ls1028a binding support")
which implemented this for the LS1028A.
Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
ESM MCU masks must be set to 0h so that PMIC can handle errors
that require attention for example SYS_SAFETY_ERRn. The required bits
must be cleared: ESM_MCU_RST_MASK, ESM_MCU_FAIL_MASK, ESM_MCU_PIN_MASK.
If PMIC expected to handle errors, make sure EVM is configured to
connect SOC_SAFETY_ERRz (Main) to the PMIC.
Note that even though the User Guide for TPS65941 for J721E mentions
that these bits are reset to 0h; it is not reflected once board boots to
kernel, possibly due to NVM configurations. Eithercase, it is best to
account for this from R5 SPL side as well.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
With relocation, CPM parameter RAM can be anywhere in the
dual port RAM, so don't split dual port RAM.
Remove dparam and dparam16 members of struct comm_proc
PROFF_XXX become offsets from the start of dual port RAM,
then they are now consistant with the offsets in RPBASE
registers.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
PCIe Root Port does not have any PCIe memory, so returns zero when trying
to read from PCIe Root Port BAR0 and ignore any writes.
Signed-off-by: Pali Rohár <pali@kernel.org>
It adds compatible "hisilicon,hi3798mv200-dw-mshc" for HC2910 SoC
Hi3798MV200 to probe this mmc driver.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Commit dafe0fbfb0 ("pinctrl: mediatek: rewrite mtk_pinconf_set and
related functions") changed the logic deciding to set R0 and R1
registers for V1 devices.
Before:
/* Also set PUPD/R0/R1 if the pin has them */
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
if (err != -EINVAL) {
mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
}
After:
/* try pupd_r1_r0 if pullen_pullsel return error */
err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
val);
if (err)
return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
pullup, val);
Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function
always either returns 0 in case of success or -EINVAL in case any error
has occurred. Hence the logic responsible of the decision to program R0
and R1 has been inverted.
This leads to problems on BananaPi R2 (MT7623N) when booting from
SDMMC, it turns out accessing eMMC no longer works since
U-Boot 2022.07:
MT7623> mmc dev 0
Card did not respond to voltage select! : -110
The problem wasn't detected for a long time as both eMMC and SDMMC work
fine if they are used to boot from, and hence R0 and R1 were already
setup by the bootrom and/or preloader.
Fix the logic to restore the originally intended and correct behavior
and also change the descriptive comment accordingly.
Fixes: dafe0fbfb0 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Tested-By: Frank Wunderlich <frank-w@public-files.de>
Starting from QUP v2.5 the value of oversampling is changed from 32
to 16, keeping the old value on newer platforms results on wrong set
UART IP clock divider, thus the asked baudrate does not correspond to
the actually set with all the consequencies for a user.
The change links the driver to a new Qualcomm GENI SE QUP driver
to get its hardware version and update the oversampling value.
Deliberately the code under CONFIG_DEBUG_UART_MSM_GENI is not touched,
since a wanted baudrate can be controlled by setting a modified
CONFIG_DEBUG_UART_CLOCK build time variable.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.
[vzapolskiy: removed a ready change in the driver]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
A compiler warns about a missing function prototype, which is valid
and fixed by converting the function into static one, also fix
interleaved local variable declarations and assignments.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Fixes: 324df15a29 ("serial: qcom: add support for GENI serial driver")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
This a cosmetic change, which corrects code indentation in a few places.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
There is only one clock supplier to the serial IP, thus getting it by
name is not needed, also note that "clock-names" property is not listed
under doc/device-tree-bindings/serial/msm-geni-serial.txt, and finally
"se-clk" clock name is invalid, if added, it shall get "se" value like
it's already described in Linux device tree documentation.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
In preparation for supporting upstream Linux device trees on Qualcomm
platforms, make this the default behavior.
[vzapolskiy: extracted the driver change from a combination with dts changes]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
For whatever reason, likely a driver stub was copied from another
driver, the driver contains a bunch of unnecessary and confusing
includes like watchdog.h etc., the change reduces the list.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
This change adds a Qualcomm GENI SE QUP device driver as a wrapper for
actually enabled and used serial devices found on a board.
At the moment the driver is pretty simple, its intention is to populate
childred devices and provide I/O mem read interface to them as clients,
this is needed for GENI UART driver to set up a proper clock divider
and provide the actually asked baud rate.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
MAX14526 is a powerful extcon chip which allows detection of various
plugs like usb, mhl, uart, headset etc. This version of driver
implements support of AP-usb and CP-usb/uart paths.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a new simple uclass for extcon. Currently all setup is done
in the probe. Uclass struct and ops are empty for now.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
PCI autoconfig case for PCI_CLASS_PROCESSOR_POWERPC just prints debug
message and then calls autoconfig setup code like for any other standard
endpoint device. We do not need special debug message for it, so remove
this case and handle PCI_CLASS_PROCESSOR_POWERPC via default code path.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
For the CONFIG_PHY case, move the PHY setup before the register access.
This avoids a hang when updating the imx8mm.dtsi which moves the
USB OTG power-domains to the PHY.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Fabio Estevam <festevam@denx.de>
At BDF address 00:00.0 is fictional device which PCI configuration header
is for configuring mpc85xx PCI controller itself. PCI config space of this
device has ATMU inbound registers on position of PCI BARs. Trying to do PCI
auto configuration of this device cause rewriting ATMU inbound registers.
To avoid it, do not allow overwriting registers at BARs positions. And
because this device does not have any PCI memory, return zeros when trying
to read PCI BARs config space registers. It signals to auto configuration
tool to not allocate any PCI memory for this device.
This information is taken from MPC8544E Reference Manual, sections
17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website:
https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Driver pci_mpc85xx.c is PCI controller driver for old PCI Local Bus,
which does not support access to extended PCIe registers (above 0xff),
as opposite of the PCIe driver pcie_fsl.c for the same platform.
So do not try to access extended PCIe registers as it cannot work.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read
and write access to PCI config space as described in more Freescale
reference manuals.
This change fixes issue that 8-bit and 16-bit write to PCI config space
caused to clear adjacent bits of 32-bit PCI register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
On PowerPC we should use barrier after store operation to HW register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Please pull the second part of the sunxi pull request for this cycle.
Another bunch of patches that replace old-school U-Boot hacks with
proper DM based code, this time for the raw NAND flash driver, and the
USB PHY VBUS detection code. Plus two smaller patches that were sitting
in my inbox for a while.
Gitlab CI passed. In lack of some supported board with NAND flash I
couldn't really test this part, but apparently this was tested by the
reviewer. I briefly ran the branch on some boards with USB-OTG, and
this still worked.
This pull request adds support for the last CPU board from
CS GROUP France (previously CSSI).
That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence
its name) and can be plugged in place of the CMPC885 board.
In order to support that new board, the following changes are included
in this series:
- Make the mpc8xx watchdog driver more generic for reusing it
with mpc83xx
- Fix various small problems on mpc83xx platform
- Add a GPIO Driver for QE GPIOs
- Add support for mpc832x into mpc83xx SPI driver
- Refactor existing board code that will be shared with new board
- Add the new board
For the devfdt_get_addr_index_ptr() and devfdt_get_addr_size_index_ptr()
function use map_sysmem() function as cast for the return for use in
sandbox. Also fix sandbox test.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Drop second hunk:
Signed-off-by: Simon Glass <sjg@chromium.org>
There's quite a few instances of board-specific code doing
off = fdt_path_offset(gd->fdt_blob, ...);
...
ret = uclass_get_device_by_of_offset(..., off, &dev);
looking for an eeprom or a pmic via some alias. Such code can be
simplified a little if we have a helper for directly getting a device
via device tree path (including being given as an alias).
Implement it in terms of ofnode rather than raw offsets so that this
will work whether live tree is enabled or not.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
The functions uclass_find_device_by_phandle() and
uclass_get_device_by_phandle_id() both loop over a given uclass
looking for a device with a given phandle. Factor that out to a common
helper.
For now, there are no (known potential) users of the new helper
outside uclass.c, so make it static.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix warning on sandbox_spl; fix code style:
Signed-off-by: Simon Glass <sjg@chromium.org>
Given a file ../img of size 4294967296 with GPT partition table and
partitions:
=> host bind 0 ../img
=> part list host 0
Disk host-0.blk not ready
The cause is os_filesize() returning int. File sizes must use off_t.
Correct all uses of os_filesize() too.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix a -Wimplicit-fallthrough warning in sandbox_sysreset_request().
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Avoid incorrect fall through:
A USB_RT_HUB request should not be treated as USB_RT_PORT.
Simplify the coding:
Avoid duplicate debug() statements.
This fixes all -Wimplicit-fallthrough warnings.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Handling of SANDBOX_FLASH_EP_OUT should never fall through to
SANDBOX_FLASH_EP_IN.
This addresses a warning shown when compiling with
-Wimplicit-fallthrough.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is possible to use host-side USB with externally-provided VBUS. For
example, some USB OTG cables have an extra power input which powers
both the board and the USB peripheral.
To support this setup, skip enabling the VBUS switch/regulator if VBUS
voltage is already present. This behavior matches the Linux PHY driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This driver reports the presence/absence of voltage on the PMIC's USB
VBUS pin. This information is used by the USB PHY driver. The
corresponding Linux driver uses the power supply class, which does not
exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This more closely matches the U-Boot driver to the Linux version.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Michael Trimarchi <micahel@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Clocks, resets, and pinmuxes are now handled by the driver model, so the
only thing the "board" code needs to do is load the driver. This matches
the pattern used by other DM raw NAND drivers (there is no NAND uclass).
The actual board code is now only needed in SPL.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
As a first step toward converting this driver to the driver model, use
the ofnode abstraction to replace direct references to the FDT blob.
Using ofnode_read_u32_index removes an extra pair of loops and makes the
allwinner,rb property optional, matching the devicetree binding.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
NAND is always at function 2 on port C.
Pin lists and mux values were taken from the Linux drivers.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
add nvmxip_qspi driver under UCLASS_NVMXIP
The device associated with this driver is the parent of the blk#<id> device
nvmxip_qspi can be reused by other platforms. If the platform
has custom settings to apply before using the flash, then the platform
can provide its own parent driver belonging to UCLASS_NVMXIP and reuse
nvmxip-blk driver. The custom driver can be implemented like nvmxip_qspi in
addition to the platform custom settings.
Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them.
For more details please refer to doc/develop/driver-model/nvmxip_qspi.rst
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
add block storage emulation for NVM XIP flash devices
Some paltforms such as Corstone-1000 need to see NVM XIP raw flash
as a block storage device with read only capability.
Here NVM flash devices are devices with addressable
memory (e.g: QSPI NOR flash).
The implementation is generic and can be used by different platforms.
Two drivers are provided as follows.
nvmxip-blk :
a generic block driver allowing to read from the XIP flash
nvmxip Uclass driver :
When a device is described in the DT and associated with
UCLASS_NVMXIP, the Uclass creates a block device and binds it with
the nvmxip-blk.
Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
The code has quite a few unnecessary brackets and comparisons to zero,
etc. Fix these up as well as some upper-case hex values and use of 0x in
printf() strings.
Signed-off-by: Simon Glass <sjg@chromium.org>
Avoid the use of the function name in a few of the debug() calls, since
this causes a checkpatch warning. Convert all other calls too.
Use lower-case hex consistently.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fix a longstanding bug where the LBA is calculated as the size of the
media instead of the number of blocks. This was perhaps not noticed
earlier since it prints the correct value first, before setting the wrong
value.
Drop the unnecessary blksz variable while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 68e6f221ed ("block: ide: Fix block read/write with driver model")
We only use one member of the ide_dev_desc[] array at a time and it does
not stick around outside ide_probe(). Use a single element instead.
Copy over the missing members of blk_desc at the same, since this was
missing from the previous code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 68e6f221ed ("block: ide: Fix block read/write with driver model")
Rather than having the caller fill some of this in, do it all in the
ide_ident() function, since it knows all the values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update ide_ident() to indicate whether it finds a device or not. Use
that to decide whether to create a block device for it, rather than
looking DEV_TYPE_UNKNOWN.
Signed-off-by: Simon Glass <sjg@chromium.org>
Most of the code uses 'desc' as the variable name for a blk descriptor.
Change ide to do the same.
Tidy up some extra brackets and types while we are here.
Leave the code in ide_probe() alone since it is about to be refactored.
Signed-off-by: Simon Glass <sjg@chromium.org>
The two loops in this function operate on the same ide_dev_desc[] array.
Combine them to reduce duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that ide_probe() is the only caller of ide_init(), move all the code
into the probe function, so it is easier to refactor it.
Move ide_dev_desc[] into ide_probe() to, since it is the only user.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current implementation adds this information in the block device's
probe() function, which is called in the blk_probe_or_unbind() in
ide_probe().
It is simpler to do this in ide_probe() itself, since the effect is the
same. This helps to consolidate use of ide_dev_desc[] which we would like
to remove.
Use strlcpy() to keep checkpatch happy.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use IS_ENABLED() instead for all conditions. Add the 'lba48' flag into
struct blk_desc always, since it uses very little space. Use a bool so
the meaning is clearer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Change the if() to remove extra brackets and check for the positive case
first, i.e. when a device is found. Exit the loop in that case, with the
retry logic in the 'else' part.
Signed-off-by: Simon Glass <sjg@chromium.org>
This code is hard to follow as it uses #ifdef in a strange way. Adjust
it to avoid the preprocessor. Drop the special return for the non-ATAPI
case since we can rely on tries becoming 0 and exiting the loop.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use a 'tries' variable which starts at the number of tries we want to do,
rather than a 'retries' one that stops at either 1 or 2. This will make it
easier to refactor the code to avoid the horrible #ifdefs
Signed-off-by: Simon Glass <sjg@chromium.org>
The use of atapi_read() was incorrect dropped. Fix this so that it will
be used when needed. Use a udevice for the first argument of atapi_read()
so it is consistent with ide_read().
This requires much of the ATAPI code to be brought out from behind the
existing #ifdef. It will still be removed by the compiler if it is not
needed.
Add an atapi flag to struct blk_desc so the information can be retained.
Fixes: 145df842b4 ("dm: ide: Add support for driver-model block devices")
Fixes: d0075059e4 ("ide: Drop non-DM code for BLK")
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
These are not used from outside this file anymore. Make them static and
remove them from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present the code does ide_init() as a separate operation, then calls
device_probe() to copy over the information. We can call ide_init() from
probe just as easily.
The only difference is that using 'ide init' twice will do nothing.
However it already fails to copy over the new data in that case, so the
effect is the same. For now, unbind the block devices and remove the IDE
device, which causes the bus to be probed again. Later patches will fix
this up fully, so that all blk_desc data is copied across.
Since ide_reset() is only called from ide_init(), there is no need to init
the ide_dev_desc[] array. This is already done at the end of ide_init() so
drop this code.
The call to uclass_first_device() is now within the probe() function of
the same device, so does nothing. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sometimes virtio may rely on PCI, or at least that is what the
distro_bootcmd script suggests. Add this in.
Signed-off-by: Simon Glass <sjg@chromium.org>
If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause
issues in future command reads. This issue came to light when some flash
reads in STIG mode were coming back dirty.
Co-developed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
OSPI controller supports all types of op variants in STIG mode,
only limitation being that the data payload should be less than
8 bytes when not using memory banks.
STIG mode is more stable for operations that send small data
payload and is more efficient than using DMA for few bytes of
memory accesses. It overcomes the limitation of minimum 4 bytes
read from flash into RAM seen in DAC mode.
Use STIG mode for all read and write operations that require
data input/output of less than 8 bytes from the flash, and thereby
support all four phases, cmd/address/dummy/data, through OSPI STIG.
Also, remove the reorder address chunk in apb_command_write since we now
setup ADDR BIT field that does the same job in a cleaner way.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
buswidth and dtr fields in spi_mem_op are only valid when the
corresponding spi_mem_op phase has a non-zero length. For example,
SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR
phase.
Fix the dtr checks in set_protocol() to ignore empty spi_mem_op
phases, as checking for dtr field in empty phase will result in
false negatives.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This patch adds fixups for s25fs512s to address the following issues
from reading SFDP:
- Non-uniform sectors by factory default. The setting needs to be
checked and assign erase hook as needed.
- Page size is wrongly advertised in SFDP.
- READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h)
are not supported.
- Bank Address Register (BAR) is not supported.
In addition, volatile version of Quad Enable is used for safety.
Based on patch by Takahiro Kuwano with s25fs_s_post_bfpt_fixup() updated
to use 4-byte address commands instead of extended address mode and the
page_size is fixed to 256
For future use, manufacturer code should be moved out from framework
code as same as in Linux.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Family of panels used by HTC in One X. Though were used variants
at least from 3 vendors, this driver provides generic support for
all of them.
Tested-by: Ion Agorria <ion@agorria.com> # HTC One X T30 Sony
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30 Sharp
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
DC based PWM backlight is found on some T20 and T30 devices
(HTC One X). This backlight is controlled by Tegra DC and
is adjustable by the DC PM0 or PM1 signal.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # HTC One X T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Driver adds support for panels with Renesas R69328 IC
Currently supported compatible is:
- jdi,dx12d100vm0eaa
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
R61307 is liquid crystal driver for high-definition
amorphous silicon (a-Si) panels and is ideal for
tablets and smartphones.
Supported compatibles are:
- koe,tx13d100vm0eaa
- hitachi,tx13d100vm0eaa
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
SSD2825 is an innovative and cost-effective MIPI Bridge Chip solution
targeting high resolution smartphones. It can convert 24bit RGB
interface into 4-lane MIPI-DSI interface to drive extremely high
resolution display modules of up to 800 x 1366, while supporting AMOLED,
a-si LCD or LTPS advanced panel technologies for smartphone applications.
Bridge is wrapped in panel uClass model for wider compatibility.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This is basic lm3533 driver only with bank A and backlight cell
support.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By the time we jump to the err label, count represents the number of
gpios we've successfully requested. So by subtracting one, we fail to
free the most recently requested.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Xen core_init() is calling HVC which should be called from EL1 level that's
why do Xen initialization only when U-Boot runs in EL1.
Signed-off-by: Michal Simek <michal.simek@amd.com>
The non DM code path already would enable pci bus mastering. Do the
same for the DM code path.
Fixes AHCI problems I am seeing on an Intel Apollolake device.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[trini: Use ahci_dev not dev in the calls]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add weak function psci_sysreset_get_status for platform to define
their own reset status with CONFIG_SYSRESET enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
XEN config can be enabled by other platforms (even it doesn't need to make
sense) that's why fix dependencies. XEN (xenbus.c) requires sscanf (also
pvblock needs it). And PVBLOCK is inside drivers/xen folder which requires
XEN to be enabled.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
When building with clang, it notes that sdinfo may be unused
uninitialized in some cases. This appears to be true from reading the
code, and we can simply set the variable to zero to start with and be as
correct as before.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Marek Vasut <marex@denx.de>
If rev is equal to the array size, we'll access the array
one-past-the-end.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Bryan Brattlof <bb@ti.com>
When building with clang, the compiler compains with
drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
else if (priv->mode & SPI_TX_OCTAL)
^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here
val |= ((bus_width >> 1) << BUS_WIDTH);
^~~~~~~~~
drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true
else if (priv->mode & SPI_TX_OCTAL)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning
So initialize bus_width to 1 and add a warning if none of the configured
modes matches
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
NPCM7xx/NPCM8xx default is boot from flash.
removed set clock feature due to reliability and security.
the clock will set by bootblock or tip.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The .supports_op() callback function returns true by default after
performing driver-specific checks. Therefore the driver cannot apply
the buswidth in devicetree.
Call spi_mem_default_supports_op() helper to handle the buswidth
in devicetree.
Fixes: 358f803ae2 ("spi: Add Socionext F_OSPI SPI flash controller driver")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
in spi_mem_dtr_supports_op we have a check for allowing only even number
of bytes to be r/w. Odd bytes writing can be a concern while writing
data to a flash for example because 8 DTR mode doesn't support it.
However, reading ODD Bytes even though may not be physically possible
we can still allow for it because it will not have serious implications
on any critical registers being overwritten since they are just reads.
Cc: Vaishnav Achath <vaishnav.a@ti.com>
Cc: Pratyush Yadav <pratyush@kernel.org>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Nikhil M Jain <n-jain1@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This should have been op->data.buswidth instead as we check for octal
bus width for the data related ops
Also add explanation for why there is checks for 8D even data bytes
Cc: Pratyush Yadav <pratyush@kernel.org>
Reviewed-by: Pratyush Yadav <ptyadav@amazon.de>
Tested-by: Nikhil M Jain <n-jain1@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add support for CHIP_ERASE opcode 0xc7 . This is useful in case the
entire SPI NOR is supposed to be erase at once, as is it considerably
faster than 4k sector erase and even slightly faster than 64k block
erase. The spi_nor_erase_chip() implementation is adapted from Linux
6.1.y as of commit 7d54cb2c26dad ("Linux 6.1.14") . The chip erase is
only used in case the entire MTD device is being erased, and the chip
does support this functionality.
Timing figures from W25Q128JW:
16 MiB erase using 4kiB sector erase opcode 0x20 ... 107.5s
16 MiB erase using 64kiB block erase opcode 0xd8 ... 39.1s
16 MiB erase using chip erase opcode 0xc7 .......... 38.7s
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Devices advertising the VIRTIO_F_IOMMU_PLATFORM feature require
platform-specific handling to configure their DMA transactions.
When handling virtio descriptors for such a device, use bounce
buffers to ensure that the underlying buffers are always aligned
to and padded to PAGE_SIZE in preparation for platform specific
handling at page granularity.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: 1eff171e61
Reviewed-by: Simon Glass <sjg@chromium.org>
In preparation for bouncing virtio data for devices advertising the
VIRTIO_F_IOMMU_PLATFORM feature, allocate an array of bounce buffer
structures in the vring, one per descriptor.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: 3e052749e7
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the attach and detach logic for manipulating vring descriptors
out into their own functions so that we can later extend these to
bounce the data for devices with VIRTIO_F_IOMMU_PLATFORM set.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: f73258a4bf
Reviewed-by: Simon Glass <sjg@chromium.org>
In preparation for explicit bouncing of virtqueue pages for devices
advertising the VIRTIO_F_IOMMU_PLATFORM feature, introduce a couple
of wrappers around virtqueue allocation and freeing operations,
ensuring that buffers are handled in terms of page-size units.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: b4bb5227d4
Reviewed-by: Simon Glass <sjg@chromium.org>
The pages backing the virtqueues for virtio PCI devices are not freed
on reset, despite the virtqueue structure being freed as part of the
driver '->priv_auto' destruction at ->remove() time.
Call virtio_pci_del_vqs() from virtio_pci_reset() to free the virtqueue
pages before freeing the virtqueue structure itself.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: 5ed54ccd83
Reviewed-by: Simon Glass <sjg@chromium.org>
If we detect the VIRTIO_F_IOMMU_PLATFORM transport feature for a device,
then expose it in the device features.
Signed-off-by: Will Deacon <willdeacon@google.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Link: 9693bd26bf
Reviewed-by: Simon Glass <sjg@chromium.org>
To support video driver at SPL use CONFIG_IS_ENABLED and CONFIG_VAL,
which checks for stage specific configs and thus enables video support
at respective stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
To enable TIDSS driver only at SPL stage add rule to compile the TIDSS
video driver.
CONFIG_$(SPL_)VIDEO_TIDSS will compile tidss_drv, at SPL only if
CONFIG_SPL_VIDEO_TIDSS is defined and at u-boot proper if
CONFIG_VIDEO_TIDSS is defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To enable video driver at SPL, need to compile video-uclass,
vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add
rules to compile them at SPL and u-boot proper. To support
splash_display at SPL, need to compile video-bmp, add rule to compile at
SPL and u-boot proper.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Compile video driver at SPL using CONFIG_SPL_VIDEO.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
Add Kconfigs which enable the video driver and splash screen at SPL
stage only and not at u-boot proper. The existing Kconfigs from u-boot
proper were not used to make SPL splash screen independent to them.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Configuring master firewalls require the power of the cluster to be
enabled before configuring them, change the load of rproc to configure
the gtc clocks and start the cluster along with configuring the boot
vector.
The start of rproc will only start the core.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
These probably should be in some system wide header given their use.
Until then move them out of K3 sys_proto.h so we can finish cleaning
that header out.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
The K3 JTAG and SoC ID information is already stored in the K3 arch
hardware file, include that and use its definitions here.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
- Add rk3588 evb support;
- Update pinctrl for rk3568 and rk3588;
- Update rk3288 dts;
- Update mmc support for rk3568 and rk3588;
- Add rng support for rk3588;
- Add DSI support for rk3568;
- Some other misc fixes in dts, config, driver;
- watchdog: arm_smc_wdt: add watchdog support (Lionel)
- watchdog: ftwdt010: return a previously deleted driver now ported to
DM (Sergei)
- watchdog: Add a watchdog driver for Raspberry Pi boards (Etienne)
_ Add usb_pgood_delay for ST boards
_ increase malloc size for pre-reloc for stm32mp15
_ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15
dts:
_ Add QSPI support on STM32MP13x SoC family
_ Add FMC support on STM32MP13x SoC family
drivers/machine:
_ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
_ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
_ rawnand: stm32_fmc2: remove unsupported EDO mode
_ stm32mp: fix various array bounds checks
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmQ/s+kcHHBhdHJpY2Uu
Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pkQHEACnlVjvcMLuT+Fx9fA7
sUfIoDnDQjRugyoEMts0tiAVabPps3rk2fVwuEG6LMRrF5qCTmexjB9HJ0zqIVZj
FxOdP6fLL1629rJpRHQM1tGGmrzktxe/DRGH0VuVKhdH4MLtOWq/yC1XPfmeYh8/
Lt+5uLIMIoBK0sZzNToDctN/KWPA6/UDrFZ7YmnIntL1F39dyiQ+jwvopZZVZ/+v
uP/rwMDDCS7J0yCPa3WocSgOnhN3cE1amgFO7jJP43MBOntWsWmb4TWY+YVoxz1z
PkZPRgQ2YHrFF3vtjL9rCiZSvelnRvSMaO+SZ7AmxNw6KR0ZC0SuCJY9glI257PA
qHK6H7jzHW+Ti2+1NsY8bb8pG9Ewt0AtKc5nSmtbaCgikzdOfoFNOSBIKIZPhXp4
7mxnRbPibK6a6TKIPFL82Ohxnt1hvr+ZD3V2yRdvx0ifMNB1J3F8Rpz4g5i1sPMQ
PqKLAQB6cev8pfw+ItL0VDLhX8zAlCXyrXlxHT0osU88HecIt6ERpNpZZH9Gwp0c
HbR8Sa3VYlG5EyMERmpsVZeA7pBGDtr3aKRRaqsTUrtltRkLOV8SBIXtGLLFiYFW
eEShJO660+Lpb83WenV9A38I8f9qZS9AN+CSAE7EjBDGowAR21VyNcOStz09Yn9a
a84w7wQygGm4mPQWlrOauq57XQ==
=3Txq
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20230419' of https://source.denx.de/u-boot/custodians/u-boot-stm
configs:
_ Add usb_pgood_delay for ST boards
_ increase malloc size for pre-reloc for stm32mp15
_ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15
dts:
_ Add QSPI support on STM32MP13x SoC family
_ Add FMC support on STM32MP13x SoC family
drivers/machine:
_ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()
_ spi: stm32_qspi: Remove useless struct stm32_qspi_flash
_ rawnand: stm32_fmc2: remove unsupported EDO mode
_ stm32mp: fix various array bounds checks
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm]
Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
It will be replaced by a more recent version which contains fixes for
tests run by Tom Rini.
This reverts commit ff33d3c87c.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Using DMA to load TF-A into SRAM fails when booting from eMMC on RK3588.
## Checking hash(es) for Image atf-3 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-3' image node
spl_load_simple_fit: can't load image loadables index 2 (ret = -1)
mmc_load_image_raw_sector: mmc block read error
Fix this by using PIO mode in SPL and limit the number of blocks used in
a single read command to avoid triggering Data End Bit Error interrupt.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices,
where performing DMA to SRAM later causes issues with suspend/resume.
Allow us to toggle SDMA in SPL for sdhci similar to ADMA support, so we
can ensure DMA is not used when loading the SRAM code.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
[jonas@kwiboo.se: add Kconfig default value and fix ADMA typo]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
The device tree sdhci node reference the TMCLK_EMMC clock, add limited
support this clock to rk3588 cru driver. Fixes probe of sdhci driver.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for RK3588 to the rockchip sdhci driver.
Use driver data to handle differences between RK3568 and RK3588:
- Set "Receive original clock source is auto gating" for RK3588.
- Set "Receive clock source is no-inverted" only on RK3568 and "Transmit
clock source is invertion of original clock input" for RK3588.
- Use different txclk_tapnum for HS400 modes on RK3588.
- Configure the CMDOUT reg for HS400 modes for RK3588.
This is based on the mainline linux and vendor kernel driver and have
successfully been tested with rock5b-rk3588_defconfig and
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_SPEED_MODE_SET=y
using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,
=> mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000
for each of the modes below.
0 = MMC legacy
1 = MMC High Speed (26MHz)
3 = MMC High Speed (52MHz)
4 = MMC DDR52 (52MHz)
10 = HS200 (200MHz)
11 = HS400 (200MHz)
12 = HS400ES (200MHz)
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Adjust tap number for transmit clock, tap number and delay number for
strobe input to fix HS400 modes on RK3568.
New values have been picked from vendor kernel and u-boot and have
successfully been tested with rock-3a-rk3568_defconfig and
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_SPEED_MODE_SET=y
using the following command to switch mode and then read 512 MiB of data
from eMMC into memory,
=> mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000
for each of the modes below.
0 = MMC legacy
1 = MMC High Speed (26MHz)
3 = MMC High Speed (52MHz)
4 = MMC DDR52 (52MHz)
10 = HS200 (200MHz)
11 = HS400 (200MHz)
12 = HS400ES (200MHz)
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This rearrange and remove duplicate defines to make the code cleaner.
There is no need to read vendor area1 and use an offset each time, it is
easier and clearer to just use the reg offset defined in TRM, same as
the other vendor regs.
This also removes use of the misspelled const for the RK3588 CMDOUT reg,
it will be re-added when support for RK3588 is introduced.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove empty implementations of get_phy and set_enhanced_strobe ops.
Change driver set_enhanced_strobe to return 0 in order to allow missing
implementation of the ops.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Refactor set_ios_post ops to correctly set UHS Speed Select field values
according to TRM. Also set or unset Enhanced Strobe Enable bit and
eMMC Card present bit in set_ios_post, the Enhanced Strobe Enable bit
was never unset after switching to HS400ES mode.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Check return value from mmc_send_cmd and clear HOST_CONTROL2 when there
is an error. Also skip enable of interrupt signaling and remove a delay,
a delay is already happening in sdhci_send_command.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change to configure clock and DLL in set_clock and config_dll ops
instead of in the set_ios_post ops.
With this change the output clock is turned off while configuring DLL
parameters, according to the design recommendations.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for the set_clock and config_dll sdhci_ops. Use of these ops
will allow configuration of DLL while the output clock is disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Remove the unneeded emmc_phy_init now that the no-inverter flag is
handled correctly after commit 2321a991bb ("rockchip: sdhci: rk3568:
bypass DLL when clk <= 52 MHz").
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The device private data is misused in rockchip_sdhci_of_to_plat and
rockchip_sdhci_execute_tuning.
In these functions dev_get_priv is assigned to struct sdhci_host:
struct sdhci_host *host = dev_get_priv(dev);
Instead, the sdhci host should refer to host in struct rockchip_sdhc:
struct rockchip_sdhc *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
Because host is the first member in struct rockchip_sdhc this is not a
real problem, lets fix it anyway and also use priv name consistently.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode.
Fixes: d1c0a2200a ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Set High Speed Enable bit for MMC High Speed (52MHz) mode.
Fixes: f12341a952 ("mmc: sdhci: Fix HISPD bit handling")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This adds support for the TRNG found in the RK3588 SoC to the
rockchip_rng driver so that it can be used for things such as
seeding randomness to Linux.
Changes in V3:
- Moved notes from commit to cover letter.
- Added Reviewed-By tag.
Changes in V2:
- Modified Kconfig to note that the Rockchip RNG driver supports all
versions of the hardware (v1, v2, and the trng in the rk3588).
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock
in assigned-clocks, add dummy support to set parent of this clock to the
rk3568 cru driver.
Fixes probe of pmic driver and missing regulators on affected boards,
rk3568-evb and rk3568-rock-3a.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
IO mux selection is not working correctly for all pins. Sync mux route
data from linux to add any missing and update wrong trigger pins to fix
this. Also apply the pull-up fix needed for GPIO0 D3-D6.
Fixes: 1977d746aa ("rockchip: rk3568: add rk3568 pinctrl driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.
The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.
This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.
Fixes: 7a474df740 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options
enabled and SPL_FIRMWARE disabled result in the following error.
drivers/clk/clk_scmi.o: in function `scmi_clk_gate':
drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate':
drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate':
drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg'
drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno'
drivers/clk/clk_scmi.o: in function `scmi_clk_probe':
drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel'
make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1
make: *** [Makefile:2043: spl/u-boot-spl] Error 2
Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The documentation for misc_read() says:
Return: number of bytes read if OK (may be 0 if EOF), -ve on error
The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success. Fix this so that the driver
follows the usual contract for read operations.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The documentation for misc_read() says:
Return: number of bytes read if OK (may be 0 if EOF), -ve on error
The Rockchip efuse driver implements this so it should return the number
of bytes read rather than zero on success. Fix this so that the driver
follows the usual contract for read operations.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for DSI Host controller on Rockchip RK3568. This driver
is heavily based on the Rockchip dw_mipi_dsi_rockchip.c driver in
Linux and the stm32_dsi.c driver in U-Boot. It should be easy to add
support for other SoCs as the only missing component from the mainline
driver is setting the VOP big or VOP little (which the rk3568 does
not have).
Driver was tested for use in sending commands to a DSI panel in order
to obtain the panel ID.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs.
The driver was ported from Linux and tested on a Rockchip RK3566
based device to query the panel ID via a DSI command.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin
prints:
"Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB"
U-Boot TPL prints:
"BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB"
Add missing high row detection so that U-Boot TPL prints Row=16, same as
the Rockchip ddr init bin:
"BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB"
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The GPIO V2 controller on RK3568 and RK3588 works very similar to
prior generation, main difference is the use of a write mask in the
upper 16 bits and register address offset have changed.
GPIO_VER_ID is a new register at 0x0078 that is used to determine when
the driver should use new or old register offsets and values. Earlier
generation return 0x0 from this offset.
Refactor code and add support for the GPIO V2 controller used in RK3568
and RK3588.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The current divider to calculate the bank ID can change.
Given the Rockchip TRM not all gpio-banks have 32 pins per bank.
The "gpio-ranges" syntax allows multiple items with variable number
of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM
instead of PCLK_PWM. They have the same pclk_cpu parent,
so add PCLK_RKPWM to rk3288_clk_get_rate().
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In the current rk3288.dtsi file the compatible string for
the DisplayPort(DP) node ends with "edp". The string in the
binding ends with "dp" which conflicts with "cdn-dp" as a
search term. Add "rk3288-dp" as compare string to select
vop_id.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for Rockchip rk3588 variant of pinctrl.
The driver is adapted from the Linux driver.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[eugen.hristev@collabora.com:
port to latest U-boot, bring more changes from Linux
use translated pull values table]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.
Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.
Fix it by using MAX(mmc->tran_speed, mmc->clock)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Add a DM reset driver for StarFive JH7110 SoC.
Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
In all these cases, the index on the LHS is immediately afterwards
used to access the array appearing in the ARRAY_SIZE() on the RHS - so
if that index is equal to the array size, we'll access
one-past-the-end of the array.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Remove the EDO mode support from as the FMC2 controller does not
support the feature.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Currently, in stm32_qspi_claim_bus(), QSPI_CR and QSPI_DCR registers
are saved in stm32_ospi_flash struct on first flash memory initialization
and restored on each flash accesses.
As the logic of spi-uclass.c changed since 'commit 741280e9ac
("spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logic")'
set_speed() and set_mode() callbacks are called systematically when bus
speed or bus mode need to be updated, QSPI_CR and QSPI_DCR registers are
set accordingly.
So stm32_qspi_claim_bus() can be updated by removing QSPI_CR and QSPI_DCR
save/restore code and struct stm32_ospi_flash can be removed as well.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
For debug purpose, it should be useful to indicate the slew rate for
each pins.
Add ospeed register information for pins which are configured in
either alternate function or gpio output.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Implement a ARM SMCCC based driver that allow to use
a secure watchdog on the platform.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The ftwdt010 watchdog driver was deleted by
commit 11232139e3 ("nds32: Remove the architecture")
Return it to the codebase in a DM compatible form. Enable it in
sandbox_defconfig to test compilability.
Another platform using ftwdt010 will be submitted later.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This driver supports the bcm2835 watchdog found on
Raspberry Pi boards.
It is derived from the Linux driver and was tested
on two Raspberry Pi board versions (B+ and 3B+).
Signed-off-by: Etienne Dublé <etienne.duble@imag.fr>
Reviewed-by: Stefan Roese <sr@denx.de>
The first two patches are by Frieder Schrempf who joins as a reviewer for
the SPI NAND framework and drivers.
The following 2 patches are by Linus Walleij and are taken by the series
"Add Broadcom Northstar basic support".
Bin Meng makes static a list for octeontx.
Francesco Dolcini specifies MTD partitions on command line for
colibri-{imx6ull,imx7}.
-----BEGIN PGP SIGNATURE-----
iQJYBAABCgBCFiEE6GOTDNYiFygVXvMmQBtB6IWRjvEFAmQ9ALMkHGRhcmlvLmJp
bmFjY2hpQGFtYXJ1bGFzb2x1dGlvbnMuY29tAAoJEEAbQeiFkY7x6YMP/3vW6t7v
R0y3pGS0CcZhOtxLKH2Z5KbC6qoFmkK40vqvrKyUX1m4haJ+4A6BJR/rvdTCNftP
2ezpSF5SV7ZnG6+DIuY3Zvh7Jr9+ApuMmsm2vPeg8bv8gevzq3dHMk8msZb3P9+c
YX0FOpukZcJiYI9p2d+AFBLS2ETvfOYNhcfGu9PP1LdlChu1VL5BTwxmiKPuNf7D
6Rte3he0JubiLGp3CnLnj+o2l2OVrj+Kokv+jBCVVDtaVujD8tUCT+FJ/8FrXgFS
S/IOxV1DwhaxGHEjzM6ozq94b2lKB1v9PvapmveQSRmY+O01Q108uFUxMw5G6RyS
tEzoqdTk6u5Gzv/arsbXNSPe6i41QY454NqA5tOdUYprMQKM8k/P+ow9c5r4VRMH
YybBqYMAYs/9qmhBBfHhMnwEpzpHxBVTBTWtdqEIP85FcDgDV6HOs3imx05VnMe4
jfUBja5I0rzo9i7tvOhOOr4KTA1Qdg4xGTEm2nvKXHoIrGm3pC4wY54Q1F2UNm1b
osyqUh9pHqlgy+/8VPsUmu8zoewH/j4tGl1JRhYPd2QmYPlI7lDkhRtOBGOzBDAF
xvUQd5F2sYw6bDe7kiUfoX37Uy8cDupAETEYLpnGqG2/sLDo5p/VPNEiETAbfCmV
yVTDYvljxy/l3sqTUqbmkYS7V64UUc8tn0ql
=1lGu
-----END PGP SIGNATURE-----
Merge tag 'u-boot-nand-20230417' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
Pull request for u-boot-nand-20230417
The first two patches are by Frieder Schrempf who joins as a reviewer for
the SPI NAND framework and drivers.
The following 2 patches are by Linus Walleij and are taken by the series
"Add Broadcom Northstar basic support".
Bin Meng makes static a list for octeontx.
Francesco Dolcini specifies MTD partitions on command line for
colibri-{imx6ull,imx7}.
This patch adds Ethernet Switch support that found on R-Car S4
(r8a779f0) SoC. This is extracted from multiple patches from
downstream BSP, with additional rework of the network device
registration.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Marek: Rework the driver to support all ports via subdrivers.
Split the driver up, add generic PHY framework support.
Generic code clean ups.]
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0).
The datasheet describes initialization procedure without any information
about registers' name/bits. So, this is all black magic to initialize
the hardware. Especially, all channels should be initialized at once.
This driver is imported and adjusted from Linux 6.3-rc1 commit:
50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Use IS_ENABLED() instead of CONFIG_IS_ENABLED() to check for CONFIG_
option which is identical across all of U-Boot and xPL builds.
Fixes: 2769ddc99f ("mmc: tmio: Replace ifdeffery with IS_ENABLED/CONFIG_IS_ENABLED macros")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
octeontx_bch_devices and octeontx_pci_nand_deferred_devices are only
referenced in the files where they are defined. Make them static.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230405143837.785082-1-bmeng@tinylab.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Add support for the iproc Broadcom NAND controller,
used in Northstar SoCs for example. Based on the Linux
driver.
Cc: Philippe Reynes <philippe.reynes@softathome.com>
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/all/20230308214231.378013-1-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/all/20230308212851.370939-1-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
- DDR Training sequence happens very fast. The speedup in boot time is
negligible by skipping the training sequence during 2nd boot or after.
So remove the check and skip.
- This change improves the robustness of DDR training. If u-boot crashed
during DDR training, the training could be left in a limbo state, where
the BootROM has recorded that it is already in a 2nd boot. The training
must be repeated in this scenario to get out of this limbo state, but due
to the check it cannot be performed.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Now that all differences in functionality are covered by individual
flags, remove the enumeration of SoC variants.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
While R40 puts the EMAC syscon register at a different address from
other variants, the relevant portion of the register's layout is the
same. Factor out the register offset so the same code can be shared
by all variants. This matches what the Linux driver does.
This change provides two benefits beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Describe this feature instead of using the SoC ID.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Currently, EMAC variants are distinguished by their identity, but this
gets unwieldy as more overlapping variants are added. Add a structure so
we can describe the individual feature differences between the variants.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The HDMI PHY depends on the HVCC supply being enabled. So far we have
relied on it being enabled by an earlier firmware stage (SPL or TF-A).
Attempt to enable the regulator here, so we can remove that dependency.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This abstracts away the CCU register layout, which is necessary for
supporting new SoCs like H6 with a reorganized CCU. One of the resets is
referenced from the PHY node instead of the controller node, so it will
have to wait until the PHY code is factored out to a separate driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This driver is actually used for powerpc and m68k/ColdFire.
On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6,
interrupt enabled) is not set appropriately before each transfert.
As a result, the transfert hangs forever waiting for IIEN.
This patch set IIEN before each transfert, while considering this fix
as not harming powerpc arch.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
The IS_ENABLED, which does not consider SPL build, should be replaced
by CONFIG_IS_ENABLED.
For the case that we only enable DM CLK for u-boot but not in SPL, the
IS_ENABLED(CONFIG_CLK) still returns true, then cause clock failure.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Current code use dm_gpio_get_value() to get SDA and SCL value, and the
value depends on whether DTS file config the GPIO_ACTIVE_LOW. In ususal
case for i2c GPIO, DTS need to set GPIO_ACTIVE_LOW for SCL/SDA pins. So
here the logic is not correct.
And we must not use GPIOD_ACTIVE_LOW in client code include the
dm_gpio_set_dir_flags(), it is DTS's responsibility for this flag. So
remove GPIOD_ACTIVE_LOW here.
Fixes: aa54192d4a ("dm: i2c: implement gpio-based I2C deblock")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Alexander Kochetkov <al.kochet@gmail.com <mailto:al.kochet@gmail.com>>
This code first figures out if there is an i2c,speeds property, if so
its size in u32s, and then reads the value into the local speeds[]
array. Both 'size' and 'speeds' are completely unused thereafter.
It's not at all clear what this is supposed to do. Of course, it could
be seen as a sanity check that the DT node does have an i2c,speeds
property with an appropriate number of elements, but for that one
wouldn't actually need to read it into speeds[]. Also, I can't find
anywhere else in the U-Boot code which makes use of values from that
property (this is is the only C code referencing "i2c,speeds"), so it
seems pointless to insist that it's there.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
All build targets using this driver already use DM_MMC. So let's depend
this driver on this Kconfig symbol and remove the non-DM driver part.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
CONFIG_MMC_SDHCI_IO_ACCESSORS is not supported and/or used by this
driver so let's remove these unused parts completely.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This driver already depends on CONFIG_ARCH_MVEBU, so there is no need
to have some checks for this Kconfig symbol in the driver itself. Let's
remove these superfluous checks.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The default erase command applies on erase group unit, and
simply round down to erase group size. When the start block
is not aligned to erase group size (e.g. erasing partition)
it causes unwanted erasing of the previous blocks, part of
the same erase group (e.g. owned by other logical partition,
or by the partition table itself).
To prevent this issue, a simple solution is to use TRIM as
argument of the Erase command, which is usually supported
with eMMC > 4.0, and allow to apply erase operation to write
blocks instead of erase group
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
When secure/insecure TRIM operations are supported.
When used as erase command argument it applies the
erase operation to write blocks instead of erase
groups.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
-----BEGIN PGP SIGNATURE-----
iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCZDBwUw4cYWd1c3RAZGVu
eC5kZQAKCRBM6ATMmsalXL3+AJ9EkQKAWXZtlYdAOVl4/nzJnuTCAQCfY58zkDsw
TnAlwmMGWFl3RF6yGXY=
=uYUp
-----END PGP SIGNATURE-----
Merge tag 'video-20230407' of https://source.denx.de/u-boot/custodians/u-boot-video
- fix building sandbox without SDL
- improve tegra DC driver to work with panel ops and implement
native 180 degree panel rotation support
- add T30 support to tegra DC driver
- add DSI driver (based on mainline Linux one with minor
adjustments, only T30 tested)
- add get_display_timing ops to simple panel driver
- extend simple panel driver to use it for MIPI DSI panels
which do not require additional DSI commands for setup
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The DM_REGULATOR symbol has SPL counterpart in:
drivers/power/regulator/Kconfig:config SPL_DM_REGULATOR
Use CONFIG_IS_ENABLED() macro to match on the correct
variant depending on the build stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Re-use simple panel driver for MIPI DSI panels
which do not require additional DSI commands
for setup.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Some cases may require passing display timings from
panel driver. To handle such cases support parsing
device tree panel node for timing subnode.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Google Nexus 7 2012
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features
like ganged mode won't work. Driver is heavily based on
mainline Tegra DSI and re-uses much of its features.
Only T30 is supported for now but T20 support can be added
if any supported devices will be found.
Driver is wrapped as panel driver since Tegra DC driver supports
only panel drivers calls.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Internal video devices like DSI and HDMI controllers
require sending commands into DC register field.
To make this available, lets create platform data,
which is restricted to pass DC regmap only to
pre-defined devices.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Tegra DC driver does not call panel_set_backlight, which can
result in absence of backlight on device. Fix this by calling
panel_set_backlight with BACKLIGHT_DEFAULT just after
panel_enable_backlight.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Unlike 90 and 270 degree rotation, 180 degree rotation is more
common and does not require scaling. Implement it for correct
grouper support.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # Google Nexus 7 2012
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Google Nexus 7 2012
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Check if panel driver has display timings and get those.
If panel driver does not pass timing, try to find timing
under rgb node for backwards compatibility.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
DISP1 clock may use PLLP, PLLC and PLLD as parents.
Instead of hardcoding, lets pass clock and its
parent from device tree. Default parent is PLLP.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Move tegra dc driver to tegra20 directory and also mention
T30 in description of the driver's config option.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
[agust: add commit description]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add pinctrl tables for R8A779G0 V4H SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228, sort sh_pfc_pinconf_set voltage args]
Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
plain PLL2. This should be sufficient until PLL2_VAR is implemented in
the clock core.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver
Treat PLL2 as non-PLL2_VAR for now]
Add pinctrl tables for R8A779F0 S4 SoC.
Based on Linux next 20230228 PFC tables tables up to
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Use RCAR_64 Kconfig, sync with Linux next 20230228]
Add clock tables for R8A779F0 S4 SoC
Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support
for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
Update R-Car Gen4 support in Gen3 clock driver. This patch renames the
V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6
as well as SDSRC clock which use undocumented bits so far, and RPCSRC
clock which uses its own more capable divider table. The Gen4 module
standby and reset tables are also updated.
This patch makes use of union to alias Gen3 and more extensive Gen4
PLL tables, as the driver cannot ever be instantiated on hardware
that would identify itself as both Gen3 and Gen4.
The V3U clock driver is updated to match Gen4 clock driver behavior,
it is augmented with a more extensive PLL table and a valid MODEMR
register offset.
This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver"
from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are
extremely similar. That implementation was in turn based on Linux
commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver")
by Yoshihiro Shimoda .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Use CONFIG_RCAR_64 to make the driver available on both
R-Car Gen3 and R-Car Gen4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Provide the basic HSCIF support for R-Car SoC.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Fill in HSSRR offset for Gen2 and SCBRR calculation for Gen2 and Gen3]
Reviewed-by: Simon Glass <sjg@chromium.org>
Add R-Car Gen4 family support. The basic function is as same as previous
R-Car Generation.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Swap RZ/A1 and Gen4 to keep the GenN sequence, use RCAR_64]
