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dm: adc: add iMX93 ADC support
This commit adds driver for iMX93 ADC.
The driver is implemented using driver model and provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
ADC features:
- channels: 4
- resolution: 12-bit
Signed-off-by: Luca Ellero <l.ellero@asem.it>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
This commit is contained in:
Luca Ellero
Stefano Babic
parent
cb5fe9e336
commit
1ac30d1301
3 changed files with 299 additions and 0 deletions
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@ -63,3 +63,11 @@ config STM32_ADC
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- core driver to deal with common resources
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- child driver to deal with individual ADC resources (declare ADC
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device and associated channels, start/stop conversions)
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config ADC_IMX93
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bool "Enable NXP IMX93 ADC driver"
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help
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This enables basic driver for NXP IMX93 ADC.
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It provides:
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- 4 analog input channels
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- 12-bit resolution
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@ -10,3 +10,4 @@ obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
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obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
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obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
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obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o
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obj-$(CONFIG_ADC_IMX93) += imx93-adc.o
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290
drivers/adc/imx93-adc.c
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290
drivers/adc/imx93-adc.c
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@ -0,0 +1,290 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 ASEM Srl
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* Author: Luca Ellero <l.ellero@asem.it>
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*
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* Originally based on NXP linux-imx kernel v5.15 drivers/iio/adc/imx93_adc.c
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <linux/bitfield.h>
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#include <linux/iopoll.h>
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#include <clk.h>
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#include <adc.h>
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#define IMX93_ADC_MCR 0x00
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#define IMX93_ADC_MSR 0x04
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#define IMX93_ADC_ISR 0x10
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#define IMX93_ADC_IMR 0x20
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#define IMX93_ADC_CIMR0 0x24
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#define IMX93_ADC_CTR0 0x94
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#define IMX93_ADC_NCMR0 0xA4
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#define IMX93_ADC_PCDR0 0x100
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#define IMX93_ADC_PCDR1 0x104
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#define IMX93_ADC_PCDR2 0x108
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#define IMX93_ADC_PCDR3 0x10c
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#define IMX93_ADC_PCDR4 0x110
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#define IMX93_ADC_PCDR5 0x114
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#define IMX93_ADC_PCDR6 0x118
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#define IMX93_ADC_PCDR7 0x11c
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#define IMX93_ADC_CALSTAT 0x39C
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#define IMX93_ADC_MCR_MODE_MASK BIT(29)
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#define IMX93_ADC_MCR_NSTART_MASK BIT(24)
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#define IMX93_ADC_MCR_CALSTART_MASK BIT(14)
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#define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8)
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#define IMX93_ADC_MCR_PWDN_MASK BIT(0)
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#define IMX93_ADC_MSR_CALFAIL_MASK BIT(30)
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#define IMX93_ADC_MSR_CALBUSY_MASK BIT(29)
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#define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0)
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#define IMX93_ADC_ISR_EOC_MASK BIT(1)
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#define IMX93_ADC_IMR_EOC_MASK BIT(1)
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#define IMX93_ADC_IMR_ECH_MASK BIT(0)
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#define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0)
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#define IDLE 0
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#define POWER_DOWN 1
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#define WAIT_STATE 2
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#define BUSY_IN_CALIBRATION 3
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#define SAMPLE 4
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#define CONVERSION 6
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#define IMX93_ADC_MAX_CHANNEL 3
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#define IMX93_ADC_DAT_MASK 0xfff
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#define IMX93_ADC_TIMEOUT 100000
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struct imx93_adc_priv {
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int active_channel;
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void __iomem *regs;
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struct clk ipg_clk;
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};
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static void imx93_adc_power_down(struct imx93_adc_priv *adc)
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{
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u32 mcr, msr;
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int ret;
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
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((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) == POWER_DOWN), 50);
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if (ret == -ETIMEDOUT)
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pr_warn("ADC not in power down mode, current MSR: %x\n", msr);
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}
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static void imx93_adc_power_up(struct imx93_adc_priv *adc)
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{
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u32 mcr;
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/* bring ADC out of power down state, in idle state */
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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}
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static void imx93_adc_config_ad_clk(struct imx93_adc_priv *adc)
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{
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u32 mcr;
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/* put adc in power down mode */
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imx93_adc_power_down(adc);
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/* config the AD_CLK equal to bus clock */
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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/* bring ADC out of power down state, in idle state */
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imx93_adc_power_up(adc);
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}
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static int imx93_adc_calibration(struct imx93_adc_priv *adc)
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{
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u32 mcr, msr;
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int ret;
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/* make sure ADC is in power down mode */
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imx93_adc_power_down(adc);
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/* config SAR controller operating clock */
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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/* bring ADC out of power down state */
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imx93_adc_power_up(adc);
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/*
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* we use the default TSAMP/NRSMPL/AVGEN in MCR,
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* can add the setting of these bit if need
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*/
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/* run calibration */
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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/* wait calibration to be finished */
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ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr,
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!(msr & IMX93_ADC_MSR_CALBUSY_MASK), 2000000);
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if (ret == -ETIMEDOUT) {
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pr_warn("ADC calibration timeout\n");
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return ret;
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}
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/* check whether calbration is successful or not */
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msr = readl(adc->regs + IMX93_ADC_MSR);
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if (msr & IMX93_ADC_MSR_CALFAIL_MASK) {
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pr_warn("ADC calibration failed!\n");
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return -EAGAIN;
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}
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return 0;
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}
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static int imx93_adc_channel_data(struct udevice *dev, int channel,
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unsigned int *data)
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{
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struct imx93_adc_priv *adc = dev_get_priv(dev);
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u32 isr, pcda;
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int ret;
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if (channel != adc->active_channel) {
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pr_err("Requested channel is not active!\n");
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return -EINVAL;
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}
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ret = readl_poll_timeout(adc->regs + IMX93_ADC_ISR, isr,
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(isr & IMX93_ADC_ISR_EOC_MASK), IMX93_ADC_TIMEOUT);
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/* clear interrupts */
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writel(isr, adc->regs + IMX93_ADC_ISR);
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if (ret == -ETIMEDOUT) {
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pr_warn("ADC conversion timeout!\n");
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return ret;
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}
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pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel * 4);
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*data = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda);
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return 0;
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}
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static int imx93_adc_start_channel(struct udevice *dev, int channel)
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{
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struct imx93_adc_priv *adc = dev_get_priv(dev);
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u32 imr, mcr;
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/* config channel mask register */
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writel(1 << channel, adc->regs + IMX93_ADC_NCMR0);
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/* config interrupt mask */
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imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1);
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writel(imr, adc->regs + IMX93_ADC_IMR);
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writel(1 << channel, adc->regs + IMX93_ADC_CIMR0);
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/* config one-shot mode */
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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/* start normal conversion */
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mcr = readl(adc->regs + IMX93_ADC_MCR);
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mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1);
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writel(mcr, adc->regs + IMX93_ADC_MCR);
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adc->active_channel = channel;
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return 0;
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}
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static int imx93_adc_stop(struct udevice *dev)
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{
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struct imx93_adc_priv *adc = dev_get_priv(dev);
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imx93_adc_power_down(adc);
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adc->active_channel = -1;
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return 0;
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}
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static int imx93_adc_probe(struct udevice *dev)
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{
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struct imx93_adc_priv *adc = dev_get_priv(dev);
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unsigned int ret;
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ret = imx93_adc_calibration(adc);
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if (ret < 0)
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return ret;
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imx93_adc_config_ad_clk(adc);
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adc->active_channel = -1;
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return 0;
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}
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static int imx93_adc_of_to_plat(struct udevice *dev)
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{
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struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
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struct imx93_adc_priv *adc = dev_get_priv(dev);
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unsigned int ret;
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adc->regs = dev_read_addr_ptr(dev);
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if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) {
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pr_err("Dev: %s - can't get address!", dev->name);
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return -ENODATA;
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}
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ret = clk_get_by_name(dev, "ipg", &adc->ipg_clk);
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if (ret < 0) {
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pr_err("Can't get ADC ipg clk: %d\n", ret);
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return ret;
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}
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ret = clk_enable(&adc->ipg_clk);
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if(ret) {
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pr_err("Can't enable ADC ipg clk: %d\n", ret);
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return ret;
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}
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uc_pdata->data_mask = IMX93_ADC_DAT_MASK;
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uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
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uc_pdata->data_timeout_us = IMX93_ADC_TIMEOUT;
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/* Mask available channel bits: [0:3] */
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uc_pdata->channel_mask = (2 << IMX93_ADC_MAX_CHANNEL) - 1;
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return 0;
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}
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static const struct adc_ops imx93_adc_ops = {
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.start_channel = imx93_adc_start_channel,
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.channel_data = imx93_adc_channel_data,
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.stop = imx93_adc_stop,
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};
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static const struct udevice_id imx93_adc_ids[] = {
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{ .compatible = "nxp,imx93-adc" },
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{ }
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};
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U_BOOT_DRIVER(imx93_adc) = {
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.name = "imx93-adc",
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.id = UCLASS_ADC,
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.of_match = imx93_adc_ids,
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.ops = &imx93_adc_ops,
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.probe = imx93_adc_probe,
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.of_to_plat = imx93_adc_of_to_plat,
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.priv_auto = sizeof(struct imx93_adc_priv),
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};
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