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video: zynqmp: Enable 1024x768 resolution
Add support for 1024x768 60p resolution and set it up this resolution by default. This resolution is still able to use only one GT line. But for example 800x600 60p has some issues with settings. That's why extend this table by tested resolutions. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/957e1e85a05744326ec2606dadc1af6e69976f37.1684312924.git.michal.simek@amd.com
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dbec4f0b7f
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322c0da86a
2 changed files with 8 additions and 4 deletions
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@ -27,8 +27,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* Maximum supported resolution */
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#define WIDTH 640
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#define HEIGHT 480
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#define WIDTH 1024
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#define HEIGHT 768
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static struct dp_dma dp_dma;
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static struct dp_dma_descriptor cur_desc __aligned(256);
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@ -1995,7 +1995,7 @@ static void init_run_config(struct udevice *dev)
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struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev);
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dp_sub->dp_dma = &dp_dma;
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dp_sub->video_mode = VIDC_VM_640x480_60_P;
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dp_sub->video_mode = VIDC_VM_1024x768_60_P;
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dp_sub->bpc = VIDC_BPC_8;
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dp_sub->color_encode = DP_CENC_RGB;
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dp_sub->use_max_cfg_caps = 1;
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@ -9,6 +9,7 @@
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enum video_mode {
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VIDC_VM_640x480_60_P = 0,
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VIDC_VM_1024x768_60_P = 1,
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};
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enum {
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@ -644,7 +645,7 @@ struct zynqmp_dpsub_priv {
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#define VIDEO_REF_CTRL_DIVISOR0_SHIFT 8
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#define PSS_REF_CLK 0
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#define FPD_CTRL_OFFSET 12
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#define VIDC_VM_NUM_SUPPORTED 1
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#define VIDC_VM_NUM_SUPPORTED 2
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static const u32 vs[4][4] = {
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{ 0x2a, 0x27, 0x24, 0x20 },
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@ -664,6 +665,9 @@ const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] =
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{ VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ,
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{640, 16, 96, 48, 800, 0,
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480, 10, 2, 33, 525, 0, 0, 0, 0, 0} },
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{ VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ,
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{1024, 24, 136, 160, 1344, 0,
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768, 3, 6, 29, 806, 0, 0, 0, 0, 0} },
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};
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const struct av_buf_vid_attribute avbuf_supported_formats[] = {
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