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clk: starfive: pll: Fix to use postdiv1_mask

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There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.

Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Hoegeun Kwon 2023-06-28 19:19:49 +09:00 committed by Leo Yu-Chi Liang
parent 0a8239afa3
commit 422fc299df
1 changed files with 1 additions and 1 deletions
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drivers/clk/starfive/clk-jh7110-pll.c
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@ -185,7 +185,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll,
PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1);
PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv);
PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv);
PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0);
PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0);
PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON);
if (set) {