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net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V

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For RISC-V architeture, hardware maintain the dcache coherency.
Software do not flush the cache. So even cache-line size larger
than descriptor size, driver can work.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Minda Chen 2023-07-20 19:37:27 +08:00 • committed by Leo Yu-Chi Liang
parent a6a0d6a191
commit 3094845165
1 changed files with 3 additions and 1 deletions
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4
drivers/net/rtl8169.c
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@ -311,10 +311,12 @@ static unsigned char rxdata[RX_BUF_LEN];
*
* This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
* the driver to allocate descriptors from a pool of non-cached memory.
*
* Hardware maintain D-cache coherency in RISC-V architecture.
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
#warning cache-line size is larger than descriptor size
#endif
#endif