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riscv: timer: Update the sifive clint timer driver to support aclint
This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
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parent
c9745365f5
commit
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4 changed files with 14 additions and 7 deletions
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@ -12,12 +12,16 @@
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#include <dm/device-internal.h>
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#include <linux/err.h>
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#define CLINT_MTIME_OFFSET 0xbff8
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#define ACLINT_MTIME_OFFSET 0
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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#define MTIME_REG(base, offset) ((ulong)(base) + (offset))
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static u64 notrace sifive_clint_get_count(struct udevice *dev)
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{
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
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return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
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dev_get_driver_data(dev)));
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}
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#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
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@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void)
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*/
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u64 notrace timer_early_get_count(void)
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{
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return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
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return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
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RISCV_MMODE_TIMEROFF));
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}
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#endif
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@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev)
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0" },
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{ .compatible = "sifive,clint0" },
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{ .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
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{ .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
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{ .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
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{ }
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};
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@ -11,8 +11,8 @@
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#define CFG_SYS_SDRAM_BASE 0x80000000
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#define RISCV_MMODE_TIMERBASE 0x2000000
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#define RISCV_MMODE_TIMEROFF 0xbff8
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#define RISCV_MMODE_TIMER_FREQ 1000000
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#define RISCV_SMODE_TIMER_FREQ 1000000
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/* Environment options */
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@ -14,8 +14,8 @@
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#define CFG_SYS_SDRAM_BASE 0x80000000
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#define RISCV_MMODE_TIMERBASE 0x2000000
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#define RISCV_MMODE_TIMEROFF 0xbff8
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#define RISCV_MMODE_TIMER_FREQ 1000000
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#define RISCV_SMODE_TIMER_FREQ 1000000
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/* Environment options */
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@ -9,6 +9,7 @@
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#define _STARFIVE_VISIONFIVE2_H
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#define RISCV_MMODE_TIMERBASE 0x2000000
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#define RISCV_MMODE_TIMEROFF 0xbff8
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#define RISCV_MMODE_TIMER_FREQ 4000000
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#define RISCV_SMODE_TIMER_FREQ 4000000
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