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Merge tag 'u-boot-rockchip-20230728' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

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- Enable pcie support for rk3568;
- Add boards:
        rk3399: Radxa ROCK 4SE;
        rk3328: Orange Pi R1 Plus, Orange Pi R1 Plus LTS
        rk3568: FriendlyARM NanoPi R5S/R5C, Hardkernel ODROID-M1
        rk3588: Edgeble Neu6B
- support OP-TEE with binman;
- support Winbond SPI flash;
- rk3588 usbdp phy support;
- dts and config updates for different boards;
This commit is contained in:
Tom Rini 2023-07-28 10:13:46 -04:00
commit 012174e8c1
111 changed files with 5733 additions and 243 deletions
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7
arch/arm/dts/Makefile
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@ -125,6 +125,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-orangepi-r1-plus.dtb \
rk3328-orangepi-r1-plus-lts.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb
@ -159,6 +161,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-4c-plus.dtb \
rk3399-rock-4se.dtb \
rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \
@ -169,10 +172,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
rk3588-rock-5b.dtb

1
arch/arm/dts/rk3288-u-boot.dtsi
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@ -4,7 +4,6 @@
*/
#include "rockchip-u-boot.dtsi"
#include "rockchip-optee.dtsi"
/ {
aliases {

46
arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi Normal file
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@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
* (C) Copyright 2020 David Bauer
*/
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-666.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
};
};
&gpio0 {
bootph-pre-ram;
};
&pinctrl {
bootph-pre-ram;
};
&sdmmc0m1_pin {
bootph-pre-ram;
};
&pcfg_pull_up_4ma {
bootph-pre-ram;
};
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
};
&gmac2io {
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
};
&spi0 {
spi_flash: spiflash@0 {
bootph-all;
};
};

40
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts Normal file
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@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2016 Xunlong Software. Co., Ltd.
* (http://www.orangepi.org)
*
* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include "rk3328-orangepi-r1-plus.dts"
/ {
model = "Xunlong Orange Pi R1 Plus LTS";
compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
};
&gmac2io {
phy-handle = <&yt8531c>;
tx_delay = <0x19>;
rx_delay = <0x05>;
mdio {
/delete-node/ ethernet-phy@1;
yt8531c: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
motorcomm,clk-out-frequency-hz = <125000000>;
motorcomm,keep-pll-enabled;
motorcomm,auto-sleep-disabled;
pinctrl-0 = <&eth_phy_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <15000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
};

46
arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi Normal file
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@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
* (C) Copyright 2020 David Bauer
*/
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
};
};
&gpio0 {
bootph-pre-ram;
};
&pinctrl {
bootph-pre-ram;
};
&sdmmc0m1_pin {
bootph-pre-ram;
};
&pcfg_pull_up_4ma {
bootph-pre-ram;
};
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
};
&gmac2io {
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
};
&spi0 {
spi_flash: spiflash@0 {
bootph-all;
};
};

373
arch/arm/dts/rk3328-orangepi-r1-plus.dts Normal file
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@ -0,0 +1,373 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Based on rk3328-nanopi-r2s.dts, which is:
* Copyright (c) 2020 David Bauer <mail@david-bauer.net>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "rk3328.dtsi"
/ {
model = "Xunlong Orange Pi R1 Plus";
compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
aliases {
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
gmac_clk: gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
pinctrl-names = "default";
led-0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-2 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
};
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdmmc0m1_pin>;
pinctrl-names = "default";
regulator-name = "vcc_sd";
regulator-boot-on;
vin-supply = <&vcc_io>;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdd_5v_lan: vdd-5v-lan-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lan_vdd_pin>;
pinctrl-names = "default";
regulator-name = "vdd_5v_lan";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
status = "disabled";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
clock_in_out = "input";
phy-handle = <&rtl8211e>;
phy-mode = "rgmii";
phy-supply = <&vcc_io>;
pinctrl-0 = <&rgmiim1_pins>;
pinctrl-names = "default";
snps,aal;
rx_delay = <0x18>;
tx_delay = <0x24>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8211e: ethernet-phy@1 {
reg = <1>;
pinctrl-0 = <&eth_phy_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
};
&i2c1 {
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-0 = <&pmic_int_l>;
pinctrl-names = "default";
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_sys>;
regulators {
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&io_domains {
pmuio-supply = <&vcc_io>;
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
vccio3-supply = <&vcc_io>;
vccio4-supply = <&vcc_io>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
status = "okay";
};
&pinctrl {
gmac2io {
eth_phy_reset_pin: eth-phy-reset-pin {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
leds {
lan_led_pin: lan-led-pin {
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
sys_led_pin: sys-led-pin {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
wan_led_pin: wan-led-pin {
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lan {
lan_vdd_pin: lan-vdd-pin {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm2 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
disable-wp;
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&uart2 {
status = "okay";
};
&usb20_otg {
dr_mode = "host";
status = "okay";
};
&usbdrd3 {
dr_mode = "host";
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* Second port is for USB 3.0 */
rtl8153: device@2 {
compatible = "usbbda,8153";
reg = <2>;
};
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};

3
arch/arm/dts/rk3399-rock-4c-plus.dts
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@ -548,9 +548,8 @@
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs200-1_8v;
non-removable;
mmc-hs400-enhanced-strobe;
status = "okay";
};

6
arch/arm/dts/rk3399-rock-4se-u-boot.dtsi Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"

65
arch/arm/dts/rk3399-rock-4se.dts Normal file
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@ -0,0 +1,65 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
*/
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
#include "rk3399-t-opp.dtsi"
/ {
model = "Radxa ROCK 4SE";
compatible = "radxa,rock-4se", "rockchip,rk3399";
aliases {
mmc2 = &sdio0;
};
};
&pinctrl {
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio0 {
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&uart0 {
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};
&vcc5v0_host {
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};

5
arch/arm/dts/rk3399-rock-pi-4.dtsi
View file

@ -9,7 +9,6 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
aliases {
@ -645,9 +644,9 @@
};
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};

1
arch/arm/dts/rk3399-rock-pi-4a.dts
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@ -6,6 +6,7 @@
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Radxa ROCK Pi 4A";

1
arch/arm/dts/rk3399-rock-pi-4c.dts
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@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Radxa ROCK Pi 4C";

10
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
View file

@ -46,7 +46,17 @@
<&pmucru CLK_RTC32K_FRAC>;
};
&dsi_dphy0 {
status = "okay";
};
&dsi0 {
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2m1_xfer>;
pinctrl-names = "default";
status = "okay";
};

3
arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi Normal file
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@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-nanopi-r5s-u-boot.dtsi"

112
arch/arm/dts/rk3568-nanopi-r5c.dts Normal file
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@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include "rk3568-nanopi-r5s.dtsi"
/ {
model = "FriendlyElec NanoPi R5C";
compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&reset_button_pin>;
button-reset {
debounce-interval = <50>;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
label = "reset";
linux,code = <KEY_RESTART>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
led-lan {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
};
power_led: led-power {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
linux,default-trigger = "heartbeat";
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
};
led-wan {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
};
led-wlan {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
};
};
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie20_reset_pin>;
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie3x1 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie3x2 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
gpio-leds {
lan_led_pin: lan-led-pin {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
power_led_pin: power-led-pin {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wan_led_pin: wan-led-pin {
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_led_pin: wlan-led-pin {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie20_reset_pin: pcie20-reset-pin {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rockchip-key {
reset_button_pin: reset-button-pin {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
*/
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
};
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include "rk3568-nanopi-r5s.dtsi"
/ {
model = "FriendlyElec NanoPi R5S";
compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
led-lan1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
};
led-lan2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
};
power_led: led-power {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
linux,default-trigger = "heartbeat";
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
};
led-wan {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
};
};
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
};
};
&pcie2x1 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pcie3x1 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie3x2 {
num-lanes = <1>;
num-ib-windows = <8>;
num-ob-windows = <8>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-leds {
lan1_led_pin: lan1-led-pin {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
lan2_led_pin: lan2-led-pin {
rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
};
power_led_pin: power-led-pin {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wan_led_pin: wan-led-pin {
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyelec.com)
*
* Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
aliases {
mmc0 = &sdmmc0;
mmc1 = &sdhci;
};
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
vdd_usbc: vdd-usbc-regulator {
compatible = "regulator-fixed";
regulator-name = "vdd_usbc";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdd_usbc>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vdd_usbc>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
startup-delay-us = <200000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vdd_usbc>;
};
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
regulator-name = "vcc5v0_usb_host";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-name = "vcc5v0_usb_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
};
pcie30_avdd0v9: pcie30-avdd0v9-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
pcie30_avdd1v8: pcie30-avdd1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_sys>;
};
};
&combphy0 {
status = "okay";
};
&combphy1 {
status = "okay";
};
&combphy2 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c5 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
clock-output-names = "rtcic_32kout";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
wakeup-source;
};
};
&i2s0_8ch {
status = "okay";
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_usb_host_en: vcc5v0-usb-host-en {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
status = "okay";
};
&sdmmc0 {
max-frequency = <150000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
extcon = <&usb2phy0>;
dr_mode = "host";
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1_otg {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
};
&fspi_dual_io_pins {
bootph-all;
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
};
&sfc {
bootph-pre-ram;
u-boot,spl-sfc-no-dma;
flash@0 {
bootph-pre-ram;
};
};
&uart2 {
bootph-all;
clock-frequency = <24000000>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Hardkernel Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
/ {
model = "Hardkernel ODROID-M1";
compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
i2c0 = &i2c3;
i2c3 = &i2c0;
mmc0 = &sdhci;
mmc1 = &sdmmc0;
serial0 = &uart1;
serial1 = &uart0;
};
chosen {
stdout-path = "serial2:1500000n8";
};
dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_receiver_pin>;
};
leds {
compatible = "gpio-leds";
led_power: led-0 {
gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
default-state = "keep";
linux,default-trigger = "default-on";
pinctrl-names = "default";
pinctrl-0 = <&led_power_pin>;
};
led_work: led-1 {
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
pinctrl-names = "default";
pinctrl-0 = <&led_work_pin>;
};
};
rk809-sound {
compatible = "simple-audio-card";
pinctrl-names = "default";
pinctrl-0 = <&hp_det_pin>;
simple-audio-card,name = "Analog RK817";
simple-audio-card,format = "i2s";
simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Headphone", "Headphones",
"Speaker", "Speaker";
simple-audio-card,routing =
"Headphones", "HPOL",
"Headphones", "HPOR",
"Speaker", "SPKO";
simple-audio-card,cpu {
sound-dai = <&i2s1_8ch>;
};
simple-audio-card,codec {
sound-dai = <&rk809>;
};
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
enable-active-high;
gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en_pin>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <5000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_host";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_otg";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0 {
/* Used for USB3 */
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&combphy1 {
/* Used for USB3 */
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&combphy2 {
/* used for SATA */
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
status = "okay";
tx_delay = <0x4f>;
rx_delay = <0x2d>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vdda0v9_image>;
avdd-1v8-supply = <&vcca1v8_image>;
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
vdd_cpu: regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x1c>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
rockchip,system-power-controller;
#sound-dai-cells = <0>;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc5-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
wakeup-source;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8: DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_image: LDO_REG1 {
regulator-name = "vdda0v9_image";
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v9: LDO_REG2 {
regulator-name = "vdda_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-name = "vdda0v9_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-name = "vccio_acodec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-name = "vcc3v3_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca_1v8: LDO_REG7 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pmu: LDO_REG8 {
regulator-name = "vcca1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3: SWITCH_REG1 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
rockchip,trcm-sync-tx-only;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
&pcie30phy {
status = "okay";
};
&pcie3x2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pin>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
fspi {
fspi_dual_io_pins: fspi-dual-io-pins {
rockchip,pins =
/* fspi_clk */
<1 RK_PD0 1 &pcfg_pull_none>,
/* fspi_cs0n */
<1 RK_PD3 1 &pcfg_pull_none>,
/* fspi_d0 */
<1 RK_PD1 1 &pcfg_pull_none>,
/* fspi_d1 */
<1 RK_PD2 1 &pcfg_pull_none>;
};
};
ir-receiver {
ir_receiver_pin: ir-receiver-pin {
/* external pullup to VCC3V3_SYS */
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_power_pin: led-power-pin {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_work_pin: led-work-pin {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_reset_pin: pcie-reset-pin {
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rk809 {
hp_det_pin: hp-det-pin {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio2-supply = <&vcc_1v8>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
};
&sata2 {
status = "okay";
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr50;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sfc {
/* Dual I/O mode as the D2 pin conflicts with the eMMC */
pinctrl-0 = <&fspi_dual_io_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0x0 0xe0000>;
};
partition@e0000 {
label = "U-Boot Env";
reg = <0xe0000 0x20000>;
};
partition@100000 {
label = "U-Boot";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "splash";
reg = <0x300000 0x100000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x400000 0xc00000>;
};
};
};
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy0_otg {
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

14
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
View file

@ -36,8 +36,22 @@
bootph-all;
};
&pcie2x1 {
pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
};
&pcie3x2 {
pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>;
};
&pinctrl {
bootph-all;
pcie {
pcie3x2_reset_h: pcie3x2-reset-h {
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pcfg_pull_none {

14
arch/arm/dts/rk3568.dtsi
View file

@ -94,9 +94,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0400000 0x0 0x00400000>,
<0x0 0xfe270000 0x0 0x00010000>,
<0x3 0x7f000000 0x0 0x01000000>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
<0x0 0xf2000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@ -146,9 +147,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0800000 0x0 0x00400000>,
<0x0 0xfe280000 0x0 0x00010000>,
<0x3 0xbf000000 0x0 0x01000000>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
<0x0 0xf0000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";

7
arch/arm/dts/rk356x.dtsi
View file

@ -951,7 +951,7 @@
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc0000000 0x0 0x00400000>,
<0x0 0xfe260000 0x0 0x00010000>,
<0x3 0x3f000000 0x0 0x01000000>;
<0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@ -980,8 +980,9 @@
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;

22
arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include "rk3588j-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc;
};
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc;
};
};
&sdmmc {
bus-width = <4>;
status = "okay";
};

27
arch/arm/dts/rk3588-edgeble-neu6b-io.dts Normal file
View file

@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
/dts-v1/;
#include "rk3588j.dtsi"
#include "rk3588-edgeble-neu6b.dtsi"
/ {
model = "Edgeble Neu6B IO Board";
compatible = "edgeble,neural-compute-module-6b-io",
"edgeble,neural-compute-module-6b", "rockchip,rk3588";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};

32
arch/arm/dts/rk3588-edgeble-neu6b.dtsi Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
*/
/ {
compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
aliases {
mmc0 = &sdhci;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};

197
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
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@ -7,6 +7,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/usb/pd.h>
/ {
aliases {
@ -18,6 +19,25 @@
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_usbdcin: vcc5v0-usbdcin {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usbdcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
@ -29,6 +49,28 @@
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usbdcin>;
};
vbus5v0_typec: vbus5v0-typec {
compatible = "regulator-fixed";
regulator-name = "vbus5v0_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
};
};
&combphy0_ps {
@ -85,6 +127,16 @@
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
};
typec5v_pwren: typec5v-pwren {
rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pcfg_pull_none {
@ -168,6 +220,15 @@
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
rockchip,typec-vbus-det;
status = "okay";
};
&u2phy2 {
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
reset-names = "phy", "apb";
@ -209,3 +270,139 @@
status = "okay";
};
&usbdp_phy0 {
orientation-switch;
svid = <0xff01>;
sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
usbdp_phy0_dp_altmode_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&dp_altmode_mux>;
};
};
};
&usbdp_phy0_u3 {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdp_phy1 {
rockchip,dp-lane-mux = <2 3>;
status = "okay";
};
&usbdp_phy1_u3 {
status = "okay";
};
&usbdrd3_1 {
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
status = "okay";
};
&i2c4 {
pinctrl-0 = <&i2c4m1_xfer>;
status = "okay";
usbc0: fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
altmodes {
#address-cells = <1>;
#size-cells = <0>;
altmode@0 {
reg = <0>;
svid = <0xff01>;
vdo = <0xffffffff>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
port@1 {
reg = <1>;
dp_altmode_mux: endpoint {
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
};
};
};
};
};
};

152
arch/arm/dts/rk3588-rock-5b.dts
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@ -2,6 +2,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "rk3588.dtsi"
/ {
@ -17,6 +18,31 @@
stdout-path = "serial2:1500000n8";
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 95 145 195 255>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
#cooling-cells = <2>;
};
sound {
compatible = "audio-graph-card";
label = "Analog";
widgets = "Microphone", "Mic Jack",
"Headphone", "Headphones";
routing = "MIC2", "Mic Jack",
"Headphones", "HPOL",
"Headphones", "HPOR";
dais = <&i2s0_8ch_p0>;
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hp_detect>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@ -27,6 +53,132 @@
};
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c7 {
status = "okay";
es8316: audio-codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s0_8ch_p0_0>;
};
};
};
};
&i2s0_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
status = "okay";
i2s0_8ch_p0: port {
i2s0_8ch_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sound {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;

93
arch/arm/dts/rk3588-u-boot.dtsi
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@ -5,3 +5,96 @@
#include "rockchip-u-boot.dtsi"
#include "rk3588s-u-boot.dtsi"
/ {
usbdrd3_1: usbdrd3_1 {
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
clock-names = "ref", "suspend", "bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usbdrd_dwc3_1: usb@fc400000 {
compatible = "snps,dwc3";
reg = <0x0 0xfc400000 0x0 0x400000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&power RK3588_PD_USB>;
resets = <&cru SRST_A_USB3OTG1>;
reset-names = "usb3-otg";
dr_mode = "host";
phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
};
};
usbdpphy1_grf: syscon@fd5cc000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5cc000 0x0 0x4000>;
};
usb2phy1_grf: syscon@fd5d4000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5d4000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy1: usb2-phy@4000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x4000 0x10>;
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
reset-names = "phy", "apb";
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
#clock-cells = <0>;
rockchip,usbctrl-grf = <&usb_grf>;
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
rockchip,u2phy-grf = <&usb2phy1_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
rockchip,vo-grf = <&vo0_grf>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY1_IMMORTAL>,
<&cru PCLK_USBDPPHY1>,
<&u2phy1>;
clock-names = "refclk", "immortal", "pclk", "utmi";
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
<&cru SRST_P_USBDPPHY1>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
status = "disabled";
usbdp_phy1_dp: dp-port {
#phy-cells = <0>;
status = "disabled";
};
usbdp_phy1_u3: usb3-port {
#phy-cells = <0>;
status = "disabled";
};
};
};

68
arch/arm/dts/rk3588.dtsi
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@ -7,6 +7,74 @@
#include "rk3588-pinctrl.dtsi"
/ {
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 22>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO0>;
resets = <&cru SRST_M_I2S8_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s6_8ch: i2s@fddf4000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf4000 0x0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 4>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S6_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s7_8ch: i2s@fddf8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf8000 0x0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 21>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S7_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s10_8ch: i2s@fde00000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfde00000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 24>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S10_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;

6
arch/arm/dts/rk3588j-u-boot.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
#include "rk3588-u-boot.dtsi"

7
arch/arm/dts/rk3588j.dtsi Normal file
View file

@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3588.dtsi"

117
arch/arm/dts/rk3588s-u-boot.dtsi
View file

@ -13,6 +13,37 @@
status = "okay";
};
usbdrd3_0: usbdrd3_0 {
compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
<&cru ACLK_USB3OTG0>;
clock-names = "ref", "suspend", "bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usbdrd_dwc3_0: usb@fc000000 {
compatible = "snps,dwc3";
reg = <0x0 0xfc000000 0x0 0x400000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&power RK3588_PD_USB>;
resets = <&cru SRST_A_USB3OTG0>;
reset-names = "usb3-otg";
dr_mode = "otg";
phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
quirk-skip-phy-init;
};
};
usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
@ -64,6 +95,33 @@
reg = <0x0 0xfd5bc000 0x0 0x100>;
};
usb2phy0_grf: syscon@fd5d0000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5d0000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy0: usb2-phy@0 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x0 0x10>;
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
reset-names = "phy", "apb";
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
#clock-cells = <0>;
rockchip,usbctrl-grf = <&usb_grf>;
status = "disabled";
u2phy0_otg: otg-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
@ -87,6 +145,17 @@
};
};
vo0_grf: syscon@fd5a6000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a6000 0x0 0x2000>;
clocks = <&cru PCLK_VO0GRF>;
};
usb_grf: syscon@fd5ac000 {
compatible = "rockchip,rk3588-usb-grf", "syscon";
reg = <0x0 0xfd5ac000 0x0 0x4000>;
};
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
@ -110,6 +179,11 @@
};
};
usbdpphy0_grf: syscon@fd5c8000 {
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
reg = <0x0 0xfd5c8000 0x0 0x4000>;
};
pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;
@ -174,24 +248,43 @@
status = "disabled";
};
otp: nvmem@fecc0000 {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc0000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
cpu_id: id@7 {
reg = <0x07 0x10>;
};
};
rng: rng@fe378000 {
compatible = "rockchip,trngv1";
reg = <0x0 0xfe378000 0x0 0x200>;
status = "disabled";
};
usbdp_phy0: phy@fed80000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed80000 0x0 0x10000>;
rockchip,u2phy-grf = <&usb2phy0_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
rockchip,vo-grf = <&vo0_grf>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY0_IMMORTAL>,
<&cru PCLK_USBDPPHY0>,
<&u2phy0>;
clock-names = "refclk", "immortal", "pclk", "utmi";
resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
<&cru SRST_USBDP_COMBO_PHY0_CMN>,
<&cru SRST_USBDP_COMBO_PHY0_LANE>,
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
<&cru SRST_P_USBDPPHY0>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
status = "disabled";
usbdp_phy0_dp: dp-port {
#phy-cells = <0>;
status = "disabled";
};
usbdp_phy0_u3: usb3-port {
#phy-cells = <0>;
status = "disabled";
};
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;

234
arch/arm/dts/rk3588s.dtsi
View file

@ -60,6 +60,8 @@
enable-method = "psci";
capacity-dmips-mhz = <530>;
clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clock-rates = <816000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
@ -136,6 +138,8 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clock-rates = <816000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@ -174,6 +178,8 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <816000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
@ -222,6 +228,8 @@
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -230,6 +238,8 @@
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -238,6 +248,8 @@
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -246,6 +258,8 @@
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -254,6 +268,8 @@
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -262,6 +278,8 @@
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -270,6 +288,8 @@
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -278,6 +298,8 @@
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -286,6 +308,8 @@
cache-size = <3145728>;
cache-line-size = <64>;
cache-sets = <4096>;
cache-level = <3>;
cache-unified;
};
};
@ -304,10 +328,6 @@
scmi_clk: protocol@14 {
reg = <0x14>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
<&scmi_clk SCMI_CLK_CPUB23>;
assigned-clock-rates = <1200000000>,
<1200000000>;
#clock-cells = <1>;
};
@ -414,7 +434,7 @@
<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
<&cru CLK_GPU>;
assigned-clock-rates =
<100000000>, <786432000>,
<1100000000>, <786432000>,
<850000000>, <1188000000>,
<702000000>,
<400000000>, <500000000>,
@ -1132,6 +1152,103 @@
status = "disabled";
};
i2s0_8ch: i2s@fe470000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfe470000 0x0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
dmas = <&dmac0 0>, <&dmac0 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdi1
&i2s0_sdi2
&i2s0_sdi3
&i2s0_sdo0
&i2s0_sdo1
&i2s0_sdo2
&i2s0_sdo3>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s1_8ch: i2s@fe480000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfe480000 0x0 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac0 2>, <&dmac0 3>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_lrck
&i2s1m0_sclk
&i2s1m0_sdi0
&i2s1m0_sdi1
&i2s1m0_sdi2
&i2s1m0_sdi3
&i2s1m0_sdo0
&i2s1m0_sdo1
&i2s1m0_sdo2
&i2s1m0_sdo3>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s2_2ch: i2s@fe490000 {
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xfe490000 0x0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
clock-names = "i2s_clk", "i2s_hclk";
assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac1 0>, <&dmac1 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s2m1_lrck
&i2s2m1_sclk
&i2s2m1_sdi
&i2s2m1_sdo>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s3_2ch: i2s@fe4a0000 {
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xfe4a0000 0x0 0x1000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
clock-names = "i2s_clk", "i2s_hclk";
assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac1 2>, <&dmac1 3>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s3_lrck
&i2s3_sclk
&i2s3_sdi
&i2s3_sdo>;
#sound-dai-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@fe600000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
@ -1141,7 +1258,24 @@
mbi-alias = <0x0 0xfe610000>;
mbi-ranges = <424 56>;
msi-controller;
ranges;
#address-cells = <2>;
#interrupt-cells = <4>;
#size-cells = <2>;
its0: msi-controller@fe640000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfe640000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
its1: msi-controller@fe660000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfe660000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
ppi-partitions {
ppi_partition0: interrupt-partition-0 {
@ -1241,6 +1375,22 @@
status = "disabled";
};
timer0: timer@feae0000 {
compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
reg = <0x0 0xfeae0000 0x0 0x20>;
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
clock-names = "pclk", "timer";
};
wdt: watchdog@feaf0000 {
compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
reg = <0x0 0xfeaf0000 0x0 0x100>;
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
};
spi0: spi@feb00000 {
compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
reg = <0x0 0xfeb00000 0x0 0x1000>;
@ -1572,6 +1722,26 @@
status = "disabled";
};
tsadc: tsadc@fec00000 {
compatible = "rockchip,rk3588-tsadc";
reg = <0x0 0xfec00000 0x0 0x400>;
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru CLK_TSADC>;
assigned-clock-rates = <2000000>;
resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
reset-names = "tsadc-apb", "tsadc";
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
pinctrl-0 = <&tsadc_gpio_func>;
pinctrl-1 = <&tsadc_shut>;
pinctrl-names = "gpio", "otpout";
#thermal-sensor-cells = <1>;
status = "disabled";
};
i2c6: i2c@fec80000 {
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfec80000 0x0 0x1000>;
@ -1627,6 +1797,60 @@
status = "disabled";
};
otp: efuse@fecc0000 {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc0000 0x0 0x400>;
clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
<&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
clock-names = "otp", "apb_pclk", "phy", "arb";
resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
<&cru SRST_OTPC_ARB>;
reset-names = "otp", "apb", "arb";
#address-cells = <1>;
#size-cells = <1>;
cpu_code: cpu-code@2 {
reg = <0x02 0x2>;
};
otp_id: id@7 {
reg = <0x07 0x10>;
};
cpub0_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
cpub1_leakage: cpu-leakage@18 {
reg = <0x18 0x1>;
};
cpul_leakage: cpu-leakage@19 {
reg = <0x19 0x1>;
};
log_leakage: log-leakage@1a {
reg = <0x1a 0x1>;
};
gpu_leakage: gpu-leakage@1b {
reg = <0x1b 0x1>;
};
otp_cpu_version: cpu-version@1c {
reg = <0x1c 0x1>;
bits = <3 3>;
};
npu_leakage: npu-leakage@28 {
reg = <0x28 0x1>;
};
codec_leakage: codec-leakage@29 {
reg = <0x29 0x1>;
};
};
dmac2: dma-controller@fed10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfed10000 0x0 0x4000>;

64
arch/arm/dts/rockchip-optee.dtsi
View file

@ -1,64 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Google LLC
*/
#include <config.h>
#if defined(CONFIG_HAS_ROM) && defined(CONFIG_FIT)
&binman {
itb {
filename = "u-boot.itb";
fit {
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
description = "FIT image with OP-TEE support";
#address-cells = <1>;
images {
uboot {
description = "U-Boot";
type = "standalone";
os = "U-Boot";
arch = "arm";
compression = "none";
load = <CONFIG_TEXT_BASE>;
u-boot-nodtb {
};
};
optee {
description = "OP-TEE";
type = "firmware";
arch = "arm";
os = "tee";
compression = "none";
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
blob-ext {
filename = "tee.bin";
};
};
fdt {
description = CONFIG_SYS_BOARD;
type = "flat_dt";
compression = "none";
u-boot-dtb {
};
};
};
configurations {
default = "conf";
conf {
description = CONFIG_SYS_BOARD;
firmware = "optee";
loadables = "uboot";
fdt = "fdt";
};
};
};
};
};
#endif

38
arch/arm/dts/rockchip-u-boot.dtsi
View file

@ -33,9 +33,13 @@
};
};
#if defined(CONFIG_SPL_FIT) && defined(CONFIG_ARM64)
#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
fit: fit {
#ifdef CONFIG_ARM64
description = "FIT image for U-Boot with bl31 (TF-A)";
#else
description = "FIT image with OP-TEE";
#endif
#address-cells = <1>;
fit,fdt-list = "of-list";
filename = "u-boot.itb";
@ -44,10 +48,14 @@
offset = <CONFIG_SPL_PAD_TO>;
images {
u-boot {
description = "U-Boot (64-bit)";
description = "U-Boot";
type = "standalone";
os = "U-Boot";
#ifdef CONFIG_ARM64
arch = "arm64";
#else
arch = "arm";
#endif
compression = "none";
load = <CONFIG_TEXT_BASE>;
entry = <CONFIG_TEXT_BASE>;
@ -60,6 +68,7 @@
#endif
};
#ifdef CONFIG_ARM64
@atf-SEQ {
fit,operation = "split-elf";
description = "ARM Trusted Firmware";
@ -99,6 +108,25 @@
};
#endif
};
#else
op-tee {
description = "OP-TEE";
type = "tee";
arch = "arm";
os = "tee";
compression = "none";
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
tee-os {
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
};
#endif
};
#endif
@fdt-SEQ {
description = "fdt-NAME";
@ -117,7 +145,11 @@
@config-SEQ {
description = "NAME.dtb";
fdt = "fdt-SEQ";
#ifdef CONFIG_ARM64
fit,firmware = "atf-1", "u-boot";
#else
fit,firmware = "op-tee", "u-boot";
#endif
fit,loadables;
};
};
@ -150,7 +182,7 @@
};
};
#ifdef CONFIG_ARM64
#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
fit {
type = "blob";
filename = "u-boot.itb";

2
arch/arm/mach-rockchip/Kconfig
View file

@ -106,6 +106,7 @@ config ROCKCHIP_RK322X
imply ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL
imply SPL_ROCKCHIP_COMMON_BOARD
select SPL_OPTEE_IMAGE if SPL_FIT
imply TPL_SERIAL
imply TPL_ROCKCHIP_COMMON_BOARD
select TPL_LIBCOMMON_SUPPORT
@ -250,7 +251,6 @@ config ROCKCHIP_RK3399
imply PRE_CONSOLE_BUFFER
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_SDRAM_COMMON
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
imply SPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL
imply TPL_LIBCOMMON_SUPPORT

8
arch/arm/mach-rockchip/rk3568/Kconfig
View file

@ -17,6 +17,11 @@ config TARGET_ANBERNIC_RGXX3_RK3566
and RG503. The correct device tree name will automatically
be selected by the bootloader.
config TARGET_ODROID_M1_RK3568
bool "ODROID-M1"
help
Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
endchoice
config ROCKCHIP_BOOT_MODE_REG
@ -29,9 +34,10 @@ config SYS_SOC
default "rk3568"
config SYS_MALLOC_F_LEN
default 0x2000
default 0x20000
source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
source "board/hardkernel/odroid_m1/Kconfig"
endif

20
arch/arm/mach-rockchip/rk3588/Kconfig
View file

@ -10,15 +10,25 @@ config TARGET_RK3588_NEU6
bool "Edgeble Neural Compute Module 6(Neu6) SoM"
select BOARD_LATE_INIT
help
Neu6:
Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module
Neu6A:
Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
Neu6-IO:
Neural Compute Module 6(Neu6) IO board is an industrial form factor
Neu6A-IO:
Neural Compute Module 6A(Neu6A) IO board is an industrial form factor
IO board and Neu6a needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 6(Neu6) IO platform.
create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform.
Neu6B:
Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
based on Rockchip RK3588J from Edgeble AI.
Neu6A-IO:
Neural Compute Module 6B(Neu6B) IO board is an industrial form factor
IO board and Neu6a needs to mount on top of this IO board in order to
create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform.
config TARGET_ROCK5B_RK3588
config TARGET_ROCK5B_RK3588
bool "Radxa ROCK5B RK3588 board"
select BOARD_LATE_INIT

322
board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
View file

@ -6,25 +6,37 @@
#include <abuf.h>
#include <adc.h>
#include <asm/io.h>
#include <display.h>
#include <dm.h>
#include <dm/lists.h>
#include <env.h>
#include <fdt_support.h>
#include <linux/delay.h>
#include <mipi_dsi.h>
#include <mmc.h>
#include <panel.h>
#include <pwm.h>
#include <rng.h>
#include <stdlib.h>
#include <mmc.h>
#include <env.h>
#include <video_bridge.h>
#define GPIO0_BASE 0xfdd60000
#define GPIO4_BASE 0xfe770000
#define GPIO_SWPORT_DR_L 0x0000
#define GPIO_SWPORT_DR_H 0x0004
#define GPIO_SWPORT_DDR_L 0x0008
#define GPIO_SWPORT_DDR_H 0x000c
#define GPIO_A5 BIT(5)
#define GPIO_A6 BIT(6)
#define GPIO_A0 BIT(0)
#define GPIO_C5 BIT(5)
#define GPIO_C6 BIT(6)
#define GPIO_C7 BIT(7)
#define GPIO_WRITEMASK(bits) ((bits) << 16)
#define DTB_DIR "rockchip/"
struct rg3xx_model {
const u16 adc_value;
const char *board;
const char *board_name;
const char *fdtfile;
@ -34,49 +46,74 @@ enum rgxx3_device_id {
RG353M,
RG353P,
RG353V,
RG353VS,
RG503,
/* Devices with duplicate ADC value */
RG353PS,
RG353VS,
};
static const struct rg3xx_model rg3xx_model_details[] = {
[RG353M] = {
517, /* Observed average from device */
"rk3566-anbernic-rg353m",
"RG353M",
DTB_DIR "rk3566-anbernic-rg353m.dtb",
DTB_DIR "rk3566-anbernic-rg353p.dtb", /* Identical devices */
},
[RG353P] = {
860, /* Documented value of 860 */
"rk3566-anbernic-rg353p",
"RG353P",
DTB_DIR "rk3566-anbernic-rg353p.dtb",
},
[RG353V] = {
695, /* Observed average from device */
"rk3566-anbernic-rg353v",
"RG353V",
DTB_DIR "rk3566-anbernic-rg353v.dtb",
},
[RG353VS] = {
"rk3566-anbernic-rg353vs",
"RG353VS",
DTB_DIR "rk3566-anbernic-rg353vs.dtb",
},
[RG503] = {
1023, /* Observed average from device */
"rk3566-anbernic-rg503",
"RG503",
DTB_DIR "rk3566-anbernic-rg503.dtb",
},
/* Devices with duplicate ADC value */
[RG353PS] = {
860, /* Observed average from device */
"rk3566-anbernic-rg353ps",
"RG353PS",
DTB_DIR "rk3566-anbernic-rg353ps.dtb",
},
[RG353VS] = {
695, /* Gathered from second hand information */
"rk3566-anbernic-rg353vs",
"RG353VS",
DTB_DIR "rk3566-anbernic-rg353vs.dtb",
},
};
struct rg353_panel {
const u16 id;
const char *panel_compat;
};
static const struct rg353_panel rg353_panel_details[] = {
{ .id = 0x3052, .panel_compat = "newvision,nv3051d"},
{ .id = 0x3821, .panel_compat = "anbernic,rg353v-panel-v2"},
};
/*
* Start LED very early so user knows device is on. Set color
* to amber.
* to red.
*/
void spl_board_init(void)
{
/* Set GPIO0_A5 and GPIO0_A6 to output. */
writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5),
/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
(GPIO_C7 | GPIO_C6 | GPIO_C5),
(GPIO0_BASE + GPIO_SWPORT_DDR_H));
/* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */
writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6,
/* Set GPIO0_C5 and GPIO_C6 to 0 and GPIO0_C7 to 1. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C7,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
}
@ -126,15 +163,159 @@ void __maybe_unused startup_buzz(void)
pwm_set_enable(dev, 0, 0);
}
/*
* Provide the bare minimum to identify the panel for the RG353
* series. Since we don't have a working framebuffer device, no
* need to init the panel; just identify it and provide the
* clocks so we know what to set the different clock values to.
*/
static const struct display_timing rg353_default_timing = {
.pixelclock.typ = 24150000,
.hactive.typ = 640,
.hfront_porch.typ = 40,
.hback_porch.typ = 80,
.hsync_len.typ = 2,
.vactive.typ = 480,
.vfront_porch.typ = 18,
.vback_porch.typ = 28,
.vsync_len.typ = 2,
.flags = DISPLAY_FLAGS_HSYNC_HIGH |
DISPLAY_FLAGS_VSYNC_HIGH,
};
static int anbernic_rg353_panel_get_timing(struct udevice *dev,
struct display_timing *timings)
{
memcpy(timings, &rg353_default_timing, sizeof(*timings));
return 0;
}
static int anbernic_rg353_panel_probe(struct udevice *dev)
{
struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
plat->lanes = 4;
plat->format = MIPI_DSI_FMT_RGB888;
plat->mode_flags = MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_EOT_PACKET |
MIPI_DSI_MODE_LPM;
return 0;
}
static const struct panel_ops anbernic_rg353_panel_ops = {
.get_display_timing = anbernic_rg353_panel_get_timing,
};
U_BOOT_DRIVER(anbernic_rg353_panel) = {
.name = "anbernic_rg353_panel",
.id = UCLASS_PANEL,
.ops = &anbernic_rg353_panel_ops,
.probe = anbernic_rg353_panel_probe,
.plat_auto = sizeof(struct mipi_dsi_panel_plat),
};
int rgxx3_detect_display(void)
{
struct udevice *dev;
struct mipi_dsi_device *dsi;
struct mipi_dsi_panel_plat *mplat;
const struct rg353_panel *panel;
int ret = 0;
int i;
u8 panel_id[2];
/*
* Take panel out of reset status.
* Set GPIO4_A0 to output.
*/
writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0,
(GPIO4_BASE + GPIO_SWPORT_DDR_L));
/* Set GPIO4_A0 to 1. */
writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0,
(GPIO4_BASE + GPIO_SWPORT_DR_L));
/* Probe the DSI controller. */
ret = uclass_get_device_by_name(UCLASS_VIDEO_BRIDGE,
"dsi@fe060000", &dev);
if (ret) {
printf("DSI host not probed: %d\n", ret);
return ret;
}
/* Probe the DSI panel. */
ret = device_bind_driver_to_node(dev, "anbernic_rg353_panel",
"anbernic_rg353_panel",
dev_ofnode(dev), NULL);
if (ret) {
printf("Failed to probe RG353 panel: %d\n", ret);
return ret;
}
/*
* Attach the DSI controller which will also probe and attach
* the DSIDPHY.
*/
ret = video_bridge_attach(dev);
if (ret) {
printf("Failed to attach DSI controller: %d\n", ret);
return ret;
}
/*
* Get the panel which should have already been probed by the
* video_bridge_attach() function.
*/
ret = uclass_first_device_err(UCLASS_PANEL, &dev);
if (ret) {
printf("Panel device error: %d\n", ret);
return ret;
}
/* Now call the panel via DSI commands to get the panel ID. */
mplat = dev_get_plat(dev);
dsi = mplat->device;
mipi_dsi_set_maximum_return_packet_size(dsi, sizeof(panel_id));
ret = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_ID, &panel_id,
sizeof(panel_id));
if (ret < 0) {
printf("Unable to read panel ID: %d\n", ret);
return ret;
}
/* Get the correct panel compatible from the table. */
for (i = 0; i < ARRAY_SIZE(rg353_panel_details); i++) {
if (rg353_panel_details[i].id == ((panel_id[0] << 8) |
panel_id[1])) {
panel = &rg353_panel_details[i];
break;
}
}
if (!panel) {
printf("Unable to identify panel_id %x\n",
(panel_id[0] << 8) | panel_id[1]);
env_set("panel", "unknown");
return -EINVAL;
}
env_set("panel", panel->panel_compat);
return 0;
}
/* Detect which Anbernic RGXX3 device we are using so as to load the
* correct devicetree for Linux. Set an environment variable once
* found. The detection depends on the value of ADC channel 1, the
* presence of an eMMC on mmc0, and querying the DSI panel (TODO).
* presence of an eMMC on mmc0, and querying the DSI panel.
*/
int rgxx3_detect_device(void)
{
u32 adc_info;
int ret;
int ret, i;
int board_id = -ENXIO;
struct mmc *mmc;
@ -144,30 +325,37 @@ int rgxx3_detect_device(void)
return ret;
}
/* Observed value 517. */
if (adc_info > 505 && adc_info < 530)
board_id = RG353M;
/* Observed value 695. */
if (adc_info > 680 && adc_info < 710)
board_id = RG353V;
/* Documented value 860. */
if (adc_info > 850 && adc_info < 870)
board_id = RG353P;
/* Observed value 1023. */
if (adc_info > 1010)
board_id = RG503;
/*
* Get the correct device from the table. The ADC value is
* determined by a resistor on ADC channel 0. The hardware
* design calls for no more than a 1% variance on the
* resistor, so assume a +- value of 15 should be enough.
*/
for (i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) {
u32 adc_min = rg3xx_model_details[i].adc_value - 15;
u32 adc_max = rg3xx_model_details[i].adc_value + 15;
if (adc_min < adc_info && adc_max > adc_info) {
board_id = i;
break;
}
}
/*
* Try to access the eMMC on an RG353V. If it's missing, it's
* an RG353VS. Note we could also check for a touchscreen at
* 0x1a on i2c2.
* Try to access the eMMC on an RG353V or RG353P. If it's
* missing, it's an RG353VS or RG353PS. Note we could also
* check for a touchscreen at 0x1a on i2c2.
*/
if (board_id == RG353V) {
if (board_id == RG353V || board_id == RG353P) {
mmc = find_mmc_device(0);
if (mmc) {
ret = mmc_init(mmc);
if (ret)
board_id = RG353VS;
if (ret) {
if (board_id == RG353V)
board_id = RG353VS;
else
board_id = RG353PS;
}
}
}
@ -179,6 +367,14 @@ int rgxx3_detect_device(void)
rg3xx_model_details[board_id].board_name);
env_set("fdtfile", rg3xx_model_details[board_id].fdtfile);
/* Detect the panel type for any device that isn't a 503. */
if (board_id == RG503)
return 0;
ret = rgxx3_detect_display();
if (ret)
return ret;
return 0;
}
@ -186,18 +382,64 @@ int rk_board_late_init(void)
{
int ret;
/* Turn off orange LED and turn on green LED. */
writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A5,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
ret = rgxx3_detect_device();
if (ret) {
printf("Unable to detect device type: %d\n", ret);
return ret;
}
/* Turn off red LED and turn on orange LED. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C6,
(GPIO0_BASE + GPIO_SWPORT_DR_H));
if (IS_ENABLED(CONFIG_DM_PWM))
startup_buzz();
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
int node, ret;
char *env;
/* No fixups necessary for the RG503 */
env = env_get("board_name");
if (env && (!strcmp(env, rg3xx_model_details[RG503].board_name)))
return 0;
/* Change the model name of the RG353M */
if (env && (!strcmp(env, rg3xx_model_details[RG353M].board_name)))
fdt_setprop(blob, 0, "model",
rg3xx_model_details[RG353M].board_name,
sizeof(rg3xx_model_details[RG353M].board_name));
/*
* Check if the environment variable doesn't equal the panel.
* If it doesn't, update the devicetree to the correct panel.
*/
node = fdt_path_offset(blob, "/dsi@fe060000/panel@0");
if (!(node > 0)) {
printf("Can't find the DSI node\n");
return -ENODEV;
}
env = env_get("panel");
if (!env) {
printf("Can't get panel env\n");
return -ENODEV;
}
ret = fdt_node_check_compatible(blob, node, env);
if (ret < 0)
return -ENODEV;
/* Panels match, return 0. */
if (!ret)
return 0;
do_fixup_by_path_string(blob, "/dsi@fe060000/panel@0",
"compatible", env);
return 0;
}

1
board/edgeble/neural-compute-module-6/MAINTAINERS
View file

@ -4,3 +4,4 @@ S: Maintained
F: board/edgeble/neural-compute-module-6
F: include/configs/neural-compute-module-6.h
F: configs/neu6a-io-rk3588_defconfig
F: configs/neu6b-io-rk3588_defconfig

103
board/hardkernel/odroid_go2/go2.c
View file

@ -2,3 +2,106 @@
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <linux/stddef.h>
#include <adc.h>
#include <asm/io.h>
#include <dm.h>
#include <env.h>
#include <stdlib.h>
#define DTB_DIR "rockchip/"
struct oga_model {
const u16 adc_value;
const char *board;
const char *board_name;
const char *fdtfile;
};
enum oga_device_id {
OGA,
OGA_V11,
OGS,
};
/*
* All ADC values from schematic of Odroid Go Advance Black Edition.
* Value for OGS is inferred based on schematic and observed values.
*/
static const struct oga_model oga_model_details[] = {
[OGA] = {
856,
"rk3326-odroid-go2",
"ODROID-GO Advance",
DTB_DIR "rk3326-odroid-go2.dtb",
},
[OGA_V11] = {
677,
"rk3326-odroid-go2-v11",
"ODROID-GO Advance Black Edition",
DTB_DIR "rk3326-odroid-go2-v11.dtb",
},
[OGS] = {
85,
"rk3326-odroid-go3",
"ODROID-GO Super",
DTB_DIR "rk3326-odroid-go3.dtb",
},
};
/* Detect which Odroid Go Advance device we are using so as to load the
* correct devicetree for Linux. Set an environment variable once
* found. The detection depends on the value of ADC channel 0.
*/
int oga_detect_device(void)
{
u32 adc_info;
int ret, i;
int board_id = -ENXIO;
ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info);
if (ret) {
printf("Read SARADC failed with error %d\n", ret);
return ret;
}
/*
* Get the correct device from the table. The ADC value is
* determined by a resistor on ADC channel 0. The manufacturer
* accounted for this with a 5% tolerance, so assume a +- value
* of 50 should be enough.
*/
for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) {
u32 adc_min = oga_model_details[i].adc_value - 50;
u32 adc_max = oga_model_details[i].adc_value + 50;
if (adc_min < adc_info && adc_max > adc_info) {
board_id = i;
break;
}
}
if (board_id < 0)
return board_id;
env_set("board", oga_model_details[board_id].board);
env_set("board_name",
oga_model_details[board_id].board_name);
env_set("fdtfile", oga_model_details[board_id].fdtfile);
return 0;
}
int rk_board_late_init(void)
{
int ret;
ret = oga_detect_device();
if (ret) {
printf("Unable to detect device type: %d\n", ret);
return ret;
}
return 0;
}

15
board/hardkernel/odroid_m1/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_ODROID_M1_RK3568
config SYS_BOARD
default "odroid_m1"
config SYS_VENDOR
default "hardkernel"
config SYS_CONFIG_NAME
default "odroid_m1"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

8
board/hardkernel/odroid_m1/MAINTAINERS Normal file
View file

@ -0,0 +1,8 @@
ODROID-M1
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/hardkernel/odroid_m1/
F: include/configs/odroid_m1.h
F: configs/odroid-m1-rk3568_defconfig
F: arch/arm/dts/rk3568-odroid-m1.dts
F: arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi

3
board/hardkernel/odroid_m1/Makefile Normal file
View file

@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += odroid_m1.o

1
board/hardkernel/odroid_m1/odroid_m1.c Normal file
View file

@ -0,0 +1 @@
// SPDX-License-Identifier: GPL-2.0+

72
board/rockchip/evb_rk3229/README
View file

@ -13,25 +13,23 @@ Compile the OP-TEE
> cd optee_os
> make clean
> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
Get tee.bin in this step, copy it to U-Boot root dir:
> cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
> make CROSS_COMPILE=arm-none-eabi- PLATFORM=rockchip-rk322x
Get tee-raw.bin in this step, copy it to U-Boot root dir:
> cp out/arm-plat-rockchip/core/tee-raw.bin ../u-boot/tee.bin
Compile the U-Boot
==================
> cd ../u-boot
> export CROSS_COMPILE=arm-linux-gnueabihf-
> make evb-rk3229_defconfig
> make
> make u-boot.itb
> TEE=tee.bin CROSS_COMPILE=arm-linux-gnueabihf- make
Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
Get u-boot-rockchip.bin in this step.
Compile the rkdeveloptool
=======================
Follow instructions in latest README
> cd ../rkflashtool
> cd ../rkdeveloptool
> autoreconf -i
> ./configure
> make
@ -42,30 +40,56 @@ Compile the rkdeveloptool
Both origin binaries and Tool are ready now, choose either option 1 or
option 2 to deploy U-Boot.
Package the image
=================
> cd ../u-boot
> tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
> cat spl/u-boot-spl.bin >> idbloader.img
Get idbloader.img in this step.
Flash the image to eMMC
=======================
Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
> cd ..
> rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
> rkdeveloptool wl 64 u-boot/idbloader.img
> rkdeveloptool wl 0x4000 u-boot/u-boot.itb
> rkdeveloptool rd
> rkdeveloptool/rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
> rkdeveloptool/rkdeveloptool wl 64 u-boot/u-boot-rockchip.bin
> rkdeveloptool/rkdeveloptool rd
Flash the image to SD card
==========================
> dd if=u-boot/idbloader.img of=/dev/sdb seek=64
> dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
> dd if=u-boot/u-boot-rockchip.bin of=/dev/sdb seek=64
You should be able to get U-Boot log message with OP-TEE boot info:
U-Boot TPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51)
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200)
Trying to boot from MMC1
I/TC:
I/TC: Non-secure external DT found
I/TC: Switching console to device: /serial@11030000
I/TC: OP-TEE version: 3.22.0-27-g893a762d1 (gcc version 10.3.1 20210621 (release) (15:10.3-2021.07-4)) #1 Sat Jul 15 12:14:36 UTC 2023 arm
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
M/TC: Not protecting region 1: 0x68400000-0x68600000
I/TC: Primary CPU switching to normal world boot
U-Boot 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200)
Model: Rockchip RK3229 Evaluation board
DRAM: 1 GiB (effective 992 MiB)
Core: 113 devices, 16 uclasses, devicetree: separate
MMC: mmc@30000000: 1, mmc@30020000: 0
Loading Environment from MMC... Card did not respond to voltage select! : -110
*** Warning - No block device, using default environment
In: serial@11030000
Out: serial@11030000
Err: serial@11030000
Model: Rockchip RK3229 Evaluation board
Net:
Warning: ethernet@30200000 (eth0) using random MAC address - 72:65:2b:f1:c5:0a
eth0: ethernet@30200000
Hit any key to stop autoboot: 0
=>
You should be able to get U-Boot log message with OP-TEE boot info.
For more detail, please reference to:
http://opensource.rock-chips.com/wiki_Boot_option

12
board/rockchip/evb_rk3328/MAINTAINERS
View file

@ -18,6 +18,18 @@ F: configs/nanopi-r2s-rk3328_defconfig
F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
F: arch/arm/dts/rk3328-nanopi-r2s.dts
ORANGEPI-R1-PLUS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/orangepi-r1-plus-rk3328_defconfig
F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
ORANGEPI-R1-PLUS-LTS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/orangepi-r1-plus-lts-rk3328_defconfig
F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
ROC-RK3328-CC
M: Loic Devulder <ldevulder@suse.com>
M: Chen-Yu Tsai <wens@csie.org>

6
board/rockchip/evb_rk3399/MAINTAINERS
View file

@ -86,6 +86,12 @@ S: Maintained
F: configs/rock-4c-plus-rk3399_defconfig
F: arch/arm/dts/rk3399-rock-4c-plus.dts
ROCK-4SE
M: Christopher Obbard <chris.obbard@collabora.com>
S: Maintained
F: configs/rock-4se-rk3399_defconfig
F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
ROCK-PI-4
M: Akash Gajjar <akash@openedev.com>
M: Jagan Teki <jagan@amarulasolutions.com>

15
board/rockchip/evb_rk3568/MAINTAINERS
View file

@ -7,6 +7,21 @@ F: configs/evb-rk3568_defconfig
F: arch/arm/dts/rk3568-evb-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
NANOPI-R5C
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/nanopi-r5c-rk3568_defconfig
F: arch/arm/dts/rk3568-nanopi-r5c.dts
F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
NANOPI-R5S
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/nanopi-r5s-rk3568_defconfig
F: arch/arm/dts/rk3568-nanopi-r5s.dts
F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
RADXA-CM3
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

2
cmd/ini.c
View file

@ -89,7 +89,7 @@ static char *memgets(char *str, int num, char **mem, size_t *memsize)
end = *mem + *memsize;
newline = 0;
}
len = min((end - *mem) + newline, num);
len = min((int)(end - *mem) + newline, num);
memcpy(str, *mem, len);
if (len < num)
str[len] = '\0';

15
configs/anbernic-rgxx3_defconfig
View file

@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
@ -24,9 +25,13 @@ CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@ -41,6 +46,7 @@ CONFIG_CMD_PWM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_CLS is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
@ -60,6 +66,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
@ -69,10 +76,18 @@ CONFIG_REGULATOR_RK8XX=y
CONFIG_DM_REGULATOR_SCMI=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
# CONFIG_RNG_SMCCC_TRNG is not set
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_VIDEO=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_REGEX=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

1
configs/chromebit_mickey_defconfig
View file

@ -81,6 +81,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y

1
configs/chromebook_bob_defconfig
View file

@ -43,6 +43,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

1
configs/chromebook_jerry_defconfig
View file

@ -84,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y

1
configs/chromebook_kevin_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y

1
configs/chromebook_minnie_defconfig
View file

@ -83,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y

1
configs/chromebook_speedy_defconfig
View file

@ -82,6 +82,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y

1
configs/eaidk-610-rk3399_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

2
configs/evb-rk3229_defconfig
View file

@ -31,7 +31,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
CONFIG_SPL_OPTEE_IMAGE=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_GPT=y

1
configs/evb-rk3399_defconfig
View file

@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/ficus-rk3399_defconfig
View file

@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x10000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y

1
configs/firefly-rk3399_defconfig
View file

@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/khadas-edge-captain-rk3399_defconfig
View file

@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_BOOTZ=y

1
configs/khadas-edge-rk3399_defconfig
View file

@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_BOOTZ=y

1
configs/khadas-edge-v-rk3399_defconfig
View file

@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PBSIZE=1048
CONFIG_CMD_BOOTZ=y

1
configs/leez-rk3399_defconfig
View file

@ -25,6 +25,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/nanopc-t4-rk3399_defconfig
View file

@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/nanopi-m4-2gb-rk3399_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/nanopi-m4-rk3399_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/nanopi-m4b-rk3399_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/nanopi-neo4-rk3399_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/nanopi-r4s-rk3399_defconfig
View file

@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

85
configs/nanopi-r5c-rk3568_defconfig Normal file
View file

@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

85
configs/nanopi-r5s-rk3568_defconfig Normal file
View file

@ -0,0 +1,85 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_WARN=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ERRNO_STR=y

64
configs/neu6b-io-rk3588_defconfig Normal file
View file

@ -0,0 +1,64 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_RK3588_NEU6=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_ERRNO_STR=y

1
configs/odroid-go2_defconfig
View file

@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000

111
configs/odroid-m1-rk3568_defconfig Normal file
View file

@ -0,0 +1,111 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_ODROID_M1_RK3568=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_INI=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_CRAMFS=y
CONFIG_MTDPARTS_DEFAULT="nor0:0x100000(reserved),0x200000(uboot),0x100000(splash),0xc00000(Firmware)"
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_AHCI_PCI=y
CONFIG_DWC_AHCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=4
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_FS_CRAMFS=y
CONFIG_ERRNO_STR=y

114
configs/orangepi-r1-plus-lts-rk3328_defconfig Normal file
View file

@ -0,0 +1,114 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

114
configs/orangepi-r1-plus-rk3328_defconfig Normal file
View file

@ -0,0 +1,114 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_SPL_STACK=0x400000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

1
configs/orangepi-rk3399_defconfig
View file

@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/pinebook-pro-rk3399_defconfig
View file

@ -36,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y

1
configs/pinephone-pro-rk3399_defconfig
View file

@ -35,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y

1
configs/roc-pc-mezzanine-rk3399_defconfig
View file

@ -37,6 +37,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

1
configs/roc-pc-rk3399_defconfig
View file

@ -38,6 +38,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

9
configs/rock-3a-rk3568_defconfig
View file

@ -22,7 +22,9 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
@ -46,6 +48,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PMIC=y
@ -56,6 +59,8 @@ CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
@ -70,6 +75,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
@ -78,6 +85,8 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y

1
configs/rock-4c-plus-rk3399_defconfig
View file

@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y

100
configs/rock-4se-rk3399_defconfig Normal file
View file

@ -0,0 +1,100 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x400000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_ROCKCHIP_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y

1
configs/rock-pi-4-rk3399_defconfig
View file

@ -33,6 +33,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y

1
configs/rock-pi-4c-rk3399_defconfig
View file

@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y

1
configs/rock-pi-n10-rk3399pro_defconfig
View file

@ -32,6 +32,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

17
configs/rock5b-rk3588_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
@ -34,6 +35,7 @@ CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@ -47,9 +49,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
@ -59,6 +63,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@ -71,10 +76,12 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RTL8169=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
@ -85,10 +92,16 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
@ -97,4 +110,8 @@ CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
configs/rock960-rk3399_defconfig
View file

@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PBSIZE=1052
CONFIG_CMD_BOOTZ=y

1
configs/rockpro64-rk3399_defconfig
View file

@ -41,6 +41,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y

29
doc/board/anbernic/rgxx3.rst
View file

@ -7,27 +7,36 @@ This allows U-Boot to boot the following Anbernic devices:
- Anbernic RG353M
- Anbernic RG353P
- Anbernic RG353PS
- Anbernic RG353V
- Anbernic RG353VS
- Anbernic RG503
The correct device is detected automatically by comparing ADC values
from ADC channel 1. In the event of an RG353V, an attempt is then made
to probe for an eMMC and if it fails the device is assumed to be an
RG353VS. Based on the detected device, the environment variables
"board", "board_name", and "fdtfile" are set to the correct values
corresponding to the board which can be read by a boot script to boot
with the correct device tree.
from ADC channel 1. In the event of an RG353V or RG353P, an attempt
is then made to probe for an eMMC and if it fails the device is assumed
to be an RG353VS or RG353PS. Based on the detected device, the
environment variables "board", "board_name", and "fdtfile" are set to
the correct values corresponding to the board which can be read by a
boot script to boot with the correct device tree. If the board detected
is not of type RG503 (which currently has only 1 panel revision) a
panel detect is then performed by probing a "dummy" display on the DSI
bus and then querying the display ID. The display ID is then compared
to a table to get the known compatible string for use in Linux, and
this string is saved as an environment variable of "panel".
Please note that there are some versions of the RG353 devices with
different panels. Panel auto-detection is planned for a later date.
FDT fixups are performed in the event of an RG353M to change the device
name, or in the event the panel detected does not match the devicetree.
This allows Linux to load the correct panel driver without having to
know exactly which panel is used (as there is no user distingushable
way to tell).
Building U-Boot
---------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-none-elf-
$ export CROSS_COMPILE=aarch64-linux-gnu-
$ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf
$ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin
$ make anbernic-rgxx3_defconfig
@ -40,7 +49,7 @@ Image installation
------------------
Write the ``u-boot-rockchip.bin`` to an SD card offset 32kb from the
start.
start. Please note that eMMC booting has not been tested at this time.
.. code-block:: bash

6
doc/board/rockchip/rockchip.rst
View file

@ -84,7 +84,7 @@ List of mainline supported Rockchip boards:
- Orange Pi RK3399 (orangepi-rk3399)
- Pine64 RockPro64 (rockpro64-rk3399)
- Radxa ROCK 4C+ (rock-4c-plus-rk3399)
- Radxa ROCK 4SE (rock-pi-4-rk3399)
- Radxa ROCK 4SE (rock-4se-rk3399)
- Radxa ROCK Pi 4A/B/A+/B+ (rock-pi-4-rk3399)
- Radxa ROCK Pi 4C (rock-pi-4c-rk3399)
- Rockchip Evb-RK3399 (evb_rk3399)
@ -95,10 +95,12 @@ List of mainline supported Rockchip boards:
* rk3568
- Rockchip Evb-RK3568 (evb-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
* rk3588
- Rockchip EVB (evb-rk3588)
- Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- Radxa ROCK 5B (rock5b-rk3588)
* rv1108

4
drivers/ata/dwc_ahci.c
View file

@ -13,7 +13,9 @@
#include <ahci.h>
#include <scsi.h>
#include <sata.h>
#ifdef CONFIG_ARCH_OMAP2PLUS
#include <asm/arch/sata.h>
#endif
#include <asm/io.h>
#include <generic-phy.h>
@ -72,12 +74,14 @@ static int dwc_ahci_probe(struct udevice *dev)
return ret;
}
#ifdef CONFIG_ARCH_OMAP2PLUS
if (priv->wrapper_base) {
u32 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
/* Enable SATA module, No Idle, No Standby */
writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG);
}
#endif
return ahci_probe_scsi(dev, (ulong)priv->base);
}

1
drivers/clk/rockchip/clk_rk3568.c
View file

@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)
break;
case CLK_PCIEPHY0_REF:
case CLK_PCIEPHY1_REF:
case CLK_PCIEPHY2_REF:
return 0;
default:
return -ENOENT;

11
drivers/core/read.c
View file

@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index,
return devfdt_get_addr_size_index(dev, index, size);
}
void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index,
fdt_size_t *size)
{
fdt_addr_t addr = dev_read_addr_size_index(dev, index, size);
if (addr == FDT_ADDR_T_NONE)
return NULL;
return map_sysmem(addr, 0);
}
void *dev_remap_addr_index(const struct udevice *dev, int index)
{
fdt_addr_t addr = dev_read_addr_index(dev, index);

34
drivers/mtd/nand/raw/rockchip_nfc.c
View file

@ -525,7 +525,7 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
int pages_per_blk = mtd->erasesize / mtd->writesize;
int ret = 0, i, boot_rom_mode = 0;
dma_addr_t dma_data, dma_oob;
u32 reg;
u32 tmp;
u8 *oob;
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
@ -552,6 +552,13 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
*
* 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
*
* The code here just swaps the first 4 bytes with the last
* 4 bytes without losing any data.
*
* The chip->oob_poi data layout:
*
* BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3
*
* Configure the ECC algorithm supported by the boot ROM.
*/
if (page < (pages_per_blk * rknand->boot_blks)) {
@ -561,21 +568,17 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
}
for (i = 0; i < ecc->steps; i++) {
if (!i) {
reg = 0xFFFFFFFF;
} else {
if (!i)
oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;
else
oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
reg = oob[0] | oob[1] << 8 | oob[2] << 16 |
oob[3] << 24;
}
if (!i && boot_rom_mode)
reg = (page & (pages_per_blk - 1)) * 4;
tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24;
if (nfc->cfg->type == NFC_V9)
nfc->oob_buf[i] = reg;
nfc->oob_buf[i] = tmp;
else
nfc->oob_buf[i * (oob_step / 4)] = reg;
nfc->oob_buf[i * (oob_step / 4)] = tmp;
}
dma_data = dma_map_single((void *)nfc->page_buf,
@ -720,12 +723,17 @@ static int rk_nfc_read_page_hwecc(struct mtd_info *mtd,
goto timeout_err;
}
for (i = 1; i < ecc->steps; i++) {
oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
for (i = 0; i < ecc->steps; i++) {
if (!i)
oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE;
else
oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
if (nfc->cfg->type == NFC_V9)
tmp = nfc->oob_buf[i];
else
tmp = nfc->oob_buf[i * (oob_step / 4)];
*oob++ = (u8)tmp;
*oob++ = (u8)(tmp >> 8);
*oob++ = (u8)(tmp >> 16);

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