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https://github.com/AsahiLinux/u-boot
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net: mediatek: add support for MediaTek MT7988 SoC
This patch adds support for MediaTek MT7988. MT7988 features MediaTek NETSYS v3, including three GMACs, and two of them supports 10Gbps USXGMII. MT7988 embeds a MT7531 switch (not MCM) which supports accessing internal registers through MMIO instead of MDIO. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
parent
7628194d7a
commit
93eb707c28
2 changed files with 177 additions and 1 deletions
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@ -54,6 +54,16 @@
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(DP_PDMA << MC_DP_S) | \
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(DP_PDMA << UN_DP_S))
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#define GDMA_BRIDGE_TO_CPU \
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(0xC0000000 | \
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GDM_ICS_EN | \
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GDM_TCS_EN | \
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GDM_UCS_EN | \
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(DP_PDMA << MYMAC_DP_S) | \
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(DP_PDMA << BC_DP_S) | \
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(DP_PDMA << MC_DP_S) | \
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(DP_PDMA << UN_DP_S))
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#define GDMA_FWD_DISCARD \
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(0x20000000 | \
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GDM_ICS_EN | \
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@ -68,7 +78,8 @@
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enum mtk_switch {
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SW_NONE,
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SW_MT7530,
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SW_MT7531
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SW_MT7531,
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SW_MT7988,
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};
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/* struct mtk_soc_data - This is the structure holding all differences
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@ -102,6 +113,7 @@ struct mtk_eth_priv {
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void __iomem *fe_base;
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void __iomem *gmac_base;
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void __iomem *sgmii_base;
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void __iomem *gsw_base;
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struct regmap *ethsys_regmap;
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@ -171,6 +183,11 @@ static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
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writel(val, priv->fe_base + gdma_base + reg);
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}
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static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
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{
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clrsetbits_le32(priv->fe_base + reg, clr, set);
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}
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static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
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{
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return readl(priv->gmac_base + reg);
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@ -208,6 +225,16 @@ static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
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regmap_write(priv->infra_regmap, reg, val);
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}
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static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
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{
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return readl(priv->gsw_base + reg);
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}
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static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
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{
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writel(val, priv->gsw_base + reg);
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}
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/* Direct MDIO clause 22/45 access via SoC */
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static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
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u32 cmd, u32 st)
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@ -342,6 +369,11 @@ static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
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{
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int ret, low_word, high_word;
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if (priv->sw == SW_MT7988) {
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*data = mtk_gsw_read(priv, reg);
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return 0;
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}
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/* Write page address */
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ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
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if (ret)
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@ -367,6 +399,11 @@ static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
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{
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int ret;
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if (priv->sw == SW_MT7988) {
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mtk_gsw_write(priv, reg, data);
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return 0;
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}
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/* Write page address */
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ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
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if (ret)
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@ -537,6 +574,7 @@ static int mtk_mdio_register(struct udevice *dev)
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priv->mmd_write = mtk_mmd_ind_write;
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break;
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case SW_MT7531:
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case SW_MT7988:
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priv->mii_read = mt7531_mii_ind_read;
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priv->mii_write = mt7531_mii_ind_write;
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priv->mmd_read = mt7531_mmd_ind_read;
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@ -957,6 +995,103 @@ static int mt7531_setup(struct mtk_eth_priv *priv)
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return 0;
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}
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static void mt7988_phy_setting(struct mtk_eth_priv *priv)
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{
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u16 val;
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u32 i;
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for (i = 0; i < MT753X_NUM_PHYS; i++) {
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/* Enable HW auto downshift */
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priv->mii_write(priv, i, 0x1f, 0x1);
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val = priv->mii_read(priv, i, PHY_EXT_REG_14);
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val |= PHY_EN_DOWN_SHFIT;
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priv->mii_write(priv, i, PHY_EXT_REG_14, val);
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/* PHY link down power saving enable */
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val = priv->mii_read(priv, i, PHY_EXT_REG_17);
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val |= PHY_LINKDOWN_POWER_SAVING_EN;
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priv->mii_write(priv, i, PHY_EXT_REG_17, val);
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}
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}
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static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
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{
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u32 pmcr = FORCE_MODE_LNK;
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if (enable)
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pmcr = priv->mt753x_pmcr;
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mt753x_reg_write(priv, PMCR_REG(6), pmcr);
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}
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static int mt7988_setup(struct mtk_eth_priv *priv)
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{
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u16 phy_addr, phy_val;
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u32 pmcr;
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int i;
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priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
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priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
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MT753X_SMI_ADDR_MASK;
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/* Turn off PHYs */
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for (i = 0; i < MT753X_NUM_PHYS; i++) {
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phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
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phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
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phy_val |= BMCR_PDOWN;
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priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
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}
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switch (priv->phy_interface) {
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case PHY_INTERFACE_MODE_USXGMII:
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/* Use CPU bridge instead of actual USXGMII path */
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/* Set GDM1 no drop */
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mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
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/* Enable GDM1 to GSW CPU bridge */
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mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
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/* XGMAC force link up */
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mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
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/* Setup GSW CPU bridge IPG */
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mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
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(0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
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break;
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default:
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printf("Error: MT7988 GSW does not support %s interface\n",
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phy_string_for_interface(priv->phy_interface));
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break;
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}
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pmcr = MT7988_FORCE_MODE |
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(IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
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MAC_MODE | MAC_TX_EN | MAC_RX_EN |
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BKOFF_EN | BACKPR_EN |
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FORCE_RX_FC | FORCE_TX_FC |
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(SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
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FORCE_LINK;
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priv->mt753x_pmcr = pmcr;
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/* Keep MAC link down before starting eth */
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mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
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/* Turn on PHYs */
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for (i = 0; i < MT753X_NUM_PHYS; i++) {
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phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
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phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
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phy_val &= ~BMCR_PDOWN;
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priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
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}
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mt7988_phy_setting(priv);
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return 0;
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}
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static int mt753x_switch_init(struct mtk_eth_priv *priv)
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{
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int ret;
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@ -1497,6 +1632,11 @@ static int mtk_eth_start(struct udevice *dev)
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}
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if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
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if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
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mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
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GDMA_BRIDGE_TO_CPU);
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}
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mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
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GDMA_CPU_BRIDGE_EN);
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}
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@ -1845,6 +1985,12 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
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priv->switch_mac_control = mt7531_mac_control;
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priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
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priv->mt753x_reset_wait_time = 200;
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} else if (!strcmp(str, "mt7988")) {
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priv->sw = SW_MT7988;
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priv->switch_init = mt7988_setup;
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priv->switch_mac_control = mt7988_mac_control;
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priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
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priv->mt753x_reset_wait_time = 50;
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} else {
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printf("error: unsupported switch\n");
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return -EINVAL;
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@ -1879,6 +2025,15 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
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return 0;
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}
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static const struct mtk_soc_data mt7988_data = {
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.caps = MT7988_CAPS,
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.ana_rgc3 = 0x128,
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.gdma_count = 3,
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.pdma_base = PDMA_V3_BASE,
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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.rxd_size = sizeof(struct mtk_rx_dma_v2),
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};
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static const struct mtk_soc_data mt7986_data = {
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.caps = MT7986_CAPS,
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.ana_rgc3 = 0x128,
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@ -1930,6 +2085,7 @@ static const struct mtk_soc_data mt7621_data = {
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};
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static const struct udevice_id mtk_eth_ids[] = {
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{ .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
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{ .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
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{ .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
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{ .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
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@ -51,6 +51,8 @@ enum mkt_eth_capabilities {
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#define MT7986_CAPS (MTK_NETSYS_V2)
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#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA)
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/* Frame Engine Register Bases */
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#define PDMA_V1_BASE 0x0800
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#define PDMA_V2_BASE 0x6000
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@ -59,6 +61,7 @@ enum mkt_eth_capabilities {
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#define GDMA2_BASE 0x1500
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#define GDMA3_BASE 0x0540
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#define GMAC_BASE 0x10000
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#define GSW_BASE 0x20000
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/* Ethernet subsystem registers */
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@ -117,6 +120,9 @@ enum mkt_eth_capabilities {
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#define RG_XFI_PLL_ANA_SWWA 0x02283248
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/* Frame Engine Registers */
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#define PSE_NO_DROP_CFG_REG 0x108
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#define PSE_NO_DROP_GDM1 BIT(1)
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#define FE_GLO_MISC_REG 0x124
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#define PDMA_VER_V2 BIT(4)
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@ -187,6 +193,17 @@ enum mkt_eth_capabilities {
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#define MDIO_RW_DATA_S 0
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#define MDIO_RW_DATA_M 0xffff
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#define GMAC_XGMAC_STS_REG 0x000c
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#define P1_XGMAC_FORCE_LINK BIT(15)
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#define GMAC_MAC_MISC_REG 0x0010
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#define GMAC_GSW_CFG_REG 0x0080
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#define GSWTX_IPG_M 0xF0000
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#define GSWTX_IPG_S 16
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#define GSWRX_IPG_M 0xF
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#define GSWRX_IPG_S 0
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/* MDIO_CMD: MDIO commands */
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#define MDIO_CMD_ADDR 0
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#define MDIO_CMD_WRITE 1
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@ -285,6 +302,9 @@ enum mkt_eth_capabilities {
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FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
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FORCE_MODE_DPX | FORCE_MODE_SPD | \
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FORCE_MODE_LNK
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#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
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FORCE_MODE_DPX | FORCE_MODE_SPD | \
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FORCE_MODE_LNK
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/* MT7531 SGMII Registers */
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#define MT7531_SGMII_REG_BASE 0x5000
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