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phy: ti: phy-j721e-wiz: Add j721s2-wiz-10g module support
Add support for j721s2-wiz-10g device to use clock-names interface instead of explicitly defining clock nodes within device tree node. Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
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1 changed files with 20 additions and 1 deletions
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@ -256,6 +256,7 @@ enum wiz_type {
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J721E_WIZ_10G,
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AM64_WIZ_10G,
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J784S4_WIZ_10G,
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J721S2_WIZ_10G,
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};
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struct wiz_data {
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@ -307,6 +308,15 @@ static struct wiz_data j784s4_wiz_10g = {
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.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
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};
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static struct wiz_data j721s2_10g_data = {
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.type = J721S2_WIZ_10G,
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.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
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.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
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.refclk_dig_sel = &refclk_dig_sel_10g,
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.clk_mux_sel = clk_mux_sel_10g,
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.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
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};
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#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
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#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
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@ -1037,8 +1047,14 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
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ofnode node;
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int i, rc;
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if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
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switch (type) {
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case AM64_WIZ_10G:
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case J784S4_WIZ_10G:
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case J721S2_WIZ_10G:
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return j721e_wiz_bind_clocks(wiz);
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default:
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break;
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};
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div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
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if (!div_clk_drv) {
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@ -1282,6 +1298,9 @@ static const struct udevice_id j721e_wiz_ids[] = {
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{
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.compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
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},
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{
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.compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data,
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},
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{}
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};
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