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drivers/mtd/nvmxip: introduce NVM XIP block storage emulation
add block storage emulation for NVM XIP flash devices Some paltforms such as Corstone-1000 need to see NVM XIP raw flash as a block storage device with read only capability. Here NVM flash devices are devices with addressable memory (e.g: QSPI NOR flash). The implementation is generic and can be used by different platforms. Two drivers are provided as follows. nvmxip-blk : a generic block driver allowing to read from the XIP flash nvmxip Uclass driver : When a device is described in the DT and associated with UCLASS_NVMXIP, the Uclass creates a block device and binds it with the nvmxip-blk. Platforms can use multiple NVM XIP devices at the same time by defining a DT node for each one of them. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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@ -1204,6 +1204,12 @@ F: cmd/nvme.c
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F: include/nvme.h
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F: doc/develop/driver-model/nvme.rst
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NVMXIP
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M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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S: Maintained
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F: doc/develop/driver-model/nvmxip.rst
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F: drivers/mtd/nvmxip/
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NVMEM
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M: Sean Anderson <seanga2@gmail.com>
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S: Maintained
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@ -20,6 +20,7 @@ subsystems
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livetree
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migration
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nvme
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nvmxip
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of-plat
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pci-info
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pmic-framework
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48
doc/develop/driver-model/nvmxip.rst
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48
doc/develop/driver-model/nvmxip.rst
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@ -0,0 +1,48 @@
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.. SPDX-License-Identifier: GPL-2.0+
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NVM XIP Block Storage Emulation Driver
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=======================================
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Summary
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-------
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Non-Volatile Memory devices with addressable memory (e.g: QSPI NOR flash) could
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be used for block storage needs (e.g: parsing a GPT layout in a raw QSPI NOR flash).
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The NVMXIP Uclass provides this functionality and can be used for any 64-bit platform.
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The NVMXIP Uclass provides the following drivers:
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nvmxip-blk block driver:
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A generic block driver allowing to read from the XIP flash.
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The driver belongs to UCLASS_BLK.
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The driver implemented by drivers/mtd/nvmxip/nvmxip.c
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nvmxip Uclass driver:
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When a device is described in the DT and associated with UCLASS_NVMXIP,
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the Uclass creates a block device and binds it with the nvmxip-blk.
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The Uclass driver implemented by drivers/mtd/nvmxip/nvmxip-uclass.c
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The implementation is generic and can be used by different platforms.
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Supported hardware
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--------------------------------
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Any 64-bit plaform.
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Configuration
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----------------------
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config NVMXIP
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This option allows the emulation of a block storage device
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on top of a direct access non volatile memory XIP flash devices.
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This support provides the read operation.
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This option provides the block storage driver nvmxip-blk which
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handles the read operation. This driver is HW agnostic and can support
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multiple flash devices at the same time.
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Contributors
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------------
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* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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@ -28,6 +28,7 @@ static struct {
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{ UCLASS_AHCI, "sata" },
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{ UCLASS_HOST, "host" },
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{ UCLASS_NVME, "nvme" },
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{ UCLASS_NVMXIP, "nvmxip" },
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{ UCLASS_EFI_MEDIA, "efi" },
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{ UCLASS_EFI_LOADER, "efiloader" },
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{ UCLASS_VIRTIO, "virtio" },
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@ -270,4 +270,6 @@ source "drivers/mtd/spi/Kconfig"
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source "drivers/mtd/ubi/Kconfig"
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source "drivers/mtd/nvmxip/Kconfig"
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endmenu
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@ -25,6 +25,7 @@ obj-y += nand/
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obj-y += onenand/
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obj-y += spi/
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obj-$(CONFIG_MTD_UBI) += ubi/
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obj-$(CONFIG_NVMXIP) += nvmxip/
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#SPL/TPL build
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else
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13
drivers/mtd/nvmxip/Kconfig
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13
drivers/mtd/nvmxip/Kconfig
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# Authors:
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# Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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config NVMXIP
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bool "NVM XIP devices support"
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select BLK
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help
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This option allows the emulation of a block storage device
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on top of a direct access non volatile memory XIP flash devices.
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This support provides the read operation.
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7
drivers/mtd/nvmxip/Makefile
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7
drivers/mtd/nvmxip/Makefile
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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# Authors:
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# Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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obj-y += nvmxip-uclass.o nvmxip.o
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67
drivers/mtd/nvmxip/nvmxip-uclass.c
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67
drivers/mtd/nvmxip/nvmxip-uclass.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* Authors:
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* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <linux/bitops.h>
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#include "nvmxip.h"
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/* LBA Macros */
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#define DEFAULT_LBA_SHIFT 10 /* 1024 bytes per block */
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#define DEFAULT_LBA_COUNT 1024 /* block count */
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#define DEFAULT_LBA_SZ BIT(DEFAULT_LBA_SHIFT)
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/**
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* nvmxip_post_bind() - post binding treatments
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* @dev: the NVMXIP device
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*
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* Create and probe a child block device.
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*
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* Return:
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*
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* 0 on success. Otherwise, failure
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*/
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static int nvmxip_post_bind(struct udevice *udev)
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{
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int ret;
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struct udevice *bdev = NULL;
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char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1];
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int devnum;
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devnum = uclass_id_count(UCLASS_NVMXIP);
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snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", devnum);
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ret = blk_create_devicef(udev, NVMXIP_BLKDRV_NAME, bdev_name, UCLASS_NVMXIP,
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devnum, DEFAULT_LBA_SZ,
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DEFAULT_LBA_COUNT, &bdev);
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if (ret) {
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log_err("[%s]: failure during creation of the block device %s, error %d\n",
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udev->name, bdev_name, ret);
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return ret;
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}
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ret = blk_probe_or_unbind(bdev);
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if (ret) {
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log_err("[%s]: failure during probing the block device %s, error %d\n",
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udev->name, bdev_name, ret);
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return ret;
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}
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log_info("[%s]: the block device %s ready for use\n", udev->name, bdev_name);
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return 0;
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}
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UCLASS_DRIVER(nvmxip) = {
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.name = "nvmxip",
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.id = UCLASS_NVMXIP,
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.post_bind = nvmxip_post_bind,
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};
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119
drivers/mtd/nvmxip/nvmxip.c
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119
drivers/mtd/nvmxip/nvmxip.c
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* Authors:
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* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <mapmem.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include "nvmxip.h"
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/**
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* nvmxip_mmio_rawread() - read from the XIP flash
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* @address: address of the data
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* @value: pointer to where storing the value read
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*
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* Read raw data from the XIP flash.
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*
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* Return:
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*
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* Always return 0.
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*/
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static int nvmxip_mmio_rawread(const phys_addr_t address, u64 *value)
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{
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*value = readq(address);
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return 0;
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}
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/**
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* nvmxip_blk_read() - block device read operation
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* @dev: the block device
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* @blknr: first block number to read from
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* @blkcnt: number of blocks to read
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* @buffer: destination buffer
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*
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* Read data from the block storage device.
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*
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* Return:
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*
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* number of blocks read on success. Otherwise, failure
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*/
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static ulong nvmxip_blk_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
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{
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struct nvmxip_plat *plat = dev_get_plat(dev->parent);
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struct blk_desc *desc = dev_get_uclass_plat(dev);
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/* number of the u64 words to read */
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u32 qwords = (blkcnt * desc->blksz) / sizeof(u64);
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/* physical address of the first block to read */
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phys_addr_t blkaddr = plat->phys_base + blknr * desc->blksz;
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u64 *virt_blkaddr;
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u64 *pdst = buffer;
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uint qdata_idx;
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if (!pdst)
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return -EINVAL;
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log_debug("[%s]: reading from blknr: %lu , blkcnt: %lu\n", dev->name, blknr, blkcnt);
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virt_blkaddr = map_sysmem(blkaddr, 0);
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/* assumption: the data is virtually contiguous */
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for (qdata_idx = 0 ; qdata_idx < qwords ; qdata_idx++)
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nvmxip_mmio_rawread((phys_addr_t)(virt_blkaddr + qdata_idx), pdst++);
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log_debug("[%s]: src[0]: 0x%llx , dst[0]: 0x%llx , src[-1]: 0x%llx , dst[-1]: 0x%llx\n",
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dev->name,
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*virt_blkaddr,
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*(u64 *)buffer,
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*(u64 *)((u8 *)virt_blkaddr + desc->blksz * blkcnt - sizeof(u64)),
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*(u64 *)((u8 *)buffer + desc->blksz * blkcnt - sizeof(u64)));
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unmap_sysmem(virt_blkaddr);
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return blkcnt;
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}
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/**
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* nvmxip_blk_probe() - block storage device probe
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* @dev: the block storage device
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*
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* Initialize the block storage descriptor.
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*
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* Return:
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*
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* Always return 0.
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*/
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static int nvmxip_blk_probe(struct udevice *dev)
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{
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struct nvmxip_plat *plat = dev_get_plat(dev->parent);
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struct blk_desc *desc = dev_get_uclass_plat(dev);
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desc->lba = plat->lba;
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desc->log2blksz = plat->lba_shift;
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desc->blksz = BIT(plat->lba_shift);
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desc->bdev = dev;
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log_debug("[%s]: block storage layout\n lbas: %lu , log2blksz: %d, blksz: %lu\n",
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dev->name, desc->lba, desc->log2blksz, desc->blksz);
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return 0;
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}
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static const struct blk_ops nvmxip_blk_ops = {
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.read = nvmxip_blk_read,
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};
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U_BOOT_DRIVER(nvmxip_blk) = {
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.name = NVMXIP_BLKDRV_NAME,
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.id = UCLASS_BLK,
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.probe = nvmxip_blk_probe,
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.ops = &nvmxip_blk_ops,
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};
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32
drivers/mtd/nvmxip/nvmxip.h
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32
drivers/mtd/nvmxip/nvmxip.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* Authors:
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* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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*/
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#ifndef __DRIVER_NVMXIP_H__
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#define __DRIVER_NVMXIP_H__
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#include <blk.h>
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#define NVMXIP_BLKDRV_NAME "nvmxip-blk"
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#define NVMXIP_BLKDEV_NAME_SZ 20
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/**
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* struct nvmxip_plat - the NVMXIP driver plat
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*
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* @phys_base: NVM XIP device base address
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* @lba_shift: block size shift count
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* @lba: number of blocks
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*
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* The NVMXIP information read from the DT.
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*/
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struct nvmxip_plat {
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phys_addr_t phys_base;
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u32 lba_shift;
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lbaint_t lba;
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};
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#endif /* __DRIVER_NVMXIP_H__ */
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@ -89,6 +89,7 @@ enum uclass_id {
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UCLASS_NOP, /* No-op devices */
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UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */
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UCLASS_NVME, /* NVM Express device */
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UCLASS_NVMXIP, /* NVM XIP devices */
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UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */
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UCLASS_PANEL, /* Display panel, such as an LCD */
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UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
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