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22763 commits

Author SHA1 Message Date
Vignesh Raghavendra
8d1acfd8de ARM: dts: k3-am642: Correct timer frequency
Timer0 runs at 200MHz,and the clock-frequency defined in DT is
incorrect. Fix it.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-By: Nishanth Menon <nm@ti.com>
2022-04-04 19:02:04 -04:00
Hari Nagalla
92e46092f2 arch: arm: mach-k3: am642_init: Probe ESM nodes
On AM64x devices, it is possible to route Main ESM0 error events to MCU
ESM. MCU ESM high error output can trigger the reset logic to reset the
device. So, for these devices we expect two ESM device nodes in the
device tree, one for Main ESM and the another MCU ESM in the device tree.
 When these ESM device nodes are properly configired it is possible to
route the Main RTI0 WWDT output to the MCU ESM high output through Main
ESM and trigger a device reset when
CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.

On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node
configurations.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04 19:02:04 -04:00
Hari Nagalla
3d64cffa91 arm: dts: k3-am64: Add support for ESM device nodes
Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM
nodes to the AM64 device tree.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04 19:02:04 -04:00
Andre Przywara
5907357322 spl: mmc: extend spl_mmc_boot_mode() to take mmc argument
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.

Pass the pointer to the mmc struct to that function, so implementations
can make use of that.

Compile-tested for all users changed.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA)
Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3)
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-04 23:24:17 +01:00
Jernej Skrabec
35b786c1ba sunxi: clock: H6: Adjust PLL LDO before clock setup
BSP boot0 adjust PLL LDO regulator before clocks are initialized.
Let's do that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Jernej Skrabec
40a9c200af sunxi: clock: H6/H616: Add resistor calibration
BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Jernej Skrabec
1772771ac0 sunxi: prcm: Add a few registers
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Angelo Dureghello
482c1ccd1c sunxi: H3: fix non working console on uart2
Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.

Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Baltazár Radics
fbc8acf644 Add ethernet0 alias in Nanopi NEO's device tree
This syncs the sun8i-h3-nanopi-neo.dts from the Linux tree, from tag
v5.18-rc1.
The alias is required to enable automatic MAC address generation.

Signed-off-by: Baltazár Radics <baltazar.radics@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
a0ca51f70b sunxi: Support building a SPL as a TOC0 image
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
44de13d945 sunxi: Support SPL in both eGON and TOC0 images
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
458e59da5d pwm: sunxi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
aadf3d5383 sunxi: Remove options and setup code for I2C2-I2C4
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
3e42d919af sunxi: Remove non-DM GMAC pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
12bd00aafc net: sunxi_emac: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
b799eabc7e sunxi: pinctrl: Create the driver skeleton
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:23:50 +01:00
Dzmitry Sankouski
f8a1b33889 board: starqltechn: get board usable - add bootcmd and docs
U-boot is intended to replace linux kernel in android boot image(ABL), and
it's FIT payload to replace initramfs file. The boot process is similar to
boot image with linux:
- android bootloader (ABL) unpacks android boot image
- ABL sets `linux,initrd-start property` in chosen node in unpacked FDT
- ABL sets x0 register to FDT address, and passes control to u-boot
- u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable
- u-boot reads `linux,initrd-start` property,
and stores it in `prevbl_initrd_start_addr`

In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env
variable, and boils down to `bootm $prevbl_initrd_start_addr`.
If more control on boot process is desired, pack a boot script in
FIT image, and put it to default configuration

What done:
- strip unneeded config options
- add FIT image support
- add framebuffer node, u-boot logo and video console
- increase LMB_MAX_REGIONS, to store all linux dtb reserved memory regions
- add linux kernel image header

Uart driver causes hang, when u-boot is used in android boot image instead
of linux. Temporary disable console driver, until investigated and fixed.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
2022-04-04 15:06:11 -04:00
Dzmitry Sankouski
12a3e1ada0 arm: init: save previous bootloader data
When u-boot is used as a chain-loaded bootloader (replacing OS kernel),
previous bootloader leaves data in RAM, that can be reused.

For example, on recent arm linux system, when chainloading u-boot,
there are initramfs and fdt in RAM prepared for OS booting. Initramfs
may be modified to store u-boot's payload, thus providing the ability to
use chainloaded u-boot to boot OS without any storage support.

Two config options added:
- SAVE_PREV_BL_INITRAMFS_START_ADDR
  saves initramfs start address to 'prevbl_initrd_start_addr' environment
  variable
- SAVE_PREV_BL_FDT_ADDR
  saves fdt address to 'prevbl_fdt_addr' environment variable

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2022-04-04 14:53:26 -04:00
Tom Rini
01f1ab67f3 Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-04 10:48:44 -04:00
Tom Rini
8221c52d88 First set of u-boot-at91 features for the 2022.07 cycle
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Merge tag 'u-boot-at91-2022.07-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.07 cycle:

This feature set includes the new driver for the Atmel TCB timer,
alignment in DT for sama7g5 and sama7g5ek board, one Kconfig conversion
for external reset, and the usage of Galois tables from ROM for sama5d2
device.
2022-04-04 08:26:55 -04:00
Sean Anderson
53b953f2eb arm64: ls1046a: Support semihosting fallback
Use the semihosting_enabled function to determine whether or not to
enable semihosting devices. This allows for graceful fallback in the
event a debugger is not attached.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:54 -04:00
Sean Anderson
bbe310cdaf arm64: Catch non-emulated semihosting calls
If a debugger is not attached to U-Boot, semihosting calls will raise a
synchronous abort exception. Try to catch this and disable semihosting
so we can e.g. use another uart if one is available. In the immediate
case, we return an error, since it is not always possible to check for
semihosting beforehand (debug uart, user-initiated load command, etc.)

We handle all possible semihosting instructions, which is probably
overkill. However, we do need to keep track of what instruction set
we're using so that we don't suppress an actual error.

A future enhancement could try to determine semihosting capability by
inspecting the processor state.  There's an example of this at [1] for
RISC-V. The equivalent for ARM would inspect the monitor modei
enable/select bits of the DSCR. However, as the article notes, an
exception handler is still helpful in order to catch disconnected
debuggers.

[1] https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html#avoiding-hangs-when-a-debugger-is-not-connected

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00
Sean Anderson
385d69d76b arm: smh: Add option to detect semihosting
These functions are intended to support detecting semihosting and
falling back gracefully to alternative implementations. The test starts
by making semihosting call. SYS_ERRNO is chosen because it should not
mutate any state. If this semihosting call results in an exception
(rather than being caught by the debugger), then the exception handler
should call disable_semihosting() and resume execution after the call.

Ideally, this would just be part of semihosting by default, and not a
separate config. However, to reduce space ARM SPL doesn't include
exception vectors by default. This means we can't detect if a
semihosting call failed unless we enable them. To avoid forcing them to
be enabled, we use a separate config option. It might also be possible
to try and detect whether a debugger has enabled (by reading HDE from
DSCR), but I wasn't able to figure out a way to do this from all ELs.

This patch just introduces the generic code to handle detection. The
next patch will implement it for arm64 (but not arm32).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00
Sean Anderson
6d16157426 arm64: Import some ESR and SPSR defines from Linux
This imports some defines for esr and spsr from Linux v5.16. I have
modified the includes and fixed some indentation nits but otherwise it
is the same. There are a lot more defines than we need, but it doesn't
hurt.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00
Sean Anderson
e75d791c50 arm64: Save spsr in pt_regs
This register holds "pstate" which includes (among other things) the
instruction mode the CPU was in when the exception was taken. This is
necessary to correctly interpret instructions at elr.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00
Sean Anderson
e97ac4780d arm64: Save esr in pt_regs
To avoid passing around an extra register everywhere, save esr in
pt_regs like the rest. For proper alignment we need to have a second
(unused) register. All the printfs have to be adjusted, since
it's now an unsigned long and not an int.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00
Sean Anderson
93c3d32970 ls1046ardb: Add support for JTAG boot
This adds support for booting entirely from JTAG while using a
hard-coded RCW. With these steps, it is not necessary to program a
"good" RCW using CodeWarrior. The method here can be performed with any
JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP
(albeit very slowly).

These steps require LS1046A support in OpenOCD, which was added in [1].

[1] 5b70c1f679/

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
[trini: Add reference to doc/board/nxp/ls1046ardb.rst]
2022-04-01 16:56:44 -04:00
Sean Anderson
3ea744e873 arm: smh: Add some functions for working with the host console
This adds three wrappers around the semihosting commands for reading and
writing to the host console. We use the more standard getc/putc/puts
names instead of readc/writec/write0 for familiarity.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
dcc4f9623e arm: smh: Remove smhload command
This command's functionality is now completely implemented by the
standard fs load command. Convert the vexpress64 boot command (which is
the only user) and remove the implementation.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
dbf6f7c952 cmd: fdt: Use start/size for chosen instead of start/end
Most U-Boot command deal with start/size instead of start/end. Convert
the "fdt chosen" command to use these semantics as well. The only user
of this subcommand is vexpress, so convert the smhload command to use
this as well. We don't bother renaming the variable in vexpress64's
bootcommand, since it will be rewritten in the next commit.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
8e1c9fe243 spl: Add semihosting boot method
This adds a boot method for loading the next stage from the host. It is
mostly modeled off of spl_load_image_ext. I am not really sure why/how
spl_load_image_fat uses three different methods to load the image, but
the simple case seems to work OK for now.

To control the presence of this boot method, we add a config symbol.
While we're at it, we update the original semihosting config symbol.

I think semihosting has some advantages of other forms of JTAG boot.
Common other ways to boot from JTAG include:

- Implementing DDR initialization through JTAG (typically with dozens of
  lines of TCL) and then loading U-Boot. The DDR initialization
  typically uses hard-coded register writes, and is not easily adapted
  to different boards. BOOT_DEVICE_SMH allows booting with SPL,
  leveraging U-Boot's existing DDR initialization code. This is the
  method used by NXP's CodeWarrior IDE on Layerscape processors (see
  AN12270).
- Loading a bootloader into SDRAM, waiting for it to initialize DDR, and
  then loading U-Boot. This is tricky, because the debugger must stop the
  boot after the bootloader has completed its work. Trying to load
  U-Boot too early can cause failure to boot. This is the method used by
  Xilinx with its Zynq(MP) processors.
- Loading SPL with BOOT_DEVICE_RAM and breaking before SPL loads the
  image to load U-Boot at the appropriate place. This can be a bit
  tricky, because the load address is dependent on the header size. An
  elf with symbols must also be used in order to stop at the appropriate
  point. BOOT_DEVICE_SMH can be viewed as an extension of this process,
  where SPL automatically stops and tells the host where to place the
  image.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
12a05b3bcd arm: smh: Add some file manipulation commands
In order to add filesystem support, we will need to be able to seek and
write files. Add the appropriate helper functions.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
79f6ad6a7b arm: smh: Document functions in header
This adds some documentation for semihosting functions in the header.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
80e62ccfa6 arm: smh: Return errno on error
Instead of printing in what are now library functions, try to return a
numeric error code. This also adjust some functions (such as read) to
behave more similarly to read(2). For example, we now return the number
of bytes read instead of failing immediately on a short read.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
eff77c3a24 arm: smh: Use numeric modes for smh_open
There's no point in using string constants for smh_open if we are just
going to have to parse them. Instead, use numeric modes. The user needs
to be a bit careful with these, since they are much closer semantically
to string modes used by fopen(3) than the numeric modes used with
open(2).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Sean Anderson
b10f724807 arm: smh: Export semihosting functions
This exports semihosting functions for use in other files. The header is
in include/ and not arm/include/asm because I anticipate that RISC-V may
want to add their own implementation at some point.

smh_len_fd has been renamed to smh_flen to more closely match the
semihosting spec.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 15:03:13 -04:00
Peter Hoyes
8d78a6b674 vexpress64: Add ARMv8R-64 board variant
The ARMv8-R64 architecture introduces optional VMSA (paging based MMU)
support in the EL1/0 translation regime, which makes that part mostly
compatible to ARMv8-A.

Add a new board variant to describe the "BASE-R64" FVP model, which
inherits a lot from the existing v8-A FVP support. One major difference
is that the memory map in "inverted": DRAM starts at 0x0, MMIO is at
2GB [1].

 * Create new TARGET_VEXPRESS64_BASER_FVP target, sharing most of the
   exising configuration.
 * Implement inverted memory map in vexpress_aemv8.h
 * Create vexpress_aemv8r defconfig
 * Provide an MMU memory map for the BASER_FVP
 * Update vexpress64 documentation

At the moment the boot-wrapper is the only supported secure firmware. As
there is no official DT for the board yet, we rely on it being supplied
by the boot-wrapper into U-Boot, so use OF_HAS_PRIOR_STAGE, and go with
a dummy DT for now.

[1] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
[Andre: rebase and add Linux kernel header]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[trini: Add MAINTAINERS entry for Peter]
2022-04-01 15:03:03 -04:00
Andre Przywara
8a0a8ff52c vexpress64: fvp: add distro_boot support
So far the FVP model just supports booting through semihosting, so by
loading files from the host the model is running on. This allows for
quick booting of new kernels (or replacing DTBs), but prevents more
featureful boots like using UEFI.

Enable the distro_boot feature, and provide a list of possible boot
sources that U-Boot should check:
- For backwards compatibility we start with semihosting, which gets its
  commands migrated from CONFIG_BOOTCOMMAND into the distro_boot
  infrastructure. This is also slightly tweaked to fail graceful in case
  the required files could not be found.
- Next we try to use a user provided script, that could be easily
  placed into memory using the model command line.
- Since we gained virtio support with the enablement of OF_CONTROL,
  let's check virtio block devices next. This is where UEFI boot can
  be easily used, for instance by providing a distro installer .iso
  file through virtio-blk.
- Networking is now provided by virtio as well, so enable the default
  PXE and DHCP boot flows, mostly because we can.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-01 14:58:16 -04:00
Andre Przywara
5865038257 vexpress64: move hardware setting from defconfig to Kconfig
The defconfigs for the Arm Juno board and the FVP model are quite large,
setting a lot of platform-fixed variables like SYS_TEXT_BASE.
As those values are not really a user choice, let's provide default
values for them in our Kconfig file, so a lot of cruft can be removed
from the defconfig files.
This also moves the driver selection out of there, since this is again
not something a user should really decide on. Instead we allow users to
enable or disable subsystems, and select the appropriate drivers based
on that in the Kconfig file.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-01 14:57:46 -04:00
Andre Przywara
c0fce92956 vexpress64: fvp: enable OF_CONTROL
The FVP base model is relying on a DT for Linux operation, so there is
no reason we would need to rely on hardcoded information for U-Boot.
Letting U-Boot use a DT will open up the usage of actual peripherals,
beyond the support for semihosting only.

Enable OF_CONTROL in the Kconfig, and use the latest dts files from
Linux. Depending on whether we use the boot-wrapper or TF-A, there is
already a DTB provided or not, respectively.

To cover the boot-wrapper, we add an arm64 Linux kernel header, which
allows the boot-wrapper to treat U-Boot like a Linux kernel. U-Boot will
find the pointer to the DTB in x0, and will use it.

Even though TF-A carries a DT, at the moment this is not made available
to non-secure world, so to not break users, we use the U-Boot provided
DTB copy in that case. For some reason TF-A puts some DT like structure
at the address x0 is pointing at, but that is very small and doesn't
carry any hardware information. Make the code to ignore those small DTBs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-01 14:55:38 -04:00
Andre Przywara
71fa41ebfc arm: dts: Add Arm FVP Fastmodel RevC .dts files from Linux
The Arm Fixed Virtual Platform (FVP) is a software model for an
artificial ARM platform, it is available for free on the Arm website[1].

Add the devicetree files for the latest RevC version, as we will need
them to enable OF_CONTROL for the vexpress_aemv8a_semi board.

This is a verbatim copy of the respective files from Linux v5.17-rc6,
which is unchanged from the v5.16 release.

[1] https://developer.arm.com/tools-and-software/simulation-models/fast-models

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-01 14:55:38 -04:00
Andre Przywara
fac7fc43cf vexpress64: Kconfig: move board definitions out of arch/arm
At the moment we define three "VExpress64" boards in arch/arm/Kconfig,
plus have a second Kconfig file in board/armltd/Kconfig.
One of those three boards is actually bogus (TARGET_VEXPRESS64_AEMV8A),
that stanza looks like being forgotten in a previous cleanup.

To remove the clutter from the generic Kconfig file, just define some
ARCH_VEXPRESS64 symbol there, enable some common options, and do the
board/model specific configuration in the board/armltd Kconfig file.

That allows to streamline and fine tune the configuration later, and
to also pull a lot of "non user choices" out of the defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-01 14:55:38 -04:00
Tom Rini
e4d741f8ab Convert CONFIG_SYS_MONITOR_BASE to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_MONITOR_BASE

Note that for how this is re-used on some PowePC platforms, we introduce
CONFIG_SPL_SYS_MONITOR_BASE and CONFIG_TPL_SYS_MONITOR_BASE and use the
CONFIG_VAL macro to get the correct value at build time, in the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:47 -04:00
Tom Rini
f2428acbf1 Convert CONFIG_E300 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_E300
   CONFIG_E5500

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:47 -04:00
Tom Rini
225aaacf36 db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP
The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to
CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-04-01 10:28:47 -04:00
Tom Rini
b20e79f0bb Convert CONFIG_CLOCK_SYNTHESIZER to Kconfig
This converts the following to Kconfig:
   CONFIG_CLOCK_SYNTHESIZER

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:47 -04:00
Tom Rini
a9ee1ad95a exynos: Drop CONFIG_CLK_*
We only set one of these values ever at this point, so remove dead code.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-04-01 10:28:47 -04:00
Tom Rini
c6c0e56ff8 keymile: Move sourcing of common Kconfig
The way board/keymile/Kconfig is written protects the options there from
being parsed on non-keymile platforms.  We cannot however safely source
this file from multiple locations.  This does not manifest as a problem
currently as there are no choice statements inside of this file (nor the
sub-Kconfig files it sources).  However, moving some target selection to
one of these files exposes the underlying problem.  Rework things so
that we have this file sourced in arch/Kconfig.

Cc: Holger Brunck <holger.brunck@hitachienergy.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-04-01 10:28:46 -04:00
Tom Rini
3c205a6e4a Convert CONFIG_MCFRTC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MCFRTC
   CONFIG_SYS_MCFRTC_BASE

While at it, remove '#undef RTC_DEBUG' from these config files.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:46 -04:00
Tom Rini
143a365a5b Convert CONFIG_MCFTMR to Kconfig
This converts the following to Kconfig:
   CONFIG_MCFTMR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:46 -04:00
Tom Rini
f88e9f5ab8 Convert CONFIG_CF_DSPI to Kconfig
This converts the following to Kconfig:
   CONFIG_CF_DSPI

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:46 -04:00
Tom Rini
6815a66ad7 am33xx: musb: Remove unused configuration logic
At this point DM and OF_CONTROL are used to configure how the USB ports
are enabled, with the exception of in SPL and no SPL_OF_CONTROL.  Remove
a bunch of now unused logic to simplify the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-01 10:28:45 -04:00
Francesco Dolcini
182887735c ARM: dts: colibri-imx6ull: fix mac address passing
colibri-imx6ull ethernet device is fec2, while the optional secondary
ethernet is fec1, update the ethernet aliases in the .dts file so that
ethaddr is set to fec2 and eth1addr to fec1.

Without this change the ethernet interfaces have a different
mac address between Linux and U-Boot.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-04-01 10:05:24 -04:00
Clément Léger
3d3fdaf075 ARM: dts: at91: sama5d2: add u-boot, dm-pre-reloc property for TCB
In order to use the TCB early in boot and in the SPL, add
u-boot,dm-pre-reloc property for the TCB and the clock that is used by
the driver (tcb0_clk).

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2022-04-01 15:42:46 +03:00
Clément Léger
757647313d ARM: dts: at91: sama5d2: add TCB node
Add the device-tree node to describe the TCB timer.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2022-04-01 15:42:46 +03:00
Clément Léger
d29e55a6c2 ARM: dts: at91: sama5d2: add AIC node
When using interrupts property, a global interrupt controller needs to
be added to avoid warnings when compiling device-tree:

 arch/arm/dts/at91-sama5d2_xplained.dtb: Warning (interrupts_property):
    /ahb/apb/timer@f800c000: Missing interrupt-parent

Add AIC node as the sama5d2 global interrupt controller.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2022-04-01 15:42:46 +03:00
Clément Léger
70fb1ae9dd timer: atmel_tcb_timer: add atmel_tcb driver
Add a driver for the timer counter block that can be found on sama5d2.
This driver will be used when booting under OP-TEE since the pit timer
which is part of the SYSC is secured. Channel 1 & 2 are configured to
be chained together which allows to have a 64bits counter.

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2022-04-01 15:42:46 +03:00
Eugen Hristev
746b738224 ARM: dts: at91: sama7g5/sama7g5ek: align with Linux DT
Align the DT for sama7g5 SoC and sama7g5 EK board with Linux devicetree
in version 5.18.

Some things remain still different, due to some things yet unimplemented in
certain drivers. These include in PMC, pinctrl, and others.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-04-01 15:42:46 +03:00
Eugen Hristev
29641527ac ARM: dts: at91: rename sama7g5ek.dts to at91-sama7g5ek.dts
In Linux this DT file is named at91-sama7g5ek.dts. Rename it accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-04-01 15:42:46 +03:00
Tudor Ambarus
f206af80f8 ARM: at91: sama7g5: Reset external devices at software reset
sama7g5 and other SoCs (sama5d3, sam9x60) define in the Reset Controller
a RSTC_CR.EXTRST bit that asserts the nrst_out pin which resets external
devices.

This is particular useful for external devices that are configured in
stateful modes which can not be undone without reconfiguring the device
or without resetting the device. An example is an SPI NOR flash that is
configured in octal mode. The do_reset u-boot cmd does not call any
driver's remove method, but merely resets the CPU. As the code was, this
left the flash in octal mode, being impossible for the first stage boot
loaders to recover/identify the flash after a "software reset".
RSTC_CR.EXTRST comes in handy here, as it can be set at "software reset"
to assert low the nrst_out pin during a time defined by the RSTC_MR.ERSTL
field and reset the external devices (including the SPI NOR flash in the
example).
nrst_out is always asserted at "user reset" and it resets the external
devices correctly. Asserting nrst_out at "software reset" should behave
in a similar way. The only difference that I could find between the two
types of resets in regards to the nrst_out signal, is that at "user reset"
timing diagram the "Processor and Peripherals Reset Line" rises after six
MD_SLCK cycles after the nrst_out line rose, while at the "software reset"
timing diagram the "Processor and Peripherals Reset Line" is active for
3 MD_SLCK cycles + 2 MCK cycles. In other words, in the "software reset"
case the nrst_out signal can be active for a longer period of time than the
"Processor and Peripherals Reset Line" active time, depending on the
RSTC_MR.ERSTL value.
Using the default value (zero) for RSTC_MR.ERSTL, worked just fine for the
sama7g5 case. Tested QSPI0 and GMAC0/GMAC1 on sama7g5ek rev 4 after a
software reset with RSTC_CR.EXTRST=1 and RSTC_MR.ERSTL=0.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-04-01 15:42:46 +03:00
Tudor Ambarus
af612ee418 configs: Convert AT91RESET_EXTRST to Kconfig
Convert AT91RESET_EXTRST to Kconfig for easier integration. The symbol is
not configurable from menuconfig, it will be automatically selected by SoCs
that select it explicitly via the "select" directive.
AT91RESET_EXTRST sets the Reset Controller's RSTC_CR.EXTRST bit which
asserts the nrst_out pin that resets external devices.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-04-01 15:42:46 +03:00
Tudor Ambarus
5576bb36ad ARM: at91: sama5d2: Enable the use of Galois Tables from ROM
sama5d2 contains in its ROM memory BCH code tables for NAND Flash ECC
correction. Enable the use of the GF tables defined in ROM. This should
speed up the boot process, as the tables are no longer constructed at
runtime. Tested with sama5d2-ptc-ek.

Reported-by: David Mosberger-Tang <davidm@egauge.net>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2022-04-01 15:42:46 +03:00
Philippe Reynes
059df5624b arch: Kconfig: imply BINMAN for SANDBOX
To be able to use the tool binman on sandbox,
the config SANDBOX should imply BINMAN.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-03-31 14:12:01 -04:00
Andy Shevchenko
ce1cbf1ae0 Revert "x86: Move FACP table into separate functions"
Before the culprit patch (see BugLink for the details):

  => acpi list
  Name      Base   Size  Detail
  ----  --------  -----  ------
  RSDP  000e4500     24  v02 U-BOOT
  RSDT  000e4530     38  v01 U-BOOT U-BOOTBL 20220401 INTL 0
  XSDT  000e45e0     4c  v01 U-BOOT U-BOOTBL 20220401 INTL 0
  CSRT  000e5490     58  v00 U-BOOT U-BOOTBL 20220401 INTL 0
  FACP  000e54f0    114  v06 U-BOOT U-BOOTBL 20220401 INTL 0
  DSDT  000e4780    c06  v02 U-BOOT U-BOOTBL 10000 INTL 20200925
  FACS  000e4740     40
  MCFG  000e5610     3c  v01 U-BOOT U-BOOTBL 20220401 INTL 0
  SPCR  000e5650     50  v02 U-BOOT U-BOOTBL 20220401 INTL 0
  APIC  000e56a0     48  v02 U-BOOT U-BOOTBL 20220401 INTL 0

After the culprit patch:

  => acpi list
  Name      Base   Size  Detail
  ----  --------  -----  ------
  RSDP  000e4500     24  v02 U-BOOT
  RSDT  000e4530     34  v01 U-BOOT U-BOOTBL 20220401 INTL 0
  XSDT  000e45e0     44  v01 U-BOOT U-BOOTBL 20220401 INTL 0
  CSRT  000e53a0     58  v00 U-BOOT U-BOOTBL 20220401 INTL 0
  MCFG  000e5520     3c  v01 U-BOOT U-BOOTBL 20220401 INTL 0
  SPCR  000e5560     50  v02 U-BOOT U-BOOTBL 20220401 INTL 0
  APIC  000e55b0     48  v02 U-BOOT U-BOOTBL 20220401 INTL 0

As a result Linux kernel can't find mandatory tables and fails
to boot.

Hence, revert it for good.

This reverts commit 379d3c1fd6.

BugLink: https://lore.kernel.org/all/20220131225930.GJ7515@bill-the-cat/
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-03-31 08:27:52 -04:00
Tom Rini
dd2986ac11 powerpc: Fix incorrect SYS_IMMR migration values
When migrating SYS_IMMR, I didn't allow for boards to provide
non-default values here.  This lead to an incorrect migration on the
platforms where CONFIG_SYS_IMMR is set to CONFIG_SYS_CCSRBAR and
CONFIG_SYS_CSSRBAR is NOT the same as CONFIG_SYS_CCSRBAR_DEFAULT.  Add
text to the prompt so that non-default values can be used and re-migrate
the platforms that have CONFIG_SYS_IMMR=CONFIG_SYS_CSSRBAR where
CONFIG_SYS_CSSRBAR != CONFIG_SYS_CCSRBAR_DEFAULT.

Fixes: be7dbb60c5 ("Convert CONFIG_SYS_IMMR to Kconfig")
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Pali Rohár <pali@kernel.org>
2022-03-31 08:27:52 -04:00
Sai Krishna Potthuri
8bd9e2f631 arm64: zynqmp: Add resets property to sdhci nodes
Add "resets" property to sdhci nodes.
resets property is used to reset the SD host controller when
dynamic configuration support is enabled.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/f1fe39259c45a37aae56c2835ee8ba187c889d25.1646060367.git.michal.simek@xilinx.com
2022-03-29 09:12:58 +02:00
Simon Glass
77f46f0607 video: fsl: colibri_vf: Drop FSL DCU driver
This does not use driver model and is more than two years past the
migration date. Drop it.

It can be added back later if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28 20:18:07 +02:00
Simon Glass
1fa43cad86 video: Drop references to CONFIG_VIDEO et al
Drop the Kconfigs which are not used and all references to them. In
particular, this drops CONFIG_VIDEO to avoid confusion and allow us to
eventually rename CONFIG_DM_VIDEO to CONFIG_VIDEO.

Also drop the prototype for video_get_info_str() which is no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
2022-03-28 20:17:07 +02:00
Simon Glass
fff49e01d8 video: Drop video_fb header
This is not used now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28 20:16:46 +02:00
Simon Glass
9b39da6e42 video: nexell: Drop unused and invalid code
Unfortunately this driver uses the old video structure to store things.
This is not supported with driver model.

Drop the old code and comment out the other pieces, so the maintainer can
take a look.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28 20:16:30 +02:00
Tom Rini
34d2b7f203 Prepare v2022.04-rc5
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Merge tag 'v2022.04-rc5' into next

Prepare v2022.04-rc5
2022-03-28 12:36:49 -04:00
Mark Kettenis
8b9c77053c arm: apple: Fix mem layout
The current approach for setting the environment variables that
describe the memory layout runs the risk of overlapping with
reserved memory regions. Use the lmb code to derive the addresses
for these variables instead.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-28 08:22:17 -04:00
Hector Martin
66899c8d19 arm: apple: Increase RTKit timeout
The firmware on larger NVMe drives needs more than 100ms to come up.
Change the timeout to 1s.

Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-28 08:22:17 -04:00
Andre Przywara
85da558762 sunxi: dts: Update RGMII phy-mode properties
Commit f11513d997 ("net: phy: realtek: Add tx/rx delay config for
8211e") made the Realtek PHY driver honour the phy-mode DT property,
to set up the proper delay scheme for the RX and TX lines. A similar
change in the kernel revealed that those properties were mostly wrong.
The kernel DTs got updated over the last few months, but we were missing
out on the U-Boot version.

Just sync in the phy-mode properties from the mainline kernel,
v5.17-rc7, to avoid the breaking DT sync that late in the cycle.

This fixes Ethernet operation on the affected boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-03-26 00:16:44 +00:00
Andre Przywara
e943753dc2 sunxi: Fix old GMAC pinmux setup
Commit 5bc4cd05d7 ("sunxi: move non-essential code out of s_init()")
moved the call to eth_init_board() from s_init() into board_init_f().
This means it's now only called from the SPL, which makes sense for
most of the other moved low-level functions. However the GMAC pinmux and
clock setup in eth_init_board() was not happy about that, so it broke
the sun7i GMAC.

Since Ethernet is of no use in the SPL anyway, just move the call into
board_init(), which is only run in U-Boot proper.

This fixes Ethernet operation for the A20 SoCs, which broke in
v2022.04-rc1, with the above mentioned commit.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Petr Štetiar <ynezz@true.cz> [a20-olinuxino-lime2]
2022-03-26 00:16:06 +00:00
Billy Tsai
5b66ebb4e9 ARM: dts: ast2600: Add PWM to device tree
Add the PWM node and enable it for AST2600 EVB

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-25 13:35:50 -04:00
Billy Tsai
73ee1f261e pinctrl: Add the pinctrl setting for PWM.
This patchs add the signal description array for PWM pinctrl settings.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-03-25 13:35:50 -04:00
Pali Rohár
f02b396548 sandbox: video: Replace PCI_CLASS_* macros by one from pci_ids.h
Replace old macros PCI_CLASS_CODE_COMM and PCI_CLASS_SUB_CODE_COMM_SERIAL
by new macros defined in pci_ids.h. Old macros would be deleted in followup
commit.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-25 13:35:50 -04:00
Sean Anderson
f38cb2aca7 Split CONFIG_CC_OPTIMIZE_FOR_SIZE into two configs
This adds a separate CONFIG_CC_OPTIMIZE_FOR_SPEED option in a choice,
in preparation for adding another optimization option. Also convert SH's
makefile to use this new option.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-25 13:35:50 -04:00
Tom Rini
b40d2b2891 Convert CONFIG_BACKSIDE_L2_CACHE to Kconfig
This converts the following to Kconfig:
   CONFIG_BACKSIDE_L2_CACHE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25 12:01:15 +00:00
Tom Rini
16199a8b96 Convert CONFIG_PHY_RESET_DELAY to Kconfig
This converts the following to Kconfig:
   CONFIG_PHY_RESET_DELAY

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25 12:01:15 +00:00
Tom Rini
1d5686acfd Convert CONFIG_SYS_FAULT_ECHO_LINK_DOWN to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FAULT_ECHO_LINK_DOWN

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25 12:01:15 +00:00
Tom Rini
29cc2b542d Convert CONFIG_RESET_PHY_R to Kconfig
This converts the following to Kconfig:
   CONFIG_RESET_PHY_R

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25 12:01:15 +00:00
Tom Rini
5a606a4c97 Convert CONFIG_AT91_WANTS_COMMON_PHY to Kconfig
This converts the following to Kconfig:
   CONFIG_AT91_WANTS_COMMON_PHY

Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-25 12:01:15 +00:00
Pali Rohár
8285b928c5 arm: a37xx: espressobin: Fix non-working SPI
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke SPI support on some Espressobin boards and results in
following U-Boot error:

  Loading Environment from SPIFlash... jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f7, 30, 0b
  *** Warning - spi_flash_probe_bus_cs() failed, using default environment

Before that commit DT node for SPI was called 'spi-flash@0' and after
that commit it is called 'flash@0'. Before that commit 'spi-max-frequency'
was set to 50000000 and after it is 104000000.

Rename DT node 'spi-flash@0 in armada-3720-espressobin-u-boot.dtsi to
'flash@0' and set custom U-Boot 'spi-max-frequency' back to 50000000.

With this change SPI is working on Espressobin again and it is detected
with JEDEC ids ef, 60, 16 on our tested unit.

  Loading Environment from SPIFlash... SF: Detected w25q32dw with page size 256 Bytes, erase size 4 KiB, total 4 MiB
  OK

Note that it is unknown why spi-max-frequency with value 104000000 does not
work in U-Boot as it works fine with Linux kernel. Also note that in
defconfig file configs/mvebu_espressobin-88f3720_defconfig is set option
CONFIG_SF_DEFAULT_SPEED=40000000 which is different value than in DT.

Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-24 08:09:30 +01:00
Marek Behún
3789b6a92f arm: mvebu: dts: turris_mox: fix non-working USB port
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke USB port on Turris MOX, because in Linux' DTS the bus
voltage supply is described as a `phy-supply` property of connector
node, a mechanism that is not supported in U-Boot yet.

For now, fix this by adding `vbus-supply` to usb3 node.

Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-23 11:47:38 +00:00
Tom Rini
a958c58571 binman FIT improvements
various minor sandbox improvements
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Merge tag 'dm-pull-18mar22' of https://source.denx.de/u-boot/custodians/u-boot-dm into next

binman FIT improvements
various minor sandbox improvements
2022-03-19 09:09:58 -04:00
Simon Glass
acc874a4c5 sandbox: Add the handoff header for spl
This defines a function declared in handoff.h so add the header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-18 19:24:24 -06:00
Simon Glass
d02f99dd67 sandbox: Show a message when writing out the ram buffer
If state is not being written, but RAM is, we should still show a message,
so it is clear that this is happening.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-18 19:24:24 -06:00
Tom Rini
cb81640011 Convert CONFIG_ATMEL_LEGACY to Kconfig
This converts the following to Kconfig:
   CONFIG_ATMEL_LEGACY

Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:18 -04:00
Tom Rini
5644f3b19d Convert CONFIG_AT91_GPIO_PULLUP to Kconfig
This converts the following to Kconfig:
   CONFIG_AT91_GPIO_PULLUP

Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:18 -04:00
Tom Rini
675e703d91 Convert CONFIG_AT91SAM9260 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_AT91SAM9260
   CONFIG_AT91SAM9G20
   CONFIG_AT91SAM9XE
   CONFIG_AT91SAM9261
   CONFIG_AT91SAM9263
   CONFIG_AT91SAM9G45
   CONFIG_AT91SAM9M10G45
   CONFIG_AT91SAM9N12
   CONFIG_AT91SAM9RL
   CONFIG_AT91SAM9X5
   CONFIG_SAM9X60
   CONFIG_SAMA7G5
   CONFIG_SAMA5D2
   CONFIG_SAMA5D3
   CONFIG_SAMA5D4

These options are already select'd as needed, so we're just cleaning up
files here.

Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
ae3f467e84 Convert CONFIG_AM335X_USB0 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_AM335X_USB0
   CONFIG_AM335X_USB0_MODE
   CONFIG_AM335X_USB1
   CONFIG_AM335X_USB1_MODE

We do this by introducing specific options for static configuration of
USB0/USB1 in SPL rather than defining CONFIG_AM335X_USBx_MODE to the
enum value being used.  Furthermore, with how the code is used now we do
not need to have OTG mode exposed as an option here, so remove that.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
5d6a64f71d Remove CONFIG_HAS_ETH0 et al symbols
This converts removes the following symbols:
   CONFIG_HAS_ETH0
   CONFIG_HAS_ETH1
   CONFIG_HAS_ETH2
   CONFIG_HAS_ETH3

This is because at this point, only the ids8313 platform was using the
code which was controlled by these symbols.  In turn, this code already
performs error checking on being able to perform the device tree fixup.
Rather than convert these to Kconfig for a single platform, update the
code to not need these checks and remove them from all the platforms
they were unused on.

Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
0b5870c3f5 powerpc: Move CONFIG_BPTR_VIRT_ADDR out of CONFIG namespace
This is only used in one file, and is never overridden.  Move this out
of CONFIG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
01d1b99c9b Convert CONFIG_NET_RETRY_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_NET_RETRY_COUNT

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
5d4e863bf8 Convert CONFIG_ARP_TIMEOUT to Kconfig
This converts the following to Kconfig:
   CONFIG_ARP_TIMEOUT

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
5f7c886c82 Convert CONFIG_A008044_WORKAROUND to Kconfig
This converts the following to Kconfig:
   CONFIG_A008044_WORKAROUND

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
fdd0da4ca4 Convert CONFIG_A003399_NOR_WORKAROUND to Kconfig
This converts the following to Kconfig:
   CONFIG_A003399_NOR_WORKAROUND

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 12:48:17 -04:00
Tom Rini
b53a280b81 Convert CONFIG_ARMV8_SWITCH_TO_EL1 to Kconfig
This converts the following to Kconfig:
   CONFIG_ARMV8_SWITCH_TO_EL1

Cc: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
2022-03-18 12:48:17 -04:00
Tom Rini
0da35fa8d6 Convert CONFIG_ARMV7_SECURE_BASE et al to Kconfig
This converts the following to Kconfig:
   CONFIG_ARMV7_SECURE_BASE
   CONFIG_ARMV7_SECURE_MAX_SIZE
   CONFIG_ARMV7_SECURE_RESERVE_SIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-18 08:43:25 -04:00
Alper Nebi Yasak
b42297ba81 rockchip: Set default LNX_KRNL_IMG_TEXT_OFFSET_BASE to SYS_TEXT_BASE
U-Boot can be chainloaded from vendor firmware on ARM64 chromebooks from
a GPT partition (roughly the same as in doc/chromium/chainload.rst), but
an appropriate image header must be built-in to the U-Boot binary by
enabling LINUX_KERNEL_IMAGE_HEADER.

This header has a field for an image load offset from 2MiB alignment
which must also be customized through LNX_KRNL_IMG_TEXT_OFFSET_BASE.
Set it equal to SYS_TEXT_BASE by default for Rockchip boards, which
happens to make this offset zero and works fine on chromebook_kevin
both for chainloading and bare-metal use.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-03-18 18:12:03 +08:00
Marty E. Plummer
6d36e92d28 rockchip: rk3399: Add support for chromebook_kevin
Add support for Kevin, an RK3399-based convertible chromebook that is
very similar to Bob. This patch is mostly based on existing support for
Bob, with only minor changes for Kevin-specific things.

Unlike other Gru boards, coreboot sets Kevin's center logic to 925 mV,
so adjust it here in the dts as well. The rk3399-gru-kevin devicetree
has an unknown event code reference which has to be defined, set it
to the Linux counterpart. The new defconfig is copied from Bob with the
diffconfig:

     DEFAULT_DEVICE_TREE "rk3399-gru-bob" -> "rk3399-gru-kevin"
     DEFAULT_FDT_FILE "rockchip/rk3399-gru-bob.dtb" -> "rockchip/rk3399-gru-kevin.dtb"
     VIDEO_ROCKCHIP_MAX_XRES 1280 -> 2400
     VIDEO_ROCKCHIP_MAX_YRES 800 -> 1600
    +TARGET_CHROMEBOOK_KEVIN y

With this Kevin can boot from SPI flash to a usable U-Boot prompt on the
display with the keyboard working, but cannot boot into Linux for
unknown reasons.

eMMC starts in a working state but fails to re-init, microSD card works
but at a lower-than-expected speed, USB works but causes a hang on
de-init. There are known workarounds to solve eMMC and USB issues.

Cc: Marty E. Plummer <hanetzer@startmail.com>
Cc: Simon Glass <sjg@chromium.org>
[Alper: commit message, resync config with Bob, update MAINTAINERS,
        add to Rockchip doc, add Kconfig help message, set regulator]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-03-18 18:12:03 +08:00
Simon Glass
8ba1ade3f8 rockchip: gru: Add more devicetree settings
This adds some devicetree settings for the Gru-based boards, based on
what works on a Kevin board.

Gru-based boards usually have an 8MiB SPI flash chip and boot from it.
Make the u-boot.rom file intended to be flashed on it match its size.
Add properties for booting from SPI, and only try to boot from SPI as
MMC and SD card don't seem to work in SPL yet.

The Chromium OS EC needs a delay between transactions so it can get
itself ready. Also it currently uses a non-standard way of specifying
the interrupt. Add these so that the EC works reliably.

The Rockchip Embedded DisplayPort driver is looking for a rockchip,panel
property to find the panel it should work on. Add the property for the
Gru-based boards.

The U-Boot GPIO controlled regulator driver only considers the
"enable-gpios" devicetree property, not the singular "enable-gpio" one.
Some devicetree source files have the singular form as they were added
to Linux kernel when it used that form, and imported to U-Boot as is.
Fix one instance of this in the Gru boards' devicetree to the form that
works in U-Boot.

The PWM controlled regulator driver complains that there is no init
voltage set for a regulator it drives, though it's not clear which one.
Set them all to the voltage levels coreboot sets them: 900 mV.

The RK3399 SoC needs to know the voltage level that some supplies
provides, including one fixed 1.8V audio-related regulator. Although
this synchronization is currently statically done in the board init
functions, a not-so-hypothetical driver that does this dynamically would
query the regulator only to get -ENODATA and be confused. Make sure
U-Boot knows this supply is at 1.8V by setting its limits to that.

Most of this is a reapplication of commit 08c85b57a5 ("rockchip: gru:
Add extra device-tree settings") whose changes were removed during a
sync with Linux at commit 167efc2c7a ("arm64: dts: rk3399: Sync
v5.7-rc1 from Linux"). Apply things to rk3399-gru-u-boot.dtsi instead so
they don't get lost again.

Signed-off-by: Simon Glass <sjg@chromium.org>
[Alper: move to -u-boot.dtsi, rewrite commit message, add more nodes]
Co-developed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-03-18 18:12:03 +08:00
Tom Rini
297e6eb8dc Xilinx changes for v2022.07-rc1
microblaze:
 - Add support for reserved memory
 
 xilinx:
 - Update FRU code with MAC reading
 
 zynqmp:
 - Remove double AMS setting
 - DT updates (mostly for SOMs)
 - Add support for zcu106 rev 1.0
 
 zynq:
 - Update nand binding
 
 nand:
 - Aligned zynq_nand to upstream DT binding
 
 net:
 - Add support for ethernet-phy-id
 
 mmc:
 - Workaround CD in zynq_sdhci driver also for ZynqMP
 - Add support for dynamic/run-time SD config for SOMs
 
 gpio:
 - Add driver for slg7xl45106
 
 firmware:
 - Add support for dynamic SD config
 
 power-domain:
 - Update zynqmp driver with the latest firmware
 
 video:
 - Add skeleton driver for DP and DPDMA
 
 i2c:
 - Fix i2c to work with QEMU
 
 pinctrl:
 - Add driver for zynqmp pinctrl driver
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Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.07-rc1

microblaze:
- Add support for reserved memory

xilinx:
- Update FRU code with MAC reading

zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0

zynq:
- Update nand binding

nand:
- Aligned zynq_nand to upstream DT binding

net:
- Add support for ethernet-phy-id

mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs

gpio:
- Add driver for slg7xl45106

firmware:
- Add support for dynamic SD config

power-domain:
- Update zynqmp driver with the latest firmware

video:
- Add skeleton driver for DP and DPDMA

i2c:
- Fix i2c to work with QEMU

pinctrl:
- Add driver for zynqmp pinctrl driver
2022-03-16 12:52:02 -04:00
Michal Simek
0ac03fbab5 arm64: zynqmp: Add pinctrl emmc description to SM-K26
Production SOM has emmc on it and make sense to describe pin description to
be able use EMMC if it is not configured via psu_init.
(Still some regs are not handled but this is one step in that direction)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3545a0f08d342de98efc82b78f5725eda091555a.1647267969.git.michal.simek@xilinx.com
2022-03-16 16:14:34 +01:00
Tom Rini
f5ac18f406 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: dts: turris_mox: fix non-working network / MDIO (Marek)
2022-03-16 08:12:45 -04:00
Tom Rini
469c1bc688 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- k210 updates
2022-03-16 08:11:53 -04:00
Marek Behún
351729ca44 arm: mvebu: dts: turris_mox: fix non-working network / MDIO
Commit 0934dddc64 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke network on Turris MOX, because the SOC's MDIO bus in
U-Boot currently isn't probed via DM as it's own device, but is
registered as part of mvneta's driver, which means that pinctrl
definitions are not parsed for the MDIO bus node. Also mvneta driver
does not consider "phy-handle" property, only "phy".

For now, fix this by adding armada-3720-turris-mox-u-boot.dtsi file
returning the MDIO to how it was defined previously.

A better solution (using proper mvmdio DM driver) is being work on, but
will need testing on various boards, and we need the bug fixed now for
the upcoming release.

Fixes: 0934dddc64 ("arm: a37xx: Update DTS files to version from upstream Linux kernel")
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-16 07:24:28 +01:00
Niklas Cassel
530f29cba5 k210: dts: align plic node with Linux
The Linux PLIC interrupt-controller driver actually initializes the hart
context registers in the PLIC driver exactly in the same order as
specified in the interrupts-extended device tree property. See the device
tree binding [1].

The ordering of the interrupts is therefore essential in order to
configure the PLIC correctly.

Fix the order so that we will have sane IRQ behavior when booting Linux
with the u-boot device tree.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15 17:43:11 +08:00
Damien Le Moal
a6c86ec2d6 k210: dts: align fpioa node with Linux
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the
power bit offset of the fpioa device to be specified as a single
property "canaan,k210-sysctl-power".
Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset"
properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel
requirements. This new property is parsed using the existing function
dev_read_phandle_with_args().

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15 17:43:11 +08:00
Damien Le Moal
dd241d04a6 k210: dts: add missing power bus clocks
Linux drivers for many of the K210 peripherals depend on the power bus
clock to be specified. Add the missing clocks and their names to avoid
problems when booting Linux using u-boot DT.

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15 17:43:11 +08:00
Damien Le Moal
fd426b3106 k210: use the board vendor name rather than the marketing name
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.

Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15 17:43:11 +08:00
Marek Vasut
19fbe102b2 ARM: dts: stm32: Add DFU support for DHCOM recovery
This patch configures U-Boot SPL for DHCOM SoM to permit DFU upload of
SPL and subsequent u-boot.itb for recovery or commissioning purposes.

The DFU usage procedure is identical to STM32MP1 DHCOR SoM, see commit
3919aa1722 ("ARM: dts: stm32: Add DFU support for DHCOR recovery") ,
except for switching the SoM into DFU mode. By default, the DHCOM SoM
has no dedicated mechanism for setting BOOTn straps into UART/USB mode,
therefore to enter DFU mode, the SoC must fail to boot from boot media
which can be selected by the BOOTn strap override mechanism first and
then fall back to DFU mode.

In case of a SoM with pre-populated BOOTn strap override button, power
the system off, remove microSD card (if applicable), hold down the BOOTn
strap override button located between eMMC and SoM edge connector, power
on the SoM. The SoC will fail to boot from SD card and fall back into
DFU mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:20:32 +01:00
Marek Vasut
b49105320a stm32mp: psci: Implement PSCI system suspend and DRAM SSR
Implement PSCI system suspend and placement of DRAM into SSR while the
CPUs are in suspend. This saves non-trivial amount of power in suspend,
on 2x W632GU6NB-15 ~710mW.

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:16:55 +01:00
Marek Vasut
9a8996df05 ARM: dts: stm32: Move vdd_io extras into Avenger96 extras
The vdd_io regulator is present only on DHCOR SoM configured for 1V8 IO,
as populated on Avenger96, but not present on 3V3 DHCOR SoM. Move these
extras to Avenger96 u-boot DT extras.

Fixes: 3919aa1722 ("ARM: dts: stm32: Add DFU support for DHCOR recovery")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-03-15 09:15:10 +01:00
Marek Vasut
27f6c653ae ARM: dts: stm32: Add USB OTG pinctrl and regulator nodes into SPL DT on DHCOR
Fix the following warning in SPL and make sure that even DTs which
enforce Vbus detection using u-boot,force-vbus-detection;, the DFU
in SPL will work.

dwc2-udc-otg usb-otg@49000000: prop pinctrl-0 index 0 invalid phandle

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:13:31 +01:00
Patrick Delaunay
182738fe2f arm: dts: stm32mp15: alignment with v5.17
Device tree alignment with Linux kernel v5.17-rc1
- ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins
  on STM32MP15 DKx boards
- ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx
- ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1
- ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:11:47 +01:00
Patrick Delaunay
2d48d99c4a stm32mp1: bsec: add missing dev in function comment
Add the missing @dev reference in some function description.

Fixes: b66bfdf238 ("arm: stm32mp: bsec: migrate trace to log macro")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:10:52 +01:00
Patrick Delaunay
0c20f53b3f stm32mp: bsec: add permanent lock write support
Add support of the permanent lock support in U-Boot proper
when BSEC is not managed by secure monitor (TF-A SP_MIN or OP-TEE).

This patch avoid issue with stm32key command and fuse command
on basic boot for this missing feature of U-Boot BSEC driver.

Reported-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-03-15 09:10:52 +01:00
Tom Rini
2abf048ab7 Prepare v2022.04-rc4
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Merge tag 'v2022.04-rc4' into next

Prepare v2022.04-rc4
2022-03-14 17:40:36 -04:00
Tom Rini
630a306c1a Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- kwboot: Misc minor improvement and fixes, e.g. mix of arguments (Pali)
- PCI: a37xx: Remap IO space to bus address 0x0 (Pali)
2022-03-14 11:24:20 -04:00
Michal Simek
e5d8d08981 arm64: zynqmp: Fix i2c addresses for zynqmp-p-a2197
After double checking some i2c addresses are not correct. It is visible
from i2c dump

ZynqMP> i2c bus
Bus 3:	i2c@ff020000
   74: i2c-mux@74, offset len 1, flags 0
Bus 5:	i2c@ff020000->i2c-mux@74->i2c@0
Bus 6:	i2c@ff020000->i2c-mux@74->i2c@2
Bus 7:	i2c@ff020000->i2c-mux@74->i2c@1
Bus 8:	i2c@ff020000->i2c-mux@74->i2c@3
Bus 4:	i2c@ff030000  (active 4)
   74: i2c-mux@74, offset len 1, flags 0
Bus 9:	i2c@ff030000->i2c-mux@74->i2c@0
Bus 10:	i2c@ff030000->i2c-mux@74->i2c@3
Bus 11:	i2c@ff030000->i2c-mux@74->i2c@4
Bus 12:	i2c@ff030000->i2c-mux@74->i2c@5  (active 12)
   51: generic_51, offset len 1, flags 0
   60: generic_60, offset len 1, flags 0
   74: generic_74, offset len 1, flags 0
Bus 13:	i2c@ff030000->i2c-mux@74->i2c@6  (active 13)
   51: generic_51, offset len 1, flags 0
   5d: generic_5d, offset len 1, flags 0
   74: generic_74, offset len 1, flags 0
ZynqMP> i2c dev 4
Setting bus to 4
ZynqMP> i2c mw 74 0 18
ZynqMP> i2c probe
Valid chip addresses: 18 36 37 50 51 60 74
ZynqMP> i2c mw 74 0 20
ZynqMP> i2c probe
Valid chip addresses: 51 60 74

where it is clear that si570 (u5) is at 0x60 address and 8t49n240 (u39) is
also at address 0x60 based on log above.
i2c address 0x74 is i2c mux and 0x51 is eeprom.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0a198e9d993411e41473d130d5a5c20b6dc83458.1646639616.git.michal.simek@xilinx.com
2022-03-14 15:24:04 +01:00
Pali Rohár
037bb6e2ca arm: a37xx: Remap IO space to bus address 0x0
Remap PCI I/O space to the bus address 0x0 in the Armada 37xx device-tree
in order to support legacy I/O port based cards which have hardcoded I/O
ports in low address space.

Some legacy PCI I/O based cards do not support 32-bit I/O addressing.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-14 14:04:18 +01:00
Simon Glass
978a8a296e x86: Add an enum name for the GNVS firmware type
This enum is currently anonymous. Add a name so it can be used in the
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-03-14 15:20:40 +08:00
Tom Rini
6d35c24892 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- sunXi SPI fixups (Andre)
- bcm iproc qspi (Rayagonda)
2022-03-12 07:20:29 -05:00
weichangzheng
b9d0f00a9d arm: add initial support for the Phytium Pomelo Board
This adds platform code and the device tree for the Phytium Pomelo Board.
The initial support comprises the UART and the PCIE.

Signed-off-by: weichangzheng <nicholas_zheng@outlook.com>
2022-03-10 13:57:04 -05:00
Adam Ford
901ff692d1 ARM: mach-omap2: omap3: Make clock functions static
get_osc_clk_speed and get_sys_clkin_sel are only used in
one file.  Make them static.

Tested on OMAP3530, DM3730, AM3517.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-03-10 13:57:04 -05:00
Adam Ford
72ce7818f9 ARM: dts: am3517-evm: Sync DTS with Linux 5.17-rc5
Sync the am3517-evm device tree files with those from Linux
5.17-rc5 with some additional fixes for pinmuxing Ethernet and
moving the pinmux references to the respective peripherals.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2022-03-10 13:57:04 -05:00
Adam Ford
08ff17d3b9 ARM: dts: logicpd-torpedo: Resyc DTS files with Linux 5.17-rc5
Resyc DTS files with Linux 5.17-rc5.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-03-10 13:57:04 -05:00
Adam Ford
d0331d46c8 ARM: dts: logicpd-som-lv: Resync DTS files with Linux 5.17-rc5
Resync the DTS files for the Logic PD SOM-LV with Linux 5.17-rc5
with some additional pending changes to address issues with
wrong pin-muxing on the OMAP35.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-03-10 13:57:04 -05:00
Simon Glass
7fe32b3442 event: Convert arch_cpu_init_dm() to use events
Instead of a special function, send an event after driver model is inited
and adjust the boards which use this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Simon Glass
42fdcebf85 event: Convert misc_init_f() to use events
This hook can be implmented using events, for the three boards that
actually use it.

Add the event type and event handlers. Drop CONFIG_MISC_INIT_F since we
can just use CONFIG_EVENT to control this. Since sandbox always enables
CONFIG_EVENT, we can drop the defconfig lines there too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Simon Glass
d41b703f45 sandbox: start: Sort the header files
These header files don't follow the correct order. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-10 08:28:36 -05:00
Andre Przywara
81a46c152a sunxi: Kconfig: Fix up SPI configuration
Commit 7945caf22c ("arm: sunxi: Enable SPI/SPI-FLASH support for A64")
selected CONFIG_SPI by default on all Allwinner A64 boards, even though
only 4 out of the 14 A64 boards have a SPI flash chip. All other SoCs
had to manually select DM_SPI and friends, even though they are a
platform property (the sunxi SPI driver is DM_SPI only).

Clean this up to allow easy selection of SPI flash support in U-Boot
proper, by selecting DM_SPI and DM_SPI_FLASH *if* CONFIG_SPI is
selected, for *all* Allwinner SoCs. This simplifies the defconfig for
two Libretech boards already.

Also remove the forced CONFIG_SPI from the A64 Kconfig, instead let the
four boards which allow SPI booting select this explicitly.

Any board wishing to support SPI flash in U-Boot proper now just defines
CONFIG_SPI and CONFIG_SPI_FLASH_<vendor> in its defconfig, Kconfig takes
care of the rest.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-03-10 17:32:13 +05:30
Neal Frager
9fb9ec5e24 arm64: zynqmp: add support for zcu106 rev1.0
This patch adds psu_init for Xilinx ZCU106 rev1.0. Xilinx ZCU106 rev1.0 has
newer x16 DDR4 memories and it is SW compatible with revA.

Signed-off-by: Neal Frager <neal.frager@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/997b3e23457e4d24ce0e197d742382aaec36c2b2.1646230318.git.michal.simek@xilinx.com
2022-03-09 12:39:33 +01:00
Andrew Jeffery
7da8754971 ARM: dts: ast2500: Add ngpios property to GPIO node
Populate gpio_count in the gpio subsystem for the AST2500.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2022-03-07 11:36:12 -05:00
Lukasz Majewski
4a9099ef1c arm: dts: Add DTS description for MMC2 am33xx devices
This code has been ported from Linux v5.16.9 arch/arm/boot/dts/am33xx.dtsi
file to allow correct usage of MMC2 controller in U-Boot.

This IP block is a bit specific as it is connected to L3 interconnect bus,
whereas mmc[01] are connected to L4.

Proper configuration of this block (including providing clock) is handled
in ti-sysc.c driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-03-07 11:36:12 -05:00
Lukasz Majewski
ab9e48f096 arm: dts: Add mmc[01] aliases to am33xx.dtsi
This change provides similar aliases definitions as now present in
Linux kernel v5.16.9 for am33xx.dtsi file.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-03-07 11:36:12 -05:00
Philippe Reynes
3bf5e4343c arch: arm: dts: bcm96753ref: enable led support
Enable the led in the device tree of the refboard bcm96753ref.
It also defines two leds (led_red ad led_green).

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-03-07 11:36:12 -05:00
Philippe Reynes
66425ca694 arch: arm: dts: bcm6753: add led support
Add a node leds to support the LED IP in the
device tree of the bcm6753.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-03-07 11:36:12 -05:00
Philippe Reynes
a241ccdc44 bcm96753ref: add initial support
This add the initial support of the broadcom reference
board bcm96753ref with a bcm6753 SoC.

This board has 1 GB of RAM, 256 MB of flash (nand),
2 USB port, 1 UART, and 4 ethernet ports.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-03-07 11:36:12 -05:00
Philippe Reynes
1d5555fae4 bcm6753: add initial support
This add the initial support of the broadcom bcm6753 SoC family.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-03-07 11:36:12 -05:00
Michal Simek
2f6e1dde38 arm64: zynqmp: Fix level of gpio reset for usb on kv260 boards
Active level is low that's why it should be fixed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/86b3a96ce990b0ee0adab221146b5a5c751bd4a9.1645629459.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michal Simek
8b82a3a7fe arm64: zynqmp: Enable DP driver for SOMs
The main reason is to send pmufw cfg overlay from U-Boot to PMUFW to enable
access to DP. Overlay is sent when cls command is called and for that IP
has to be enabled in carrier cards.
And IP needs to be also enabled in SOM dt because with DTB reselection new
DT is not parsed in pre reloc U-Boot instance. It is called from board_f
via embedded_dtb_select(). That's why bind function is not able to allocate
memory and it ends up with error:
"Video device 'display@fd4a0000' cannot allocate frame buffer memory
-ensure the device is set up before relocation"

To avoid this situation DP is placed also to SOM where bind function is
called and frame buffer memory is allocated and just reused after DTB
reselection. Result is the same. There could be a problem in Linux with
different DP configurations but that's need to be solved there because
console should be on from u-boot already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/c4f31641f917fddb09d976f56875057c658f264c.1645629459.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michal Simek
ff79448294 arm64: zynqmp: Switch to ethernet-phy-id in kv260
Use ethernet-phy-id compatible string to properly describe phy reset on
kv260 boards. Previous description wasn't correct because reset was done
for mdio bus to operate and it was in this case used for different purpose
which was eth phy reset. With ethernet-phy-id phy reset happens only for
the phy via phy framework.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/73b64f1a2b873b4e26bd2b365364bdf313794ae2.1645629459.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michal Simek
a3efa53c01 arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM
With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for USBs
and SDs.
Also setup proper bus width for SD cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/d9f80b2551bd246c3d7ecb09b516806c8dc83ed9.1645629459.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michal Simek
59e1bdd48d arm64: zynqmp: Setup clock for DP and DPDMA
Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/04454c50d0d13e450976942085d763ab5aa38f98.1645629459.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michal Simek
c36dc2449b arm64: zynqmp: Move usb hub from i2c to usb node
Based on upstream discussion based on link below usb hub should be placed
to usb node directly as child node. Based on this Linux driver was updated
and the same change should be also reflected in kv260 board.

Link: https://lore.kernel.org/all/CAL_JsqJZBbu+UXqUNdZwg-uv0PAsNg55026PTwhKr5wQtxCjVQ@mail.gmail.com/
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/aa18df1978f161b933e6cdc6cd99c807b5f74398.1645629459.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michal Simek
d7b5cc89d3 microblaze: Do not place u-boot to reserved memory location
Microblaze can also have reserved space in DT which u-boot has to avoid to
placing self to that location. The same change was done in Zynqmp by commit
ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory location").

This feature was tested with this memory description on kc705:

	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		alloc@b00000000 {
			reg = <0xb0000000 0x10000000>;
			no-map;
		};

		alloc@a8000000 {
			reg = <0xa8000000 0x00010000>;
			no-map;
		};
	};

And in U-Boot log you can check u-boot relocation address and reserved
locations.
U-Boot 2022.01-03974-gb1b4c2dea9b9 (Feb 25 2022 - 11:59:48 +0100)

Model: Xilinx MicroBlaze
DRAM:  1 GiB
Flash: 128 MiB
Loading Environment from nowhere... OK
In:    serial
Out:   serial
Err:   serial
Model: Xilinx MicroBlaze
Net:   AXI EMAC: 40c00000, phyaddr 7, interface gmii
eth0: ethernet@40c00000
U-BOOT for microblaze-generic

U-Boot-mONStR> bdi
...
DRAM bank   = 0x00000000
-> start    = 0x80000000
-> size     = 0x40000000
...
relocaddr   = 0xaff69000
...
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]	[0x80000000-0xbfffffff], 0x40000000 bytes flags: 0
 reserved.cnt  = 0x3
 reserved[0]	[0xa8000000-0xa800ffff], 0x00010000 bytes flags: 4
 reserved[1]	[0xafe87bb0-0xafffffff], 0x00178450 bytes flags: 0
 reserved[2]	[0xb0000000-0xbfffffff], 0x10000000 bytes flags: 4

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/ea0a8ccce723478eb518f6fdceb91d4f129efb68.1646122398.git.michal.simek@xilinx.com
2022-03-07 16:33:47 +01:00
Michael Walle
03a8e826e0 ARM: dts: zynq: add NAND flash controller node
Recently, a driver for the ARM Primecell PL35x static memory controller
(including NAND controller) was added in linux. Add the corresponding
device tree node.

Also update cfi-flash registers and location in DT.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210616155437.27378-3-michael@walle.cc
Link: https://lore.kernel.org/r/ee81d3846a1ce93f240d61537d404796e5599c1c.1645625433.git.michal.simek@xilinx.com
2022-03-07 08:52:20 +01:00
Tom Rini
6d3c46ed0e Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Fix ARMv5/F1C100 FEL booting
- Fix F1C100 reset
- Introduce proper F1C100 boot method detection
- Enable SPI booting for F1C100

Boot tested from FEL, SPI, SD card and eMMC (where applicable) on
Pine64-LTS, Pine-H64, BananaPi M1, OrangePi Zero, LicheePi Nano(F1C100).
2022-03-05 20:46:55 -05:00
Jan Kiszka
39834ccdd4 arm: dts: iot2050: Add cfg register space for ringacc and udmap
Recent unrelated fixes (9876ae7db6) revealed that we were missing bits
from 2af181b53e in the IOT2050 dt. Add them, but only for main U-Boot.
SPL loads from QSPI only, thus cannot use DMA.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2022-03-04 15:20:06 -05:00
Christian Gmeiner
f7fbe547d9 arm: mach-k3: am6_init: Use CONFIG_TI_I2C_BOARD_DETECT
We only want to call do_board_detect() if CONFIG_TI_I2C_BOARD_DETECT
is set. Same as done for am64.

This makes it possible to add a custom am65 based board design to
U-Boot that does not use this board detection mechanism.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-03-04 15:20:06 -05:00
Pali Rohár
1fd54253bc arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function again
The a3700_fdt_fix_pcie_regions() function still computes nonsense.

It computes the fixup offset from the PCI address taken from the first
row of the "ranges" array, which means that:
- PCI address must equal CPU address (otherwise the computed fix offset
  will be wrong),
- the first row must contain the lowest address.

This is the case for the default device-tree, which is why we didn't
notice it.

It also adds the fixup offset to all PCI and CPU addresses, which is
wrong.

Instead:
1) The fixup offset must be computed from the CPU address, not PCI
   address.

2) The fixup offset must be computed from the row containing the lowest
   CPU address, which is not necessarily contained in the first row.

3) The PCI address - the address to which the PCIe controller remaps the
   address space as seen from the point of view of the PCIe device -
   must be fixed by the fix offset in the same way as the CPU address
   only in the special case when the CPU adn PCI addresses are the same.
   Same addresses means that remapping is disabled, and thus if we
   change the CPU address, we need also to change the PCI address so
   that the remapping is still disabled afterwards.

Consider an example:
  The ranges entries contain:
    PCI address   CPU address
    70000000      EA000000
    E9000000      E9000000
    EB000000      EB000000

  By default CPU PCIe window is at:        E8000000 - F0000000
  Consider the case when TF-A moves it to: F2000000 - FA000000

  Until now the function would take the PCI address of the first entry:
  70000000, and the new base, F2000000, to compute the fix offset:
  F2000000 - 70000000 = 82000000, and then add 8200000 to all addresses,
  resulting in
    PCI address   CPU address
    F2000000      6C000000
    6B000000      6B000000
    6D000000      6D000000
  which is complete nonsense - none of the CPU addresses is in the
  requested window.

  Now it will take the lowest CPU address, which is in second row,
  E9000000, and compute the fix offset F2000000 - E9000000 = 09000000,
  and then add it to all CPU addresses and those PCI addresses which
  equal to their corresponding CPU addresses, resulting in
    PCI address   CPU address
    70000000      F3000000
    F2000000      F2000000
    F4000000      F4000000
  where all of the CPU addresses are in the needed window.

Fixes: 4a82fca8e3 ("arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-03-04 08:38:05 +01:00
Tom Rini
f9147d636c Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig
This converts the following to Kconfig:
   CONFIG_CHIP_SELECTS_PER_CTRL

Cc: Alison Wang <alison.wang@nxp.com>
Cc: Pramod Kumar <pramod.kumar_1@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:20 -05:00
Tom Rini
6d21dd313b Convert CONFIG_BOARD_POSTCLK_INIT to Kconfig
This converts the following to Kconfig:
   CONFIG_BOARD_POSTCLK_INIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:19 -05:00
Tom Rini
da8592d5fa Convert CONFIG_BOARD_ECC_SUPPORT to Kconfig
This converts the following to Kconfig:
   CONFIG_BOARD_ECC_SUPPORT

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:19 -05:00
Tom Rini
a7e6c6b1be Convert CONFIG_BOARD_COMMON to Kconfig
This converts the following to Kconfig:
   CONFIG_BOARD_COMMON

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:19 -05:00
Tom Rini
43ea564652 arm: exynos: Move BL1/2 SPI flash defines to their user, drop CONFIG
These particular values are not configurable and today we always set
CONFIG_SECURE_BL1_ONLY.  Move these to where they're used in the code,
and drop from the CONFIG namespace.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2022-03-03 16:51:19 -05:00
Tom Rini
a3041d934f Convert CONFIG_BTB to Kconfig
This converts the following to Kconfig:
   CONFIG_BTB

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:19 -05:00
Tom Rini
3db7b2bb4c powerpc: Remove unused MPC8540/60ADS code
Remove some code, primarily CPM2 related, that is now unused since the
removal of MPC8540/60ADS.

Fixes 3913191c8a ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-03 16:51:19 -05:00
Tom Rini
d274f92246 First set of u-boot-atmel fixes for the 2022.04 cycle
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Merge tag 'u-boot-at91-fixes-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91

First set of u-boot-atmel fixes for the 2022.04 cycle:

This fixes set includes only a single fix for the Ethernet on sama7g5ek
board which is broken at the moment.
2022-03-03 08:24:37 -05:00
Tom Rini
705b5840cd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Update and fixes for sl28, lx2, pblimage generation for some powerpc
products
2022-03-03 08:24:13 -05:00
Andre Przywara
c21f3d4571 sunxi: f1c100s: Fix FEL registers restore
Commit 88998f7775 ("arm: arm926ej-s: Add sunxi code") introduced
the ARM926 version of the code to save and restore some FEL state, to
be able to return to the BROM FEL code after the SPL has run.

However during review a change was made, that happened to mess up the
register restore part, so SCTLR and CPSR ended up with the wrong values,
breaking return to FEL.

Use the same offset that we actually save those registers to, to make
FEL booting actually work on the Lichee Pi Nano.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03 01:24:06 +00:00
Jesse Taube
640f2f3bf1 mach-sunxi: Enable SPI boot for SUNIV and licheepi nano
Enable SPI boot in SPL on SUNIV architecture and use
it in the licheepi nano that uses the F1C100s.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03 01:24:06 +00:00
Jesse Taube
0dcdaff8b8 mach-sunxi: Add SPL SPI boot for SUNIV
The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: adaptation to Upstream U-Boot]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03 01:24:06 +00:00
Jesse Taube
a08b04b5c7 mach-sunxi: Add boot device detection for SUNIV/F1C100s
In contrast to other Allwinner SoCs the F1C100s BROM does not store a
boot source indicator in the eGON header in SRAM. This leaves the SPL
guessing where we were exactly booted from, and for instance trying
the SD card first, even though we booted from SPI flash.

By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.

This patch removes the existing board_boot_order bodge and replace it
with a proper boot source indication function.

The only caveat is that this only works in the SPL, as the SPL header
gets overwritten with the exception vectors, once U-Boot proper takes
over. Always return MMC0 as the boot source, when called from U-Boot
proper, as a placeholder for now, until we find another way.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Suggested-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03 01:23:58 +00:00
Etienne Carriere
10d3e5d20b firmware: scmi: fix sandbox and related tests for clock discovery
Updates sandbox SCMI clock driver and tests since enabling CCF will
mandate clock discovery that is all exposed SCMI clocks shall be
discovered at initialization. For this reason, sandbox SCMI clock
driver must emulate all clocks exposed by SCMI server, not only those
effectively consumed by some other U-Boot devices.

Therefore the sandbox SCMI test driver exposes 3 clocks (IDs 0, 1 and 2)
and sandbox SCMI clock consumer driver gets 2 of them.

Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-03-02 17:42:06 -05:00
Etienne Carriere
41d62e2f27 sandbox: scmi: test against a single scmi agent
As per DT bindings since Linux kernel v5.14, the device tree can define
only 1 SCMI agent node that is named scmi [1]. As a consequence, change
implementation of the SCMI driver test through sandbox architecture to
reflect that.

This change updates sandbox test DT and sandbox SCMI driver accordingly
since all these are impacted.

Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-03-02 17:42:06 -05:00
Andre Przywara
5ff4857d35 armv8: Fix and simplify branch_if_master/branch_if_slave
The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.

The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.

Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.

Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02 13:59:29 -05:00
Andre Przywara
f660fe0bd3 armv8: Simplify switch_el macro
The switch_el macro is a neat contraption to handle cases where we need
different code depending on the current exception level, but its
implementation was longer than needed.

Simplify it by doing just one comparison, then using the different
condition codes to branch to the desired target. PState.CurrentEL just
holds two bits, and since we don't care about EL0, we can use >, =, < to
select EL3, EL2 and EL1, respectively.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02 13:59:29 -05:00
Andre Przywara
7ab2e47d27 arm: Clean up asm/io.h
asm/io.h is the header file containing the central MMIO accessor macros.
Judging by the header and the comments, it was apparently once copied
from the Linux kernel, but has deviated since then *heavily*. There is
absolutely no point in staying close to the original Linux code anymore,
so just remove the old cruft, by:
- removing pointless Linux history
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa)

This massively improves the readability of the file.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02 13:59:29 -05:00
Andre Przywara
7ed340a828 armv8: Force SP_ELx stack pointer usage
In ARMv8 we have the choice between two stack pointers to use: SP_EL0 or
SP_ELx, which is banked per exception level. This choice is stored in
the SP field of PState, and can be read and set via the SPSel special
register. When the CPU takes an exception, it automatically switches to
the SP_ELx stack pointer.

Trusted Firmware enters U-Boot typically with SPSel set to 1, so we use
SP_ELx all along as our sole stack pointer, both for normal operation and
for exceptions.

But if we now for some reason enter U-Boot with SPSel cleared, we will
setup and use SP_EL0, which is fine, but leaves SP_ELx uninitialised.
When we now take an exception, we try to save the GPRs to some undefined
location, which will usually end badly.

To make sure we always have SP_ELx pointing to some memory, set SPSel
to 1 in the early boot code, to ensure safe operation at all times.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02 13:59:29 -05:00
Andre Przywara
6c7691edd5 armv8: Always unmask SErrors
The ARMv8 architecture describes the "SError interrupt" as the fourth
kind of exception, next to synchronous exceptions, IRQs, and FIQs.
Those SErrors signal exceptional conditions from which the system might
not easily recover, and are normally generated by the interconnect as a
response to some bus error. A typical situation is access to a
non-existing memory address or device, but it might be deliberately
triggered by a device as well.
The SError interrupt replaces the Armv7 asynchronous abort.

Trusted Firmware enters U-Boot (BL33) typically with SErrors masked,
and we never enable them. However any SError condition still triggers
the SError interrupt, and this condition stays pending, it just won't be
handled. If now later on the Linux kernel unmasks the "A" bit in PState,
it will immediately take the exception, leading to a kernel crash.
This leaves many people scratching their head about the reason for
this, and leads to long debug sessions, possibly looking at the wrong
places (the kernel, but not U-Boot).

To avoid the situation, just unmask SErrors early in the ARMv8 boot
process, so that the U-Boot exception handlers reports them in a timely
manner. As SErrors are typically asynchronous, the register dump does
not need to point at the actual culprit, but it should happen very
shortly after the condition.

For those exceptions to be taken, we also need to route them to EL2,
if U-Boot is running in this exception level.

This removes the respective code snippet from the Freescale lowlevel
routine, as this is now handled in generic ARMv8 code.

Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02 13:59:29 -05:00
Janne Grunau
6fb4f7387e arm: apple: Switch to fully dynamic mem layout
Support for Apple M1 Pro and Max will allow using a single binary for
all M1 SoCs. The M1 Pro/Max have a different memory layout. The RAM
start address is 0x100_0000_0000 instead of 0x8_0000_0000.
Replace the hardcoded memory layout with dynamic initialized
environment variables in board_late_init().

Tested on Mac Mini (2020) and Macbook Pro 14-inch (2021).

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2022-02-28 10:33:45 -05:00
Michael Walle
554a85313b board: sl28: use fit image generator
Simplify the binman config and fdt nodes by using the "@..-SEQ"
substitutions and CONFIG_OF_LIST.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-28 12:01:02 +05:30
Tom Rini
90de95f744 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- OMAP EHCI updates
2022-02-23 13:34:14 -05:00
Adam Ford
0935dbf4c9 usb: ehci-omap: Drop dead code
omap_ehci_hcd_stop appears to be dead code, and omap_ehci_hcd_init
is only called by the probe function, so it can be static to that
function.  Remove both from the header along with some additional
checking for DM_USB.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-23 05:25:17 +01:00
Simon Glass
00959d871c spl: x86: Correct the binman symbols for SPL
These symbols are incorrect, meaning that binman cannot find the
associated entry. This leads to errors like:

binman: Section '/binman/simple-bin': Symbol '_binman_spl_prop_size'
   in entry '/binman/simple-bin/u-boot-spl/u-boot-spl-nodtb':
   Entry 'spl' not found in list (mkimage,u-boot-spl-nodtb,
   u-boot-spl-bss-pad,u-boot-spl-dtb,u-boot-spl,u-boot-img,main-section)

Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-22 10:05:44 -07:00
Tom Rini
17a0dc6abf Merge branch '2022-02-21-platform-updates'
- Assorted updates / fixes for Apple, TI and Aspeed platforms
2022-02-21 08:53:24 -05:00
Suman Anna
5d90836cb5 arm: dts: k3-j7200: Fix up MAIN R5FSS cluster mode back to Split-mode
The default U-Boot environment variables and design are all set up for
the MAIN R5FSS cluster to be in Split-mode. This is the setting used
when the dts nodes were originally added in v2021.01 U-Boot and the
dt nodes are synched with the kernel binding property names in
commit 468ec2f3ef ("remoteproc: k3_r5: Sync to upstreamed kernel DT
property names") merged in v2021.04-rc2.

The modes for the MAIN R5FSS cluster got switched back to LockStep mode
by mistake in commit fa09b12dc5 ("arm: ti: k3: Resync dts files and
bindings with Linux Kernel v5.14") in v2022.01-rc1. This throws the
following warning messages when early-booting the cores using default
env variables,

k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode
Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Failed!

Fix this by switching back both the clusters to the expected Split-mode.
Make this mode change in the u-boot specific dtsi file to avoid such
sync overrides in the future until the kernel dts is also switched to
Split-mode by default.

Fixes: fa09b12dc5 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14")
Signed-off-by: Suman Anna <s-anna@ti.com>
2022-02-21 08:35:40 -05:00
Adam Ford
68a51cc8ec arm: omap3: Make some memory functions static and clean headers
There are a few memory functions for both the emif4 (AM3517)
and sdrc (OMAP35/DM37) code that can be defined as static,
because those functions are not used externally. Make them
static and clean up some of the corresponding headers.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-21 08:35:40 -05:00
Adam Ford
1c6ea4da24 arm: omap3: Cleanup sys_info to fit OMAP3 booting with LTO
With LTO enabled, some functions appear to be optimized in a
way that causes hanging on some OMAP3 boards after some
unrelated patches were applied.  The solution appears to make
several functions __used.  There also appears be to be some
dead code, so remove it while cleaning this up.

This has been tested on a general purpose OMAP3530, DM3730,
and AM3517.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-21 08:35:40 -05:00
Keerthy
da6a8d9c28 arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max voltages of VDD_CPU
Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU
minimum voltage is .6V & maximum voltage is .9V.

Correct the same. While at it fix the comment to reflect VDD_CPU
instead of VDD_MPU.

Data Sheet Link: https://www.ti.com/lit/gpn/dra829v

Signed-off-by: Keerthy <j-keerthy@ti.com>
2022-02-21 08:35:40 -05:00
Mark Kettenis
a89fea7fd1 arm: apple: Add M1 Pro/Max support
Choose the memory map based on the compatible property from the
device tree passed to us by m1n1. Since DRAM on the M1 Pro/Max
starts at a different address avoid hardcoding the top of usable
memory. Also make sure that the addresses entered into the memory
map are page aligned such that we don't crash in dcache_enable().

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Tested on: Macbook M1 Max
Tested-by: Janne Grunau <j@jannau.net>
2022-02-21 08:35:12 -05:00
Tom Rini
24b628a8f8 Xilinx changes for v2022.04-rc3
microblaze:
 - Fix exception handler
 
 zynqmp:
 - Show information about secure images
 - DT changes (som u-boot file removal)
 - Fix zynqmp_pm_cfg_obj_convert.py
 - Fix platform boot
 
 xilinx:
 - Fix bootm_size calculation
 - Remove GPIO_EXTRA_HEADER selection
 
 power:
 - Add zynqmp power management driver
 
 scsi:
 - Add phy support to ceva driver
 
 zynq qspi:
 - Fix unaligned accesses and check baudrate setup
 - Add support for spi memory operations
 
 net:
 - Fix 64bit calculation in axi_emac
 
 video:
 - Add missing gpio dependency for seps driver
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Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
2022-02-21 08:32:02 -05:00
Michal Simek
9bd4232f95 arm64: zynqmp: Remove additional gpio header from dlc21
This header shouldn't be in this file and there is already pointer to
dt-bindings/gpio/gpio.h.

Fixes: d2d14383ba ("arm64: zynqmp: Add support for DLC21 (Smartlynq+) board")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/266bc91073f1149f3f60b1c9c0ba509c48470e2e.1644911870.git.michal.simek@xilinx.com
2022-02-21 13:21:22 +01:00
Michal Simek
11381fba99 arm64: zynqmp: Fix debug uart initialization
The commit 0dba45864b ("arm: Init the debug UART") calls
debug_uart_init() from crt0.S but it won't work because SOC is not
configured yet. That's why create board_debug_uart_init() which calls
psu_init() via new psu_uboot_init() earlier before the first access to UART
in SPL. In full U-Boot call psu_uboot_init() only when
CONFIG_ZYNQMP_PSU_INIT_ENABLED is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/878dc2daaa8685346f889989fbfb98b2e44da7fb.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:29 +01:00
Michal Simek
05f0f269b7 ARM: zynq: Fix debug uart initialization
The commit 0dba45864b ("arm: Init the debug UART") calls
debug_uart_init() from crt0.S but it won't work because SOC is not
configured yet. That's why create board_debug_uart_init() which calls
ps7_init() earlier before the first access to UART.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/18e67e02a0c7190839a1ef3a11f3fd6babcf34cc.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:24 +01:00
Michal Simek
83d2941fe9 arm64: zynqmp: Fix dependencies around ZYNQMP_PSU_INIT_ENABLED
ZYNQMP_PSU_INIT_ENABLED is called only when BOARD_EARLY_INIT_F is defined
that's why cover this dependency in Kconfig.
 board_early_init_f() is only part related to
CONFIG_ZYNQMP_PSU_INIT_ENABLED which is disabled now that's why disable
BOARD_EARLY_INIT_F and also build board_early_init_f() only when
CONFIG_BOARD_EARLY_INIT_F is enabled.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d89253ec1590cd513dcd4bfbedebae618bd6d605.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:19 +01:00
Michal Simek
27703ba06d arm64: zynqmp: Build psu_spl_init for SPL all the time
ZYNQMP_PSU_INIT_ENABLED specifically saying that has connection to full
U-Boot not SPL that's why build psu_spl_init for SPL all the time.

Also disable ZYNQMP_PSU_INIT_ENABLED because it ends up in situation that
psu_init() is called twice which is wrong. By default only SPL should call
it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/bf1e5d9a163f8853c7d951ad42965114ab0b1f50.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:06 +01:00
Marek Vasut
fea6607317 ARM: imx: imx8mn-ddr4-evk: Add ethernet support
Add support for ethernet on the imx8mn-ddr4-evk.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-19 23:32:23 +01:00
Michael Trimarchi
9da828c207 imx8m: Drop unused function env_get_offset
This function is used in nxp u-boot tree.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-19 14:46:54 +01:00
Tim Harvey
2cb156e126 board: gateworks: venice: add imx8mn-gw7902 support
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
 - LPDDR4 DRAM
 - eMMC FLASH
 - Gateworks System Controller
 - LTE CAT M1 modem
 - USB 2.0 HUB
 - M.2 Socket with USB2.0, PCIe, and dual-SIM
 - IMX8M FEC
 - PCIe based GbE
 - RS232/RS485/RS422 serial transceiver
 - GPS
 - CAN bus
 - WiFi / Bluetooth
 - MIPI header (DSI/CSI/GPIO/PWM/I2S)
 - PMIC

To add support for the i.MX8M Nano GW7902:
 - Add imx8mn-venice dts/defconfig/include
 - Add imx8mn-gw7902 dts
 - Add imx8mn-2gb lpddr4 dram configs
 - Add misc support for IMX8M Nano SoC
 - rename imx8mm-venice.c to venice.c as it is no longer imx8mm specific
 - update README with differences for IMX8MN vs IMX8MM

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-19 14:46:54 +01:00
Ying-Chun Liu (PaulLiu)
ddb56f371a arm: imx8m: add support for Advantech RSB-3720
Add initial support for Advantech RSB-3720 board.
The initial support includes:
 - MMC
 - eMMC
 - I2C
 - FEC
 - Serial console

Signed-off-by: Darren Huang <darren.huang@advantech.com.tw>
Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw>
Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw>
Signed-off-by: Tim Liang <tim.liang@advantech.com.tw>
Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>
2022-02-19 14:46:54 +01:00
Patrick Wildt
e72cb770d4 arm: dts: imx8mq: add MNT Reform 2
Device tree taken from Linux v5.16-rc5.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-18 18:12:23 +01:00
Harald Seiler
f62611a9ed imx: spl: Fix typo BMODE_EMI -> BMODE_EIM
The interface for NOR/OneNAND is called "EIM" not "EMI".  Fix this.

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-18 18:12:23 +01:00
Tom Rini
8ad1c9c26f Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- a37xx: pci: Cleanup and minor fix for root port check (Pali)
- pci: mvebu: Ensure that root port is always on root zero bus (Pali)
- kwbimage: Fix dumping DATA registers for v0 images (Pali)
- kwbimage: Support for parsing extended v0 format (Pali)
- a37xx: Fix code and update DTS files to upstream version (Pali)
- a37xx: Fix and extend building memory map (Pali)
- ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision (Marek)
- mvebu: Optionally reset board on DDR training failure (Marek)
2022-02-17 11:03:50 -05:00
Marek Behún
871ee6634d arm: mvebu: spl: Add option to reset the board on DDR training failure
Some boards may occacionally fail DDR training. Currently we hang() in
this case. Add an option that makes the board do an immediate reset in
such a case, so that a new training is tried as soon as possible,
instead of hanging and possibly waiting for watchdog to reset the board.

(If the DDR training fails while booting the image via UART, we will
 still hang - it doesn't make sense to reset in such a case, because
 after reset the board will try booting from another medium, and the
 UART booting utility does not expect that.)

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
18ab060288 arm: mvebu: a37xx: Fix comment with name of the function
Function is named build_mem_map, not a3700_build_mem_map.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-02-17 14:17:07 +01:00
Pali Rohár
65375d026a arm: mvebu: a37xx: Map CCI-400 and AP BootROM address space
In function build_mem_map() prepare also mapping for CCI-400 and
BootROM windows.

BootROM window is 1 MB long and by default starts at address 0xfff00000.
A53 AP BootROM is 16 kB long and repeats in this BootROM window 64 times.
RVBAR_EL3 register is set to value 0xffff0000, so by default A53 AP BootROM
is accessed via range 0xffff0000-0xffff3fff.

CCI-400 window when new TF-A version is used, starts at address 0xfe000000
and when old TF-A version is used, starts at address 0xd8000000.

Physical addresses are read directly from mvebu registers, so if TF-A
remaps it in future (again) then it would not cause any issue for U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
2fb7426cf0 arm: mvebu: a37xx: Fix calling build_mem_map()
Function build_mem_map() modifies global variable mem_map. This variable is
used by the get_page_table_size() function which is called by function
arm_reserve_mmu() (as aliased macro PGTABLE_SIZE). Function
arm_reserve_mmu() is called earlier than enable_caches() which calls
build_mem_map(). So arm_reserve_mmu() does not calculate reserved memory
correctly.

Fix this issue by calling build_mem_map() from a3700_dram_init() which is
called before arm_reserve_mmu().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-02-17 14:17:07 +01:00
Pali Rohár
0934dddc64 arm: a37xx: Update DTS files to version from upstream Linux kernel
This change updates all Armada 37xx DTS files to version which is used by
Linux kernel v5.18.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
6560bf4ede arm: a37xx: espressobin: Explicitly enable eMMC node in -u-boot.dtsi
Official DT bindings for Espressobin have disabled eMMC node.

As U-Boot requires to have this node enabled by default, do it in
armada-3720-espressobin-u-boot.dtsi DTS file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
a134aaa54e arm: a37xx: espressobin: Move U-Boot specific partitions node to -u-boot.dtsi
U-Boot specific changes should be in armada-3720-espressobin-u-boot.dtsi DTS file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
9dde7a09fc arm: a37xx: Update sdhci pointers to official DT bindings
In Linux kernel version of armada-37xx.dtsi file sdhci1 pointer refers to
sdhci@d0000 node and sdhci0 pointer to sdhci@d8000 node.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
0c4625ac7d watchdog: armada_37xx: Convert to official DT bindings
Official DT bindings have only one reg property: watchdog address space.
Convert armada-37xx-wdt.c driver to offical DT bindings and access sel_reg
register via MVEBU_REGISTER() macro, as its value (required by U-Boot
driver) is not in DT yet. In later stage can be driver cleaned to not use
it.

This change would allow U-Boot to use A3720 watchdog DTS structure from
Linux kernel.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
af6d0938f3 usb: ehci: ehci-marvell: Update compatible string to official DT bindings
Official DT bindings use compatible string marvell,armada-3700-ehci.
Update drivers and DTS files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Pali Rohár
9bc68546bb phy: marvell: a3700: Update compatible string to official DT bindings
In commit d368e10705 ("phy: marvell: a3700: Convert to official DT
bindings in COMPHY driver") was done update to official DT bindings but
compatible string of official DT bindings was not updated.

Fix it now.

Fixes: d368e10705 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Sinthu Raja
bc2972bd9a arm: dts: k3-j721e-r5-sk: Update R5 DT to pick the new DDR config
A new lpddr4 configuration is introduced for J7 SK with 4266 MTs data
rate. Therefore, update the R5 DTS file to point to the new DDR config
file.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
51f660120f arm: dts: k3-j721e-sk: EMIF tool update to 0.6.1 with 4266MTs for lpddr4
EMIF tool for J721E SK is now updated to 0.6.1 that includes
* Updated write DQ training pattern to enable user pattern and clock
  pattern (from 0x7 to 0x6).
* Updated IO drive strength to 40-80-80 Ohms.

J721E SK uses the lpddr4 configuration of 4266 MTs data rate which is
the same as J721E EVM but facing random failures. As the tool update is
specific to the SK board, add a new lpddr4 config of 4266 MTs.

Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
daad7d6d85 arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-sk
Add R5 specific dts for J721E-SK

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
58d61fb5a7 arm: dts: k3-j721e-sk: Add initial A72 specific dts support
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed
for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
performance vision accelerators, video codec accelerators, latest C71x
and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
dedicated safety island and security accelerators. The SoC is power
optimized to provide best in class performance for industrial and
automotive applications.

    J721E SK supports the following interfaces:
    * 4 GB LPDDR4 RAM
    * x1 Gigabit Ethernet interface
    * x1 USB 3.0 Type-C port
    * x3 USB 3.0 Type-A ports
    * x1 PCIe M.2 E Key
    * x1 PCIe M.2 M Key
    * 512 Mbit OSPI flash
    * x2 CSI2 Camera interface (RPi and TI Camera connector)
    * 40-pin Raspberry Pi GPIO header

Add A72 specific dts for J721E-SK.

[1] https://www.ti.com/tool/SK-TDA4VM

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
1157f36724 arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C
Board ID I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for wakup_i2c0 on which
board ID EEPROM is connected.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Sinthu Raja
1e82a80d17 arm: j721e: Add support for selecting DT based on board name
Enable support for selecting DTB from FIT within SPL based on the
board name read from EEPROM. This will help to use single defconfig
for both EVM and SK.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Ovidiu Panait
d1114b8340 microblaze: exception: fix unaligned data access register mask
The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
339f489d52 microblaze: exception: move unaligned access printfs inside switch case
The unaligned access messages are only valid in the case of an unaligned
data access exception. Do not print them for other types of hw exceptions.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-5-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
ee8161f7d1 microblaze: exception: fix return address for delay slot exceptions
According to the MicroBlaze reference manual (xilinx2021.2/ug984/page-37):
"""
If an exception is caused by an instruction in a delay slot (that is,
ESR[DS]=1), the exception handler should return execution to
the address stored in BTR instead of the normal exception return
address stored in R17.
"""

Adjust the code to print the proper return address for delay slot
exceptions.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-4-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
7422b41175 microblaze: exception: fix delay slot exception handling
The switch statement in _hw_exception_handler() only covers the
rightmost 5 bits that encode the exception cause:
switch (state & 0x1f)
{
...
}

For this reason, the "0x1000" case will never be reached, because the 13th
bit was zeroed out. To fix this, move delay slot exception handling before
the switch statement (delay slot (DS) bit in Exception Status Register is
independent of the exception cause (EC)).

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-3-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
1669b3d1a0 microblaze: exception: migrate MICROBLAZE_V5 to Kconfig
Also, rename it to XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP, since it only
covers delay slot exception support.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-2-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Ovidiu Panait
4fef0a7b7e microblaze: exception: move privileged instruction exception out of v5 ifdef
The privileged instruction exception seems to have been introduced in
microblaze v7.00 along with MMU support, so having it wrapped in
MICROBLAZE_v5 ifdefs seems incorrect. Move it out of the ifdef, since all
recent microblaze versions support it.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-1-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15 13:11:43 +01:00
Michal Simek
753a29522c xilinx: Remove GPIO_EXTRA_HEADER selection
Platform specific headers are empty that's why there is no need to include
them. That's why remove them for Zynq/ZynqMP and Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/625b1be0b813e2b9a5323c0529f9c567bfe13e75.1643960446.git.michal.simek@xilinx.com
2022-02-15 13:06:13 +01:00
Felix Brack
9f0deae6d5 arm: pdu001: Fix dt to work with the current am33xx dtsi files
The changes introduced with commit 6337d53fdf ("arm: dts: sync am33xx
with Linux 5.9-rc7") prevent the PDU001 from operating correctly.
This patch fixes the configuration of the pin multiplexer and uart3.

Signed-off-by: Felix Brack <fb@ltec.ch>
2022-02-14 13:04:39 -05:00
Simon Glass
aafb31fc95 acpi: Move acpi_write_tables() to a generic header
This function is used by both x86 and sandbox. Put it in a common header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-11 11:29:23 -05:00
Sinthu Raja
ad41ed1208 arm:dts:k3-am64-sk: EMIF tool update to 0.8.0 with 1333MTs for lpddr4
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
* disabled Write DQ training
* improve CA ODT to 60 ohms

The lpddr4 enabled with periodic WDQ training is causing periodic 26us
stall. This makes the SoC stall without doing anything which leads to
R5 interrupt latency in TCM memory. Due to this periodic training there
are some outstanding CPU transactions waiting for the lpddr4 to complete.

Hence, disable the periodic write DQ training during the
non-initialization stage of lpddr4 which results in an approximate 1us
stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms

The rationales are as follows:
- PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling,
  disable bit 1 that supports Write DQ during non-initialization to
  avoid ~26us stall during code execution.

- MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes
  the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by
  increasing the signal swing.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-10 17:17:39 -05:00
Ovidiu Panait
6303b275a3 powerpc: mpc8xx: drop CONFIG_SYS_RESET_ADDRESS
There are no boards that define CONFIG_SYS_RESET_ADDRESS, so drop the
associated mpc8xx code that checks for it.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2022-02-10 16:44:23 -05:00
Mark Kettenis
7184e2997e spi: apple: Add driver for Apple SPI controller
Add a driver for the SPI controller integrated on Apple SoCs.
This is necessary to support the keyboard on Apple Silicon laopts
since their keyboard uses an Apple-specific HID over SPI protocol.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on: Macbook Air M1
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10 16:44:23 -05:00
Mark Kettenis
81fafbbeba power: domain: apple: Add reset support
The power management controller found on Apple SoCs als provides
a way to reset all devices within a power domain. This is needed
to cleanly shutdown the NVMe controller before we hand over
control to the OS.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on: Macbook Air M1
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-10 16:44:23 -05:00
Mark Kettenis
02e2588d3f arm: apple: Add RTKit support
Most Apple IOPs run a firmware that is based on what Apple calls
RTKit. RTKit implements a common mailbox protocol.  This code
provides an implementation of the AP side of this protocol,
providing a function to initialize RTKit-based firmwares as well
as a function to do a clean shutdown of this firmware.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on: Macbook Air M1
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10 16:44:23 -05:00
Mark Kettenis
a4bd5e4120 arm: apple: Change SoC name from "m1" into "apple"
U-Boot is expected to support multiple generations of Apple SoCs
in a single binary with a single defconfig. Therefore it makes
more sense to set SYS_SOC to "apple".

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-10 16:44:23 -05:00
Mark Kettenis
456305ec59 mailbox: apple: Add driver for Apple IOP mailbox
This mailbox driver provides a communication channel with the
Apple IOP controllers found on Apple SoCs.  These IOP controllers
are used to implement various functions such as the System
Manegement Controller (SMC) and NVMe storage.  It allows sending
and receiving a 96-bit message over a single channel.

The header file with the struct used for mailbox messages is taken
straight from Linux.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on: Macbook Air M1
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10 16:44:23 -05:00
Moritz Fischer
058fb9f5ff acpi: Move MCFG implementation to common lib
MCFG tables are used on multiple arches. Move to common ACPI lib.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use sizeof(*mcfg) instead of sizeof(*header)
Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09 12:30:13 -07:00
Moritz Fischer
ab2ffe7359 arch: x86: lib: acpi_table: Fix MCFG entries
Commit d953137526 ("x86: Move SSDT table to a writer function")
introduced a bug where the actual MCFG entries are no longer generated.

Cc: Simon Glass <sjg@chromium.org>
Fixes: d953137526 ("x86: Move SSDT table to a writer function")
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-09 12:30:13 -07:00
Heinrich Schuchardt
ebc87d0daf sandbox: fix build failure with musl and SDL
sdl.c is compiled against the SDL library.

Trying to redefine wchar_t with -fshort-wchar is not necessary
and leads to build failures when compiling against musl.

Cc: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09 12:26:12 -07:00
Rasmus Villemoes
3609e1dc5f dts: automatically build necessary .dtb files
When building for a custom board, it is quite common to maintain a
private branch which include some defconfig and .dts files. But to
hook up those .dts files requires modifying a file "belonging" to
upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch
to a newer upstream then often results in a conflict which, while it
is trivial to resolve by hand, makes it harder to have a CI do "try to
build our board against latest upstream".

The .config usually includes information on precisely what .dtb(s) are
needed, so to avoid having to modify the Makefile, simply add the
files in (SPL_)OF_LIST to dtb-y.

A technicality is that (SPL_)OF_LIST is not always defined, so rework
the Kconfig symbols so that (SPL_)OF_LIST is always defined (when
(SPL_)OF_CONTROL), but only prompted for in the cases which used to be
their "depends on".

nios2 and microblaze already have something like this in their
dts/Makefile, and the rationale in commit 41f59f6853 is similar to
the above. So this simply generalizes existing practice. Followup
patches could remove the logic in those two makefiles, just as there's
potential for moving some common boilerplate from all the
arch/*/dts/Makefile files to the new scripts/Makefile.dts.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09 12:26:12 -07:00
Simon Glass
edca8cf721 Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SCSI_AHCI_PLAT
   CONFIG_SYS_SCSI_MAX_SCSI_ID
   CONFIG_SYS_SCSI_MAX_LUN
   CONFIG_SYS_SATA_MAX_DEVICE

Drop CONFIG_SCSI for everything except the sandbox build. We only need
one build for tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09 09:16:48 -05:00
Simon Glass
ce30e3ff1e scsi: Drop CONFIG_SYS_SCSI_MAX_DEVICE
This is defined based on two other CONFIGs for all boards except sandbox
and durian.

For sandbox the value does not matter. For durian the value seems
excessive.

Drop the option completely, to simplify configuration and reduce the
number of things we need to convert to Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09 09:16:48 -05:00
Simon Glass
d2da54bfc4 Convert CONFIG_SYS_IDE_MAXBUS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_IDE_MAXBUS
   CONFIG_SYS_IDE_MAXDEVICE
   CONFIG_SYS_ATA_BASE_ADDR
   CONFIG_SYS_ATA_STRIDE
   CONFIG_SYS_ATA_DATA_OFFSET
   CONFIG_SYS_ATA_REG_OFFSET
   CONFIG_SYS_ATA_ALT_OFFSET
   CONFIG_SYS_ATA_IDE0_OFFSET
   CONFIG_SYS_ATA_IDE1_OFFSET
   CONFIG_ATAPI
   CONFIG_IDE_RESET

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09 09:16:47 -05:00
Simon Glass
d67f9e35c4 mips: Avoid using config_enabled() directly
Use IS_ENABLED() instead, which is the correct macro for checking a CONFIG
option.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-08 23:07:59 -05:00
Simon Glass
5c86a8f7a1 imx: Don't define __ASSEMBLY__ in source files
This is supposed to be a build-system flag. Move it there so we can
define it before linux/kconfig.h is included.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-08 23:07:58 -05:00
Aswath Govindraju
a94d70ad37 arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
Add support for QSGMII multilink configuration.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 11:00:04 -05:00
Aswath Govindraju
3c1d89ff76 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 11:00:03 -05:00
Keerthy
57b02b79f3 dts: am57xx*: Add ipu early boot DT changes
Add support for ipu early boot.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
5717294230 arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
5329c548eb arm: dts: dra7: Add ipu and related nodes
Add ipu and the associated nodes.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
0bfc701e67 dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot related nodes
Add all the ipu early boot related nodes

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:03 -05:00
Keerthy
b071a07743 drivers: misc: Makefile: Enable fs_loader compilation at SPL Level
Enable fs_loader compilation at SPL Level.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix compilation failures for J721e platform]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:02 -05:00
Keerthy
0197909dd1 arm: mach-omap2: load/start remoteproc IPU1/IPU2
First check the presence of the ipu firmware in the boot partition.
If present enable the ipu and the related clocks & then move
on to load the firmware and eventually start remoteproc IPU1/IPU2.

do_enable_clocks by default puts the clock domains into auto
which does not work well with reset. Hence adding do_enable_ipu_clocks
function.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix IPU1_LOAD_ADDR and compile warnings]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
81fb00b884 arm: dts: k3-j721s2-ddr: Add DDR support
J721S2 can support two instances for DDR. Therefore, add the device support
for the same and use 4266MT/s as DDR frequency.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
626a2fdb98 arm: dts: k3-j721s2: Add r5 specific dt support
Add initial support for device tree that runs on R5.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
a9d8cf24a4 arm: dts: Add support for A72 specific J721S2 Common Processor Board
The EVM architecture for J721S2 is similar to that of J721E and J7200. It
is as follows,

+------------------------------------------------------+
|   +-------------------------------------------+      |
|   |                                           |      |
|   |        Add-on Card 1 Options              |      |
|   |                                           |      |
|   +-------------------------------------------+      |
|                                                      |
|                                                      |
|                     +-------------------+            |
|                     |                   |            |
|                     |   SOM             |            |
|  +--------------+   |                   |            |
|  |              |   |                   |            |
|  |  Add-on      |   +-------------------+            |
|  |  Card 2      |                                    |    Power Supply
|  |  Options     |                                    |    |
|  |              |                                    |    |
|  +--------------+                                    | <---
+------------------------------------------------------+
                                 Common Processor Board

Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.

Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
05d441a713 arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
2bab70ed04 arm: dts: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.

Some highlights of this SoC are:

* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.

See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28

Introduce basic support for the J721S2 SoC.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2022-02-08 09:41:27 -05:00
David Huang
681023aba4 arm: K3: Add basic support for J721S2 SoC definition
Add basic support for J721S2 SoC definition

Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2022-02-08 09:41:26 -05:00
Marcel Ziswiler
2bc2f817ce board: toradex: add verdin imx8m plus support
This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB
IT V1.0B module. They are strapped to boot from eFuses which are factory
fused to properly boot from their on-module eMMC. U-Boot supports
booting from the on-module eMMC only, SDP support is disabled for now
due to missing i.MX 8M Plus USB support.

Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet both on-module eQoS and FEC (requires PHY on carrier board)
- GPIOs
- I2C

Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper

ATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.

Boot:
U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
Quad die, dual rank failed, attempting dual die, single rank configuration.
Normal Boot
WDT:   Started watchdog@30280000 with servicing (60s timeout)
Trying to boot from BOOTROM
Find img info 0x&48025a00, size 872
Need continue download 1024
Download 779264, Total size 780424
NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
NOTICE:  BL31: Built : 16:52:37, Aug 26 2021

U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)

CPU:   Freescale i.MX8MP[8] rev1.1 at 1200 MHz
Reset cause: POR
DRAM:  8 GiB
Core:  78 devices, 18 uclasses, devicetree: separate
WDT:   Started watchdog@30280000 with servicing (60s timeout)
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
Setting variant to wifi
Net:   Hard-coding pdata->enetaddr
eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
Hit any key to stop autoboot:  0
Verdin iMX8MP #

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-07 16:33:22 +01:00
Michal Simek
af98bf62fa arm64: zynqmp: Remove SOM *u-boot.dtsi
Disable mmc from u-boot.dtsi file because it was there only for kv260
board. With kr260 this is not needed because we will switch to full DT per
board with SD/EMMC there too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3440d9f94361b4800658f313a5785f43ee84ecf3.1642590109.git.michal.simek@xilinx.com
2022-02-07 10:37:21 +01:00
Heiko Thiery
16c7369ede board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board support
The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-02-05 15:49:02 +01:00
Angus Ainslie
be63dc7956 mach-imx: iomux-v3: add a define for the SION bit
SION (Software Input On Field) - force the select mode input path

Signed-off-by: Angus Ainslie <angus@akkea.ca>
2022-02-05 15:49:02 +01:00
Angus Ainslie
881c8a6154 arm: dts: imx8mq kernel dts updates
Update to the 5.16 imx8mq dts files and dt bindings

Changes since v1:

Dropped rfkill.h that is not in linux mainline yet.

Signed-off-by: Angus Ainslie <angus@akkea.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:02 +01:00
Dario Binacchi
0c9c5d2ca5 mx6: crm_regs: drop BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ
Commit 97c16dc8bf ("imx: mx6ull: update the REFTOP_VBGADJ setting")
made this macro unused. Then remove it.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:02 +01:00
Dario Binacchi
c1af358cf5 imx: mx6ull: fix REFTOP_VBGADJ setting
The previous code wrote the contents of the fuse as is in the
REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of
the table in the code comment. This table is also different from the
table in the commit description. But then, which of the two is correct?
If it is assumed that an unprogrammed fuse has a value of 0 then for
backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to
6 (b'110). Therefore, the table in the code comment can be considered
correct as well as this patch.

Fixes: 97c16dc8bf ("imx: mx6ull: update the REFTOP_VBGADJ setting")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-02-05 15:49:02 +01:00
Richard Zhu
0e0ae730bb arm64: dts: imx8mm: Add the pcie support
Add the PCIe support on i.MX8MM platforms.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux 854a4766ac12 ("arm64: dts: imx8mm: Add the pcie support")
2022-02-05 15:49:01 +01:00
Richard Zhu
f1cc436247 arm64: dts: imx8mm: Add the pcie phy support
Add the PCIe PHY support on iMX8MM platforms.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux b9ec888f636f ("arm64: dts: imx8mm: Add the pcie phy support")
2022-02-05 15:49:01 +01:00
Ying-Chun Liu (PaulLiu)
6c3373b386 arm: dts: add imx8mp-rsb3720-a1 dts file
Add board dts for Advantech's imx8mp-rsb3720-a1

Signed-off-by: Darren Huang <darren.huang@advantech.com.tw>
Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw>
Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw>
Signed-off-by: Tim Liang <tim.liang@advantech.com.tw>
Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05 15:49:01 +01:00
Marek Vasut
dd4b3ca52c arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B
The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020
documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the
pinmux tables.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Oliver Stäbler
9aac5c3c7e arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
Fix address of the pad control register
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2.  This seems
to be a typo but it leads to an exception when pinctrl is applied due to
wrong memory address access.

Signed-off-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Picked from Linux 5cfad4f45806f ("arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0")
2022-02-05 15:49:01 +01:00
Marek Vasut
2c9d2acefa ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options
Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs
in case they should be operated faster, e.g. to improve boot time.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-05 15:49:01 +01:00
Marek Vasut
66e90be99f ARM: imx: imx8m: Align PLL 1.2 GHz option with Linux
Linux uses slightly different divider settings for the 1.2 GHz PLL
configuration, adjust the coefficients to match Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-05 15:49:01 +01:00
Andrey Zhizhikin
1289ff7bd7 imx8m: lock id_swap_bypass bit in tzc380 enable
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
order to avoid AXI bus errors when GPU is enabled on the platform.
TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
derivatives, but is missing a lock settings to be applied.

Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
it implemented.

Since we're here, provide also names to bits from TRM instead of using
BIT() macro in the code.

Fixes: deca6cfbf5 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors")
Fixes: a07c718129 ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Peng Fan <peng.fan@nxp.com>
2022-02-05 15:49:01 +01:00
Adam Ford
2f95456a9a imx: imx8mm_beacon: Enable USB
With the updated device tree's having USB support, enable in
U-Boot.  This also requires the addition of the imx8m power
domain, since the USB is gated by the power domain controller.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Adam Ford
d81c6a9f63 arm: dts: imx8mm-beacon: Resync dtsi with Kernel 5.17-rc1
Resync the SOM and baseboar files with the device trees that will
be included in 5.17-RC1 when it's cut.  This will improve pinmuxing
for USDHC1 and add USB functionality.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Andrey Zhizhikin
94588ff395 imx8mn-ddr4-evk: generate single bootable image
As suggested in commit 028abfd9b1 ("imx8mm-evk: Generate a single
bootable flash.bin again") for imx8mm_evk, it is possible to produce
single bootable image via binman. This restores the original behavior in
distros, where only one boot container is used to create target image.

Perform similar adaptions in order to provide single bootable image for
imx8mn-ddr4-evk derivate.

Update documentation to drop additional step of copying u-boot.itb

Fixes: 353dfe4b43 ("imx8mn-ddr4-evk: switch to use binman")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Patrick Wildt
ea4e9387e3 arm64: dts: imx8mq-u-boot.dtsi: improve odd blob-ext naming
Rather than using odd implicit blob-ext naming, explicitly specify the
type to be of blob-ext and therefore also simplify the node naming.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05 15:49:01 +01:00
Patrick Wildt
49f55653fd arm64: dts: imx8mm-u-boot.dtsi: use dash for node names
Some of the nodes were named using a underscore, so rectify this and
consistenly use dashes.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-02-05 15:49:01 +01:00
Patrick Wildt
553216f6f9 arm64: dts: imx8mq-u-boot.dtsi: explicitly add spl filename
Explicitly add SPL aka u-boot-spl.bin filename.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05 15:49:01 +01:00
Patrick Wildt
440c7d1188 arm64: dts: imx8mq-u-boot.dtsi: alphabetically re-order properties
Alphabetically re-order properties.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05 15:49:01 +01:00
Heiko Thiery
1bcda4efed imx: imx8mm: imx8mm-kontron-n801x-s: add common board u-boot.dtsi
When using a board variant that selects the lvds specific dtb the
*.u-boot.dtsi file will not be included. To have a lvds dtb specific
u-boot.dtsi file move this part to a common board u-boot.dtsi file and
include this in the board base u-boot.dtsi and create an additional one
for the lvds variant.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-02-05 15:49:01 +01:00
Michael Trimarchi
02737ac86d cmd_nandbcb: Support secondary boot address of imx8mn
Add support of secondary boot address for imx8mn. The secondary
boot address is hardcoded in the fuse. The value is calculated
from there according to the following description:

The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows:
- Secondary boot is disabled if fuse value is bigger than 10, n = fuse
  value bigger than 10.
- n == 0: Offset = 4MB
- n == 2: Offset = 1MB
- Others & n <= 10 : Offset = 1MB*2^n
- For FlexSPI boot, the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-02-05 13:38:39 +01:00
Sven Schwermer
0be742d06d imx: Enable ACTLR.SMP in SPL for i.MX6/7
Similar to what has been done before with c5437e5b for u-boot proper, we
enable the SMP bit for SPL as well. This is necessary when SDP booting
straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
ROM code does not set this bit which makes the caches not work once
activated in Linux.

On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into
an initramfs shell from ~6.1s down to ~1.2s.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Marek Vasut
8ed378ff78 ARM: dts: imx: Synchronize iMX6QDL DHCOM PDK2 DTs with Linux 5.15.12
Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The imx6qdl-dhcom-pdk2.dtsi
had to be adjusted with additional headers, gpio.h, pwm.h, input.h, else
the DT cannot be compiled, the same change is likely necessary in Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Marek Vasut
2ab0b52841 ARM: dts: imx: Add labels to remaining anatop regulators
Add labels to remaining anatop regulators, so their supplies can be
assigned in board DTs. This is similar to Linux kernel commit
93385546ba369 ("ARM: dts: imx6qdl-sabresd: Assign corresponding power supply for LDOs")
except it does not contain the unrelated sabresd changes.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Lukasz Majewski
e2a636082e arm: dts: Enable support for USB on XEA (imx28) board
This change enables the support for USB with DM on the XEA (imx28)
board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-02-05 13:38:39 +01:00
Lukasz Majewski
1e7212ee9f xea: dts: Update the SPI-NOR flash memory partitions description
Now the dts information corresponds to the one available in the kernel.
With this patch applied the 'mtd list' shows proper names and
offsets for MTD partitions.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-02-05 13:38:39 +01:00
Lukasz Majewski
014315b2d8 spl: Provide more space to be used for storing SPL on imx28 OCRAM
With the current configuration provided in mxsimage{-spl}.mx28.cfg the
size of SPL binary has been constrained to 32 KiB, due to "LOAD IVT"
command with 0x8000 offset.

The problem was that, the imx28 ROM takes the u-boot.sb and then
extracts from it the IVT header and places it on the 0x8000 OCRAM offset
overwriting any valid (i.e. loaded from eMMC or SPI-NOR) SPL code. This
bug was unnoticed as the overwrite size was just 32 bytes, so the
probability that some important code is altered was low.

However, in the XEA board (where the SPL size is ~39KiB), the overwritten
data was `(struct dm_spi_ops *) 0x800c <mxs_spi_ops>`, which is used
during the boot process.

As a result the SPL execution code hanged with "undefined instruction"
abort as callbacks (with wrong addresses) from it were called.

The fix is to change the OCRAM's offset where IVT is loaded to 0xE000,
so the SPL can grow up to ~57KiB (the maximal size of OCRAM memory
available is 0xE3FC).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-02-05 13:38:39 +01:00
Fabio Estevam
e195550bfd ARM: dts: imx6ull: Use the correct name for ESAI_TX0
According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may
have the ESAI_TX0 functionality, not ESAI_T0.

Also, NXP's i.MX Config Tools 10.0 generates dtsi with the
MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming, so fix it accordingly.

There are no devicetree users in mainline that use the old name,
so just remove the old entry.

Fixes: f8ca22b8de ("arm: dts: imx6ull: add pinctrl defines")
Reported-by: George Makarov <georgemakarov1@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Harald Seiler
12f9b4d086 mx6: Use imx6_src_get_boot_mode() to check boot device
Use imx6_src_get_boot_mode() instead of manually reading SBMR1.  The
existing function has proper handling for software overrides of the
bootdevice which can happen, for example, when booting from an alternate
source using `bmode`.

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Christoph Niedermaier
ca27227c59 ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board
The PDK2 board is capable of running both 100M and 1G ethernet. However,
the i.MX6 has only one ethernet MAC, so it is possible to configure
either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
the PDK2 board with another RJ45 port. 100M and 1G ethernet use
different signal pins from the i.MX6, but share the MDIO bus.

This SoM board combination is used to demonstrate how to enable 1G
ethernet configuration.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-05 13:38:39 +01:00
Ariel D'Alessandro
c4c1ed68c1 imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:

- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Oleksandr Suvorov
4821074bec colibri-imx8x: add on-module gpio expander fxl6408
The FXL6408 GPIO expander manages critical devices,
including on-module USB hub. Configure the expander to
switch the USB hub into bypass mode, allowing to use
on-carrier-board USB hub.

Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05 13:38:39 +01:00
Ying-Chun Liu (PaulLiu)
556523b955 arm: imx8m: imx8mm-cl-iot-gate: detect extension board
Extension boards can be added to Compulab's iot-gate-imx8mm.
We implement extension board manager for detecting the extension
boards.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05 13:38:39 +01:00
Ying-Chun Liu (PaulLiu)
27ea1c53a3 arm: dts: imx8mm-cl-iot-gate: add Compulab's ied overlays
add the following overlays:
 - IED extension board
 - CAN/TPM/ADC extension board on IED board.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05 13:38:39 +01:00
Alice Guo
6293b73d0f imx8ulp: implement to obtain the SoC current temperature
Obatin the SoC current temperature in print_cpuinfo().

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
dc77d0f9fc imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Alice Guo
0f9b10aaba imx8ulp: clock: Support to enable/disable the ADC1 clock
This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
484b306b9e imx8ulp: Update ethernet mac to get from fuse
Get the MAC address from fuse bank5 word 3 and 4. It has
MSB first at lowest address, so have a reverse order with other
iMX used in mac.c

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
3b32010691 imx8ulp: clock: Support to reset DCNano and MIPI DSI
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
55a7e7882d imx8ulp: clock: Reset DDR controller before clock enable
The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
9c7fbebe5d imx8ulp: Workaround LPOSC_TRIM fuse load issue
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.

A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
112b4cac9d imx8ulp: Remove freescale name from CPU revision
Remove the freescale vendor name from CPU revision print to align
with other i.MX platforms

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
bd8b673003 imx8ulp: Fix DCNANO QoS setting
The setting does not have effect because we should set it after
power on the PS16 for NIC AV.

So move it after upower_init which has powered on all PS

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
16062f9b0a imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest
To avoid DCNANO underrun issue on high loading test, set its
read Qos on NIC_LPAV to highest

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
9dde390be6 imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display
The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and
backlight. However the LPI2C0 and TPM0 are M33 resources, in this
patch we simply access them, but this is a temporary solution.
We will modify it when M33 FW changes to set MIPI DSI panel as default
path and enable backlight after reset.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
608ed200f1 imx8ulp: rdc: allow A35 access flexspi0 mem
For singel boot, set flexspi0 mem to be accessed by A35

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
829e06bf41 imx8ulp: clock: Add MIPI DSI clock and DCNano clock
Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
5ff18da34f imx8ulp: clock: Support LPAV clocks in cgc and pcc
Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Peng Fan
99de168f7e imx8ulp: assign PXP/HIFI4/EPDC to APD domain
Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not
able to receive interrupts from the modules.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
d563d29203 arm: imx8ulp: Allocate LPAV resources to AP domain
When single boot, assign AP domain as the master domain of the LPAV.
Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI
eDMA channel and eDMA request to APD

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
961ac78735 imx8ulp: soc: Check the DBD_EN fuse before setting RDC
S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC
is allowed by all masters.

Current S400 has issue if the XRDC has released to A35, then A35 reset
will fail in ROM due to S400 fails to get XRDC.
So temp work around is checking the DBD_EN, if it is not fused, we
don't need to call release XRDC or TRDC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ricardo Salveti
89ca5a7ee1 ARM: imx8m: support env in fat and ext4
Change boot device logic to also allow environment stored in fat and in
ext4 when booting from SD or from eMMC.

As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location
to use IS_ENABLED instead for all modes, returning NOWHERE when no valid
mode is found.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Pali Rohár
af602631e0 imx: nandbcb: Fix printf format in write_fcb
Correct printf format for unsigned long long is %llx and not %llxx.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Lukasz Majewski
91f27f3ba8 mxs: power: Change sequence of enabling DCDC switches
The imx28 uses following voltage supplies hierarchy:

VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM
			     \-----> VDDD

One shall first enable DCDC on the parent source (VDDIO) and then
follow with its children.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Tim Harvey
cd0ecb3d80 imx8mm-venice-gw7902: fix M2_RST# gpio pinmux
Fix the invalid gw7902 M2_RST# gpio pinmux.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Ricardo Salveti
8b71576f38 mx7ulp_com: add support for SPL
Add EA iMX7ULP COM board support for building SPL.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05 13:38:38 +01:00
Oleksandr Suvorov
498eedc0d4 mx7ulp: select soc features
Force selecting features present in SoC i.MX7ULP.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2022-02-05 13:38:38 +01:00
Heiko Thiery
6ff55bcd07 arm: imx: imx8mq: add support to get values for more clocks
Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK,
MXC_UART_CLK and MXC_QSPI_CLK.

At least for the I2C clock the missing support leads to a wrong
configured I2C frequency. The expected value is 100kHz but the resulting
value is about 1MHz.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Jorge Ramirez-Ortiz
25a91f3005 arm64: zynqmp: Print the secure boot status information
Output the secure boot configuration to the console.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Link: https://lore.kernel.org/r/20211013170447.10414-1-jorge@foundries.io
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-04 13:16:45 +01:00
Codrin Ciubotariu
17a9f3f53d ARM: dts: at91: sama7g5ek: disable slew rate for GMACs non MDIO pins
Non GMAC's MDIO pins should have slew rate disabled for R(G)MII modes. Set
them accordingly in DT.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-02-04 13:53:58 +02:00
Tom Rini
3aaabfe9ff Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This is the promised second part of the sunxi PR for 2022.04, albeit
technially outside of the merge window. We were working on this full
steam since the beginning of the year, and it deserves to be merged,
I think.
The main attraction is support for the F1C100s SoC, which sports a
venerable ARM926 core. Support for this SoC and the LicheePi Nano board
has been in Linux for years, and U-Boot patches were posted mid last
year already.
The new SoC using ARMv5 also means that the bulk of the new code should
not touch any existing boards, although we did some refactorings first,
of course, which actually cleans up some existing sunxi code.

Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1,
OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards,
including F1C100s and F1C200s devices.
2022-02-03 23:24:31 -05:00
Icenowy Zheng
ce2b6c4481 ARM: dts: suniv: Add device tree files and bindings for F1C100s
Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
dt-bindings/dts are synced with 5.16.0

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
cfe673cda7 mach-sunxi: Add support for SUNIV architecture
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
645ee3c25d sunxi: Add F1C100s DRAM initial support
Add support for F1C100s internal dram controller.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
5d35f0f254 ARM: sunxi: Add clock and uart to sunxi headers
This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
88998f7775 arm: arm926ej-s: Add sunxi code
Some Allwinner SoCs use ARM926EJ-S core.

Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Jesse Taube
0d4377fc92 mach-sunxi: Move timer code to mach folder
Both armv7 and arm926ejs use this timer code so move it to mach-sunxi.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
508f75afb5 arm: arm926ej-s: start.S: port save_boot_params support from armv7 code
The ARMv7 start code has support for saving some boot params at the
entry point, which is used by some SoCs to return to BROM.

Port this to ARM926EJ-S start code.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Andre Przywara
b8cd7f439a armv8: remove no longer needed lowlevel_init.S
When we added Allwinner SoC support to ARMv8, we needed to pull in an
implementation of lowlevel_init() calling the C function s_init(), as
sunxi required it as this time.

The last few patches got rid of this bogus requirement, and as sunxi was
still the only user, we can now remove this lowlevel_init.S from ARMv8
altogether.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-04 00:09:57 +00:00
Andre Przywara
534b82a1f2 sunxi: move early "SRAM setup" into separate file
Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied
from the original BSP U-Boot. The comment speaks of this being required
before DRAM access gets enabled, but there is no indication that this
would actually be required that early.

Move this out of s_init(), into board_init_f(). Since this actually only
affects a very few older SoCs, the actual code goes into the cpu/armv7
directory, to move it out of the way for all other SoCs.

This also uses the opportunity to convert some #ifdefs over to the fancy
IS_ENABLED() macros used in actual C code.

We keep the s_init() stub around for now, since armv8's lowlevel_init
still relies on it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-04 00:09:57 +00:00
Andre Przywara
2564fce7ee sunxi: move Cortex SMPEN setting into start.S
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.

This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).

In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.

This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:36 +00:00
Andre Przywara
5bc4cd05d7 sunxi: move non-essential code out of s_init()
So far all Allwinner based boards were doing some not-so-lowlevel-setup
in lowlevel's s_init() routine.
This includes the initial clock, timer and pinmux setup, among other
things. This is clearly out of the "absolute bare minimum to get started"
scope that lowlevel_init.S suggests for this function.

Since we have an SPL, which is called right after s_init(), move those
calls to our board_init_f() function. As we overwrite this only for
the SPL, this has the added benefit of not doing this setup *again*
shortly afterwards, when running U-Boot proper.

This makes gpio_init() to be called from the SPL only, so pull this code
into a CONFIG_SPL_BUILD protected part to avoid build warnings.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:03 +00:00
Andre Przywara
68f08966b0 armv8: start.S: remove CONFIG_SYS_RESET_SCTRL code
There is some code that tries to "reset" the SCTLR_ELx register early in
the boot process. The idea seems to be to guarantee some sane settings
that U-Boot actually relies on, for instance running in little-endian
mode, with the MMU off initially.
However the current code has multiple problems:
- For a start, no platform or config defines the symbol that would
  enable that code.
- The code itself really only works if the bits that it tries to clear
  are already cleared:
  - If we run in big-endian mode initially, any previous loads would have
    been wrong already. That applies to the (optional) relocation code,
    but more prominently to the mask that it uses to clear those bits:
    "ldr x1, =0xfdfffffa" looks innocent, but actually involves a memory
    access to the literal pool, using the current endianness.
  - If we run with the MMU enabled, we are probably doomed already. We
    *could* hope that we are running with an identity mapping, but would
    need to do some cache maintenance to avoid losing dirty cache lines.
- The idea of doing a read-modify-write of SCTLR is somewhat
  questionable to begin with, because as the owner of the current
  exception level we should initialise all bits of this register with a
  certain fixed value.
- The code is unnecessarily complicated, and the function name is
  misspelled.

While those problems *could* admittedly be fixed, the point that is does
not seem to be used at all at the moment tells me we should just remove
this code, and be it to not give a bad example.

If people care, I could introduce some proper SCTLR initialisation code.
We are about to work this out for the boot-wrapper[1] as we speak, but
apparently we got away without doing this in U-Boot ever since, so it
might not be worth the potential trouble.

[1] https://lore.kernel.org/linux-arm-kernel/20220114105653.3003399-7-mark.rutland@arm.com/

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-03 12:15:37 -05:00
Alper Nebi Yasak
22eb7ba80e armv8: spl: Fix build with LINUX_KERNEL_IMAGE_HEADER
Setting LINUX_KERNEL_IMAGE_HEADER=y attempts to include an ARM64 Linux
kernel image header at the start of both U-Boot proper and SPL binaries.
However, some definitions that the image header uses are not included by
the SPL linker script, resulting in a build error. Include them the way
they are included in U-Boot proper's linker script to fix the error.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-02-03 12:15:33 -05:00
Vladimir Oltean
681adaa466 arm: dts: ls1028a-qds: declare in-band autoneg for Ethernet ports
The commit in the Fixes: tag below broke traffic through switch ports
where the SERDES protocol requires in-band autoneg and this requirement
isn't described in the device tree: SGMII, QSGMII, USXGMII (with
2500Base-X, in-band autoneg isn't supported).

The LS1028A-QDS boards are not yet ready for syncing their device trees
with Linux, since Ethernet is missing there (but has been submitted):
https://lore.kernel.org/lkml/20211112223457.10599-11-leoyang.li@nxp.com/

When agreement is reached for the Ethernet support in Linux, there will
be a sync for these boards as well. For now, just enable in-band autoneg
to fix the breakage.

Fixes: e3789a7262 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
bee9fd2957 arm: dts: ls1028a-rdb: sync device tree with Linux
Allow device trees to be reused between Linux and U-Boot.
The source for these device trees is linux-next as of commit
bd8a9cd624c6 ("arm64: dts: ls1028a-rdb: update copyright"), which was
chosen because some changes needed to be done to the Linux DTs too,
before they could be shared:
https://lore.kernel.org/linux-arm-kernel/20211202141528.2450169-5-vladimir.oltean@nxp.com/T/#m6f63c92e75fa79a01144b2c2c6dc4776e7971395

There are two more commits on the RDB device tree which haven't been
picked up yet, because they have dependencies on the SoC device tree:

dd3d936a1b17 ("arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source")
b2e2d3e02fb6 ("arm64: dts: ls1028a-rdb: enable pwm0")

These will be picked up on the next resync.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
50c49ef2ff arm: dts: ls1028a-rdb: enable PCIe controllers from U-Boot dtsi
Reuse the scheme implemented by the Kontron SL28 boards in
commit d08011d7f9
("arm: dts: ls1028a: disable the PCIe controller by default")
and move the 'status = "okay"' lines for the PCIe controllers
inside a separate U-Boot dtsi for the LS1028A-RDB board. This way, the
existing Linux device tree can simply be dropped in.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
f33fad6f37 arm: dts: ls1028a-rdb: disable I2C buses 1 through 7
There is no I2C peripheral on these buses on the reference design board,
and the Linux device tree does not enable them either.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
5b0f8eeb3d arm: dts: ls1028a-rdb: disable DSPI nodes
There is no SPI peripheral on the LS1028A-RDB, therefore no reason to
enable these nodes in the U-Boot device tree (and Linux does not enable
them either).

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
4a5362fc10 arm: dts: ls1028a-rdb: sync Ethernet device tree nodes with Linux
In a bit of a blunder, the blamed commit in the Fixes: tag below made
the mscc_felix switch driver look at the 'managed = "in-band-status"'
device tree property, forgetting that the U-Boot device tree had not
been updated to include that property, whereas the Linux one does.

The switch is therefore described in the device tree as not requiring
in-band autoneg, but the PHY driver for VSC8514 (drivers/net/phy/mscc.c)
still enables that feature. This results in a mismatch => no traffic.

This patch is a copy-paste of the Ethernet device tree nodes from Linux,
which resolves that issue. The device tree update also renames the
Ethernet PHY labels.

Fixes: e3789a7262 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
5009b11bec arm: dts: ls1028a-rdb: sort nodes alphabetically
The nodes in the NXP LS1028A-RDB device tree are out of order, regroup
them alphabetically to have a simple delta when the Linux device tree is
brought in.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
aa0586247b arm: dts: lx2160a-rdb: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LX2160A-RDB to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
41496cc330 arm: dts: ls1028a-rdb: use Linux compatible string for RTC
During this board's sync with Linux device trees, it was observed that
it doesn't use the same compatible string for the RTC node as in U-Boot.
This change makes the RTC compatible strings match, for a smoother sync.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
801f4b0cde arm: dts: ls1028a-qds: use Linux compatible string for RTC
The LS1028A-QDS board won't be synced with the Linux device trees right
now, since those are currently still in progress (Ethernet is missing).

However, while we're at converting the RDB, it can be observed that the
same RTC is present on the two boards, and the wrong compatible string
is used in both places. This change updates the RTC from the QDS to use
the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
246b7e6c9f arm: dts: lx2160a-qds: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LX2160A-QDS to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
5d0b044e96 arm: dts: ls1088a-rdb: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LS1088A-RDB to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
489c428763 arm: dts: ls1088a-qds: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LS1088A-QDS to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Aleksandar Gerasimovski
2e14b1f33f arm/expu1/seli8: adapt dts NOR partition table to the latest used
Even not used by u-boot, this has to be inline with the hw and kernel dts.
U-boot partition table is defined by MTDPARTS_DEFAULT Kconfig.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Aleksandar Gerasimovski
7539bb3b7c arm: ls1021a: limit debug eth phy speed to 100Mbps
Beside that mounted rgmii debug phy is 1000Mbps capable, the debug link
between the piggy board and the phy is 100Mbps only.
This leads to longer link establishment time when working in debug mode,
as phy tries to autoneg 1000Mbps.

This patch fixes the speed to 100Mbps and allows smother link establishment
time for the debug interface.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:04:24 +05:30
Mathew McBride
a1d2fd3874 board: traverse: add initial Ten64 support
The Ten64 is a networking-oriented MiniITX board
using the NXP LS1088A SoC.

This patch provides the bare minimum to support
Ten64 boards under U-Boot for distroboot.

Some related drivers have not yet been submitted
and this basic support lacks some of the
opinionated defaults provided by our firmware
distribution.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:04:24 +05:30
Tony Dinh
71dcfa97fa arm: kirkwood: Pogoplug-V4 : Add Kconfig files
Add Kconfig files for Pogoplug V4 board

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-01-31 10:23:37 +01:00
Tony Dinh
cd1978719c arm: kirkwood: Pogoplug-V4 : Add DTS files
Add DTS files for Pogoplug V4 board

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-01-31 10:23:37 +01:00
Jernej Skrabec
e97943b732 sunxi: Fix H616 DRAM read calibration for dual rank
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
it has to be set before read calibration and cleared afterwards. This is
already done for first rank, but not for second (copy & paste error.)

Fix it.

Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Jernej Skrabec
18a5927698 sunxi: fix H616 DRAM ODT support
Kconfig symbol is missing CONFIG_ prefix, so compiler will always
skip ODT configuration.

Fix symbol name.

Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Chris Morgan
52bcc4f053 sunxi: Add option to prevent booting on power plug-in
For sunxi boards with the AXP209, AXP221, AXP809, and AXP818 PMICs
(plus possibly others, I only confirmed the datasheets for these),
it is sometimes desirable to not boot whenever the device is
plugged in. An example would be when using the NTC CHIP inside a
PocketCHIP.
This provides a configurable option to check if bit 0 of
register 0 of the PMIC says it was powered because of a power button
press (0) or a plug-in event (1). If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
[Andre: reword to speak of boot, remove #ifdefs]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Andre Przywara
8695b5111c sunxi: gpio: Fix up pointer arithmetic
The calls for flipping bits in the Allwinner pin controller registers
were using unnecessarily complex pointer arithmetic.

Improve readability by simplifying the expression.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Samuel Holland
efdd656659 sunxi: gpio: Add per-bank drive and pull setters
The GPIO and pinctrl drivers need these setters for pin configuration.
Since they are DM drivers, they should not be using hardcoded base
addresses. Factor out variants of the setter functions which take a
pointer to the GPIO bank's MMIO registers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Samuel Holland
ac5397a219 sunxi: gpio: Return void from setter functions
The return values of these functions are always zero, and they are
never checked. Since they are not needed, remove them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:04:30 +00:00
Vignesh Raghavendra
afe5163449 ARM: dts: k3-am642-sk: Disable cpsw_port1 in SPL
ROM supports cpsw_port2 for Ethernet boot and SPL stages continue to
download images on the same port, therefore there is no need to enable
cpsw_port1. Disable the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-28 17:58:41 -05:00
Heinrich Schuchardt
8e72374feb sandbox: eth-raw: fix building with musl library
The definition of struct udphdr in include netinet/udp.h in the
musl library differs from the definition in the glibc library.

To use the same definition with musl the symbol _GNU_SOURCE has
to be defined.

Reported-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2022-01-25 14:02:38 -07:00
Simon Glass
9d2adca8c3 x86: Move acpi_get_rsdp_addr() ACPI tables to the writer
Move this over to use a writer file, moving the code from the x86
implementation.

There is no need to store a separate variable since we can simply access
the ACPI context.

With this, the original monolithic x86 function for writing ACPI tables
is gone.

Note that QEMU has its own implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
a7e53b93b1 x86: Move device-specific ACPI tables to a writer function
Move this over to use a writer function, moving the code from the x86
implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
78031ad431 x86: acpi: Update acpi_fill_csrt() to use acpi_ctx
Update this function to the newer style, so we can avoid passing and
returning an address through this function.

Also move this function out of the x86 code so it can be used by other
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-01-25 11:44:36 -07:00
Simon Glass
85b8161b14 x86: Move CSRT table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
ef55f48788 x86: Move TCPA table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
c797f98bcd x86: Move MADT table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
9aacd83389 x86: Move TPM2 table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
d953137526 x86: Move SSDT table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
379d3c1fd6 x86: Move FACP table into separate functions
Each board has its own way of creating this table. Rather than calling the
acpi_create_fadt() function for each one from a common acpi_write_fadt()
function, just move the writer into the board-specific code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-01-25 11:44:36 -07:00
Simon Glass
138d7ece70 x86: Move FADT table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
32af3261f7 x86: Move GNVS table to a writer function
Move this table over to use a writer function, for x86 only. Handle the
two cases

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
eacb6d0ba2 x86: Move DSDT table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Add a pointer to the DSDT in struct acpi_ctx so we can reference it later.

Disable this table for sandbox since we don't actually compile real ASL
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
a53d38f80a x86: Move FACS table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Add a pointer to the DSDT in struct acpi_ctx so we can reference it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
94ba15a3f1 x86: Move base tables to a writer function
Use the new ACPI writer to write the base tables at the start of the area,
moving this code from the x86 implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
31c27eb830 x86: Use the ACPI table writer
Use the new ACPI writer to write the ACPI tables. At present this is all
done in one monolithic function. Future work will split this out.

Unfortunately the QFW write_acpi_tables() function conflicts with the
'writer' version, so disable that for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
cc1f8c3988 x86: acpi: Split out context creation from base tables
At present acpi_setup_base_tables() both sets up the ACPI context and
writes out the base tables.

We want to use an ACPI writer to write the base tables, so split this
function into two, with acpi_setup_ctx() doing the context set, and
acpi_setup_base_tables() just doing the base tables.

Disable the writer's write_acpi_tables() function for now, to avoid
build errors. It is enabled in a following patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
383bf1bc9e acpi: Move acpi_fill_header() to the generic header
This function is not x86-specific so move it into the common header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
437992d3a9 acpi: Use finer-grained control of ACPI-table generation
Rather than keying everything off ACPIGEN, use the main
GENERATE_ACPI_TABLE option to determine whether the core ACPI code
is included. Make sure these option are not enabled in SPL/TPL since we
never generate tables there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
0679cca507 sandbox: Allow building with GENERATE_ACPI_TABLE
At present this option is missing a header file, a function prototype and
the qfw driver needs a header included.

Fix these problems so we can enable this option on sandbox. This will
increase the build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
27ba6289fe x86: Tidy up use of CONFIG_ACPIGEN
This is enabled for quite a few boards which don't create ACPI tables.
Tidy this up by dropping the option for some boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
0153723590 arm: Allow supporting ACPI-table generation
Some ARM boards are using ACPI now. It seems that U-Boot should support
this method. Add ARM to the list of archs which can generate ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
233f0e35a3 x86: Move the acpi table to generic global_data
Allow this to be used on any arch. Also convert to using macros so that
we can check the CONFIG option in C code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
e1722fcb7d x86: Allow any arch to generate ACPI tables
These have sadly found their way to ARM now. Allow any arch to support
generating ACPI tables.

Disable this for the tools build.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Patrice Chotard
22c0815eca configs: stm32mp15: Enable OF_BOARD flag
Since commit 9855034397 ("fdt: Don't call board_fdt_blob_setup()
 without OF_BOARD") board_fdt_blob_setup() is no more called on
STM32MP platforms in trusted boot which hangs during boot process.

Enable OF_BOARD flag to fix this issue.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-01-24 11:03:21 +01:00
Patrick Delaunay
94e561f84a stm32prog: add partition name in treat_partition_list error messages
Add the partition name and remove the line number in error messages
of treat_partition_list() to provide correct information to user of
STM32CubeProgrammer.

The "line number" value was confusing because it is incorrect here;
the index in  part_array[] is not aligned with the line number in
the parsed Layout file, because the empty lines and the lines beginning
by '#' are skipped during the first parsing in parse_flash_layout().

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 11:01:41 +01:00
Marek Vasut
332facce6f ARM: dts: stm32: Synchronize DHCOM DTs with Linux 5.15.12
Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias and
PHY reset GPIO are now reinstated in SoM u-boot dtsi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-01-24 10:57:56 +01:00
Marek Vasut
6b8bd70904 ARM: dts: stm32: Synchronize DHCOR DTs with Linux 5.15.12
Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias is
now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96
u-boot dtsi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-01-24 10:57:56 +01:00
Patrick Delaunay
bd485f9bcc arm: dts: stm32mp15: alignment with v5.16
Device tree alignment with Linux kernel v5.16-rc5
- ARM: dts: stm32: set otg-rev on stm32mp151
- ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: fix SAI sub nodes register range
- ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkx

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:57:19 +01:00
Patrick Delaunay
5c68904fe1 stm32mp: correct the dependency for bootcount configs
Default value for CONFIG_SYS_BOOTCOUNT_SINGLEWORD and
CONFIG_SYS_BOOTCOUNT_ADDR are only needed when
CONFIG_BOOTCOUNT_GENERIC is used.

This patch avoids to define these configs when an other bootcount backend
is activated, for example for CONFIG_BOOTCOUNT_ENV.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:56:45 +01:00
Patrick Delaunay
d5e8119bae stm32mp: remove the bootcount activation
Today the bootcount is not managed by the Linux kernel for STM32MP15 as
we don't have driver to update the used backup register in TAMP and the
recovery command still executes the normal bootcmd with
'altbootcmd=run bootcmd'.

So the bootcount feature is never used, the config CONFIG_BOOTCOUNT_LIMIT
and the associated environment variable 'altbootcmd' can be removed to
reduce the U-Boot size.

Each boards can re-enable this feature later in their defconfig, if it is
needed, with the expected backend, for example CONFIG_BOOTCOUNT_GENERIC
or CONFIG_BOOTCOUNT_ENV.

CC: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:56:45 +01:00
Marek Vasut
3919aa1722 ARM: dts: stm32: Add DFU support for DHCOR recovery
This patch configures U-Boot SPL for DHCOR SoM to permit DFU upload of
SPL and subsequent u-boot.itb for recovery or commissioning purposes.

To start U-Boot on DHCOR based board, e.g. Avenger96, proceed as follows:
- Install dfu-util on the host PC (in debian this is package 'dfu-util')

- Power off the Avenger96 board.
- Connect both USB-serial console and USB-OTG microB ports to host PC.
- Switch Avenger96 to USB boot mode -- BOOT0..2 switches all set to 0.
- Power on the Avenger96 board.
- Verify using '$ dmesg' that a new device has been detected as follows:
    New USB device found, idVendor=0483, idProduct=df11, bcdDevice= 2.00
    New USB device strings: Mfr=1, Product=2, SerialNumber=3
    Product: DFU in HS Mode @Device ID /0x500, @Revision ID /0x0000
    Manufacturer: STMicroelectronics

- Upload U-Boot SPL:
$ dfu-util -a 1 -D u-boot-spl.stm32
- Upload U-Boot proper:
$ dfu-util -a 0 -D u-boot.itb

- At this point, SPL will wait for user to press "Ctrl-C" on serial
  console. When ready to interact with U-Boot, press Ctrl-C to start
  the bootloader.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:55:06 +01:00
Marek Vasut
757c8387be arm: stm32mp: Fix USB boot device report
In case the SoC reports the boot device type is USB, it means the SPL was
loaded via BootROM DFU mode. Currently the spl_boot_device() returns boot
device as USB host, change it to DFU instead, so the SPL can continue the
DFU boot and load U-Boot via DFU.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:52:49 +01:00
Tom Rini
d323242b62 Merge https://source.denx.de/u-boot/custodians/u-boot-sh
- rzg2_beacon updates
2022-01-23 09:54:49 -05:00
Adam Ford
16f4d36c7b arm: dts: rz-g2-beacon-u-boot: Enable pinmux for QSPI
When booting from QSPI, the boot ROM appears to mux the QSPI
pins, but it's not guaranteed to be setup when booting from
eMMC.  Fix this by explicitly configuring the pinmux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-01-22 23:12:56 +01:00
Tom Rini
da158ec5f2 Pull request for efi-2022-04-rc1-2
Documentation:
 
 * describe printf() format codes
 
 UEFI
 
 * enable more algorithms for UEFI image verification, e.g. SHA256-RSA2048
 
 General
 
 * simplify printing short texts for GUIDs
 * provide a unit test for printing GUIDs
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Merge tag 'efi-2022-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-04-rc1-2

Documentation:

* describe printf() format codes

UEFI

* enable more algorithms for UEFI image verification, e.g. SHA256-RSA2048

General

* simplify printing short texts for GUIDs
* provide a unit test for printing GUIDs
2022-01-22 15:43:36 -05:00
Patrick Delaunay
3425decf52 Convert CONFIG_AT91_EFLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_AT91_EFLASH

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-21 14:01:35 -05:00
Simon Glass
d3877fba31 Convert CONFIG_BOOTP_SERVERIP to Kconfig
This converts the following to Kconfig:
   CONFIG_BOOTP_SERVERIP

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-21 14:01:35 -05:00
Simon Glass
d6b318de2f Convert CONFIG_TIMESTAMP to Kconfig
This converts the following to Kconfig:
   CONFIG_TIMESTAMP

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-21 14:01:34 -05:00
Tom Rini
2d7a463e82 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- fdt_support: Add fdt_for_each_node_by_compatible() helper macro
  (Marek)
- turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali)
- pci_mvebu: Add support for Kirkwood PCIe controllers (Pali)
- SPL: More verifications for kwbimage in SPL (Pali)
- mvebu: Remove comphy_update_map() (Pali)
- Minor misc stuff
2022-01-20 12:40:20 -05:00
Tom Rini
280db76f15 Pull request doc-2022-04-rc1
Replace @return by Return: in code comments.
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Merge tag 'doc-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request doc-2022-04-rc1

Replace @return by Return: in code comments.
2022-01-20 09:39:45 -05:00
Marek Behún
0d582a461e arm: mvebu: spl: Fix 100 column exceeds
Fix 100 column exceeds in arch/arm/mach-mvebu/spl.c.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
37241ce1ba arm: mvebu: spl: Use IS_ENABLED() instead of #ifdef where possible
Use the preferred
  if (IS_ENABLED(X))
instead of
  #ifdef X
where possible.

There are still places where this is not possible or is more complicated
to convert in this file. Leave those be for now.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
c894566c5d arm: mvebu: spl: Use preferred types u8/u16/u32 instead of uintN_t
Checkpatch warns about using uint32/16/8_t instead of u32/16/8.

Use the preferred types.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
62ee75a30d arm: mvebu: spl: Print srcaddr in error message
Print the wrong srcaddr (spl_image->offset) in error message also for
SATA case.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
402e84ee88 arm: mvebu: Check for kwbimage data checksum
Last 4 bytes of kwbimage boot image is checksum. Verify it via the new
spl_check_board_image() function which is called by U-Boot SPL after
loading kwbimage.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
f830703f42 arm: mvebu: Check that kwbimage blockid matches boot mode
Each boot mode has its own kwbimage specified by blockid. So check that
kwbimage is valid by blockid.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
2e0429bcc1 SPL: Add struct spl_boot_device parameter into spl_parse_board_header()
Add parameter spl_boot_device to spl_parse_board_header(), which allows
the implementations to see from which device we are booting and do
boot-device-specific checks of the image header.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
66f874855c arm: mvebu: Check that kwbimage offset and blocksize are valid
There are certain restrictions for kwbimage offset and blocksize.
Validate them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
4364071362 pci: pci_mvebu: Add support for Kirkwood PCIe controllers
Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base
address of PCIe mappings. Size of PCIe windows is not defined in any macro
yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE
macros.

Kirkwood arch code already maps mbus windows for io and mem, so avoid
calling mvebu_mbus_add_window_by_id() function which would try to do
duplicate window mapping.

Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible
string, so mark pci_mvebu.c driver as compatible for it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
3058e283b8 fdt_support: Add fdt_for_each_node_by_compatible() helper macro
Add macro fdt_for_each_node_by_compatible() to allow iterating over
fdt nodes by compatible string.

Convert various usages of
    off = fdt_node_offset_by_compatible(fdt, start, compat);
    while (off > 0) {
        code();
        off = fdt_node_offset_by_compatible(fdt, off, compat);
    }
and similar, to
    fdt_for_each_node_by_compatible(off, fdt, start, compat)
        code();

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-20 11:35:29 +01:00
Heinrich Schuchardt
185f812c41 doc: replace @return by Return:
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 18:11:34 +01:00
Tom Rini
068415eade Xilinx changes for v2022.04-rc1
gpio:
 - Add modepin driver
 
 net:
 - Save random mac addresses to eth variable
 
 zynqmp gem:
 - Add support for mdio bus DT description
 - Add support for reset and SGMII phy configuration
 - Reduce timeout for MDIO accesses
 
 zynqmp clk:
 - Fix clock handling for gem and usb
 
 phy:
 - Add zynqmp phy/serdes driver
 
 serial:
 - Add one missing compatible string
 
 microblaze:
 - Symbol alignement
 - SPL fixups
 - Code cleanups
 
 zynqmp:
 - Various dt changes, DP pre-reloc, gem resets, gem clocks
 - Switch SOM to shared psu configuration
 - Move dcache handling to firmware driver
 - Workaround gmii2rgmii DT description issue
 - Enable broadcasts again
 - Change firmware enablement logic
 - Small adjustement in firmware driver
 
 versal:
 - Support new mmc@ DT nodes
 - Fix run time variable handling
 - Add missing I2C_PMC ID for power domain
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Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc1

gpio:
- Add modepin driver

net:
- Save random mac addresses to eth variable

zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses

zynqmp clk:
- Fix clock handling for gem and usb

phy:
- Add zynqmp phy/serdes driver

serial:
- Add one missing compatible string

microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups

zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver

versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
2022-01-19 11:43:44 -05:00
Heinrich Schuchardt
d3adee1db8 sandbox: imply PARTITION_TYPE_GUID
CONFIG_PARTITION_TYPE_GUID=y is needed for testing some GPT related
functionality.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 16:16:33 +01:00
Tom Rini
b24b201b60 Merge https://source.denx.de/u-boot/custodians/u-boot-samsung
- Updates for a{3,7}y17lte platforms
2022-01-19 08:09:34 -05:00
Michal Simek
71efd45a5f arm64: zynqmp: Change firmware dependency
In case of mini U-Boot configurations there is no need to enable firmware
driver which just consume space for nothing. That's why add an option to
disable it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d439399160ff3374f2b39f54f7dd70fa8c8bfea0.1642162121.git.michal.simek@xilinx.com
2022-01-19 11:36:11 +01:00
Shravya Kumbham
d10807a06b arm64: xilinx: dts: Add dma properties to fix dtbs_check warnings
Update dma name and add #dma-cells properties to fix dtbs_check
warnings.

Signed-off-by: Shravya Kumbham <shravya.kumbham@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/fedbf83fd5c682b4d61905d2cb790d33c2f079d6.1642160644.git.michal.simek@xilinx.com
2022-01-19 11:33:50 +01:00
Manish Narani
1d70cc7789 arm64: zynqmp: Update USB node handle from dwc3 to usb
The DWC3 bindings require all USB node handles to be '^usb@[0-9a-f]+$'.
Update the same in ZynqMP device tree.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/26fc2777eeb92cb5cb1d558d7c19cfb54ac42d0c.1642160613.git.michal.simek@xilinx.com
2022-01-19 11:33:03 +01:00
Michal Simek
59b21d2aea arm64: zynqmp: Change compatible strings for cadence uart
Based on Linux kernel DT binding there should be different compatible
strings used that's why align zynqmp.dtsi with it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/e2404ccd22fd97fe6020be0b3b6eb3c8677f55b0.1642160583.git.michal.simek@xilinx.com
2022-01-19 11:25:54 +01:00
Dylan Hung
abc75897ca ARM: dts: ast2600: Add MDIO devices
There are 4 MDIO bus controllers in AST2600 SOC.  Each of them can
connect to one or more PHY chips and is flexible to work with the 4 MAC
devices in AST2600.  On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY
chips used by MAC 0,1,2,3 respectively.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
3739cd58a4 ARM: dts: s700: add MMC/SD controller node
This patch adds node for mmc/sd controller found on Action Semi OWL
S700 SoC.

Since, upstream Linux binding has not been merged for S700 MMC/SD
controller, Changes are put in u-boot specific dtsi file.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
a7e7baea0a ARM: dts: sync Actions Semi S700 DT from Linux v5.16-rc3
This Synchronizes the Actions Semi S700 SoC DT changes from
commit "g58e1100fdc59" ("Linux v5.16-rc3").

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18 12:48:17 -05:00
Ovidiu Panait
2fd81be11c common: board_r: move init_addr_map() to init.h
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because
the header is only present on arm and powerpc. In order to remove the
dependency on this header and the associated ifdef, move init_addr_map()
declaration to init.h, since it is only called during the common init
sequence.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18 08:31:02 -05:00
Ovidiu Panait
1b212bb9f4 common: board_r: drop initr_addr_map wrapper
Add a return value to init_addr_map and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18 08:31:02 -05:00
Ovidiu Panait
485c90c06b common: remove bedbug debugger support
Commit 98f705c9ce ("powerpc: remove 4xx support") removed (in 2017) the
last code that made use of bedbug debugger support. Since there aren't
any boards left that define either CONFIG_CMD_BEDBUG or a real
bedbug_init(), drop this feature from u-boot.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-18 08:31:02 -05:00
Ovidiu Panait
027b0e9c16 common: spl: move armv7m-specific code to spl_perform_fixups()
Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board
specific function designed for this purpose.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18 08:31:02 -05:00
Tom Rini
4e81f3be34 Merge branch '2022-01-15-TI-platform-updates'
- Let am335x_evm use the CPSW or PRUSS ethernet.
- Implement timer_get_boot_us in the omap timer driver
- gpmc bitflip, QSPI clock calculation on am437x, da8xx_gpio bugfixes
- Assorted K3 updates
2022-01-17 11:24:43 -05:00
Tom Rini
6d2ebcd7be Second set of u-boot-at91 features for the 2022.04 cycle
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Merge tag 'u-boot-at91-2022.04-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2022.04 cycle:

This small feature set includes few changes for sama7g5 and sama7g5ek:
turn blue led on at boot, changes required for the Rev4 of the board,
better sync with the Linux DT with regards to the new DT nodes.
2022-01-17 08:36:12 -05:00
Eugen Hristev
e92ebf9f25 ARM: dts: at91: sama7g5ek: move eeproms to flexcom8
The rev4 of the board sama7g5ek has the eeproms on flexcom8 instead of
flexcom1.
Initialize flexcom8 with required pincontrol and move the eeproms accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-17 11:18:39 +02:00
Eugen Hristev
4727f954a4 ARM: dts: at91: sama7g5: add flx8 and required nodes
Add Flexcom8 node with required referenced nodes as phandles.
Since Flexcom8 is present in Linux, take the node exactly as-is from Linux.
Some nodes are referenced in Linux as phandles, the dma and the gic.
Add them as well to the file, even if they are unused by Uboot.
This is a step towards having the U-boot DT equivalent with the DT in Linux.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-17 11:18:39 +02:00
Mark Kettenis
97187d5e37 power: domain: Add Apple pmgr driver
This driver supports power domains for the power management
controller found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:01 +09:00
Mark Kettenis
6034c9140f arm: dts: apple: Add u-boot,dm-pre-reloc properties
These are necessary to make sure the power domains needed for the
serial console are availble in the pre-relocation phase.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:00 +09:00
Mark Kettenis
c918e2c303 arm: dts: apple: Update Apple M1 device trees
This synchronizes the device trees with those that are in the
process of being upstreamed into Linux. This is mostly the
current state of the device trees on the asahilinux branch
with a few extra bits used by OpenBSD. This includes device
trees for machines that were still missing.

There are still some differences that will hopefully be resolved
soon.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:00 +09:00
Vignesh Raghavendra
ef7be5a07b ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL
Enable Second Ethernet port on which ROM support Ethboot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 21:44:50 -05:00
Vignesh Raghavendra
07252f5c71 mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC
This is required to enables spl_net boot on AM64x

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
93c43a8365 mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
e58d928485 mach-k3: common: Instantiate AM65 CPSW NUSS wrapper
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver
is enabled. Since driver is modeled as UCLASS_MISC, we need to
explicitly probe the driver. Use common misc_init_r() that entire
K3 family of SoCs.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
584216315d ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmode
In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed
in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image
directly on OSPI flash via MMIO window. So, copy the image to internal
on-chip RAM before parsing the image.

Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform
and thus cannot reside in OSPI/xSPI and needs to be copied over to
internal OCRAM.

This unblocks OSPI/xSPI boot on HS platforms

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-01-15 10:38:26 -05:00
Michael Liebert
67c8678346 arm: mach-k3: am642_init: Unlock MCU PADCFG regs
Currently only the PADCFG registers of the main domain are unlocked.
Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be configured by u-boot or Linux.

Signed-off-by: Michael Liebert <liebert@ibv-augsburg.de>
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Nishanth Menon <nm@ti.com>
2022-01-15 10:38:26 -05:00
Tom Rini
d71dbe657c Pull request for efi-2022-04-rc1
Documentation:
 
 * Fix building HTML documentation of readthedocs.io
 * Add ARM Juno board documentation
 * Build requirements for Alpine Linux
 * Include DM headers in API documentation
 
 UEFI:
 
 * Fix section alignment of EFI binaries
 * Fix header length of RISC-V EFI binaries allowing to run them on EDK II
 * Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided
 
 Other:
 
 * Let 'part list' show all 128 GPT partitions
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Merge tag 'efi-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-04-rc1

Documentation:

* Fix building HTML documentation of readthedocs.io
* Add ARM Juno board documentation
* Build requirements for Alpine Linux
* Include DM headers in API documentation

UEFI:

* Fix section alignment of EFI binaries
* Fix header length of RISC-V EFI binaries allowing to run them on EDK II
* Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided

Other:

* Let 'part list' show all 128 GPT partitions
2022-01-15 07:39:09 -05:00
Simon Glass
081dfcf783 x86: efi: Set the correct link flags for the 64-bit EFI app
At present some 32-bit settings are used with the 64-bit app. Fix this by
separating out the two cases.

Be careful not to break the 64-bit payload, which needs to build a 64-bit
EFI stub with a 32-bit U-Boot.

Signed-off-by: Christian Melki <christian.melki@t2data.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Simon Glass
59e8f36dd9 x86: efi: Don't use the 64-bit link script for the EFI app
That script is not intended for use with EFI, so update the logic to avoid
using it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Christian Melki <christian.melki@t2data.com>
2022-01-15 10:57:22 +01:00
Simon Glass
3b4ae096b0 x86: efi: Round out the link script for 64-bit EFI
Make sure the linker lists are in the right place and drop the eh_frame
section, which is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Simon Glass
450ce56a11 x86: efi: Tweak the code used for the 64-bit EFI app
Add an empty CPU init function to avoid fiddling with low-level CPU
features in the app. Set up the C runtime correctly for 64-bit use
and avoid clearing BSS, since this is done by EFI when U-Boot is loaded.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Simon Glass
ce1dc0cc17 x86: efi: Update efi_get_next_mem_desc() to avoid needing a map
At present this function requires a pointer to struct efi_entry_memmap
but the only field used in there is the desc_size. We want to be able
to use it from the app, so update it to use desc_size directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Heinrich Schuchardt
9ef5ccaa71 efi_loader: fix SectionAlignment, FileAlignment
The alignment of sections in the EFI binaries generated by U-Boot is
incorrect.

According to the PE-COFF specification [1] the minimum value for
FileAlignment is 512. If the value of SectionAlignment is
less then the page size, it must equal FileAlignment.

Let's set both values to 512 for the ARM and RISC-V architectures.

[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-15 10:57:22 +01:00
Heinrich Schuchardt
dfbc2be47e riscv: revert Complete efi header for RV32/64
EDK II refuses to load the EFI binaries created by U-Boot.
The reason is an incorrect PE-COFF header. The number of
data directories does not match NumberOfRvaAndSizes.
This leads to a failed consistency check in
PeCoffLoaderGetPeHeader():

    SizeOfOptionalHeader - HeaderWithoutDataDir) !=
    NumberOfRvaAndSizes * sizeof(DATA_DIRECTORY))

Fixes: 9afaeec6ef ("riscv: Complete efi header for RV32/64")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-15 10:57:21 +01:00
Mark Kettenis
3cdfa312c6 armv8: apple: Disable PSCI reset
Apple's ARMv8 cores don't implement EL3 and therefore don't
provide a PSCI implementation.  So don't attempt to use
PSCI to reset on machines using Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2022-01-14 13:16:11 -05:00
Pali Rohár
18d85d6e8a arm: mvebu: Enable BootROM output on A38x
BootROMs on pre-A38x SoCs enabled its output on UART by default, but A38x'
BootROM has its output on UART disabled by default.

To enable BootROM output on A38x SoC, it is required to set DEBUG flag
(which only enables BootROM output and nothing more) in kwbimage. For UART
images this DEBUG flag is ignored by BootROM.

Enable kwbimage DEBUG flag for all A38x boards.

With this change BootROM prints the following (success) information on UART
before booting U-Boot kwbimage:

  BootROM - 1.73
  Booting from SPI flash

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pali Rohár
a2b1db41cf arm: mvebu: Correctly set LOAD_ADDRESS for U-Boot SPL binary in kwbimage
U-Boot SPL for mvebu platform is not compiled as position independent.
Therefore it is required to instruct BootROM to load U-Boot SPL at the
correct address. Loading of kwbimage binary code at specific address can be
now achieved by the new LOAD_ADDRESS token as part of BINARY command in
kwbimage config file.

Update mvebu Makefile to put value of $(CONFIG_SPL_TEXT_BASE) into
LOAD_ADDRESS token when generating kwbimage.cfg from kwbimage.cfg.in.

It is required to update regex for sed to find replacement tokens at any
position on a line in kwbimage config file and not only at the beginning of
the line. This is because LOAD_ADDRESS is specified at the end of line
containing the BINARY command.

It looks like all Armada boards set CONFIG_SPL_TEXT_BASE to value
0x40004030 or 0x40000030. Why this value? It is because main kwbimage
header is at address 0x40004030 or 0x40000000 and it is 32 bytes long.
After the main header there is the binary header, which consist of 1 byte
for type, 3 bytes for size, 1 byte for number of arguments, 3 reserved
bytes and then 4 bytes for each argument. After these arguments comes the
executable code.

So arguments start at address 0x40004028 or 0x40000028. Before commit
e6571f38c9 ("arm: mvebu: Remove dummy BIN header arguments for SPL
binary") there were two (dummy) arguments, which resulted in load address
of 0x40004030 or 0x40000030, always. After that commit (which removed dummy
arguments), load address stayed same due to the 128-bit alignment done by
mkimage.

This patch now reflects the dependency between $(CONFIG_SPL_TEXT_BASE),
load address and dummy kwbimage arguments, and allows the user to adjust
$(CONFIG_SPL_TEXT_BASE) config option to some other value.

For unsupported values, when mkimage/kwbimage cannot set chosen load address
as specified by $(CONFIG_SPL_TEXT_BASE), the build process now fails,
instead of silently generating non-working kwbimage.

Removal of this alignment between $(CONFIG_SPL_TEXT_BASE) and LOAD_ADDRESS
can only be done by compiling U-Boot SPL as position independent. But this
currently is not possible for 32-bit ARM version of U-Boot SPL.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pali Rohár
29c6a9c763 arm: mvebu: Set CPU for U-Boot SPL binary in kwbimage
kwbimage needs to know CPU type, so set it in kwbimage config file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pali Rohár
6329d4402e arm: mvebu: Generate kwbimage.cfg with $(call cmd, ...)
Usage of $(call cmd,...) is standard way to call other commands which
generate things.

It also has the advantage of printing build information in the form
  KWBCFG  arch/arm/mach-mvebu/kwbimage.cfg
if verbosity is disabled, and printing the build command otherwise.

Note that the '#' character needs to be escaped in Makefile when used as
value for make variable assignment.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pierre Bourdon
c03f4da187 mtd: nand: pxa3xx: use marvell, prefix for custom DT properties
The DT properties for the "enable-arbiter" and "keep-config" config
knobs were previously named inconsistently:

- The u-boot driver used "nand-enable-arbiter" and "nand-keep-config"
  names, without Marvell prefixes.

- The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter"
  does not exist anymore in recent kernels, but it also used to be
  "marvell,nand-enable-arbiter").

- The device trees almost all use "marvell," prefixed names, except for
  one single instance of "nand-enable-arbiter" without vendor prefix.

This commit standardizes on the vendor prefixed version, making the
u-boot driver read from DT props "marvell,nand-enable-arbiter" and
"marvell,nand-keep-config". The one device tree using the unprefixed
version is also changed to use the new naming.

This has the side effect of making the previously no-op "marvell,"
config knobs already present in some DTs actually do something. This was
likely the original intention of the DT authors, but note that this
commit was not tested on every single impacted board.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
2022-01-14 07:47:57 +01:00
Pali Rohár
94c30f9c8f arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.

Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.

Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.

Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.

This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
35e29e89a3 arm: mvebu: Implement simple mvebu-reset driver for enabling/disabling PCIe ports
Enabling and disabling PCIe ports is done via address space of system
controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register
for enabling and disabling some or more PCIe ports. Correct mapping needs
to be set in particular DTS files.

DT API for mvebu-reset is prepared for implementing resets also for other
HW blocks, but currently only PCIe is implemented via index 0.

Currently this driver is not used as PCIe ports are automatically enabled
by SerDes code executed by U-Boot SPL. But this will change in followup
patches.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
537b0142b0 pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.

Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
and IO ranges. Previously these macros covered only address ranges for the
first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.

Function resource_size() returns zero when start address is 0 and end
address is -1. So set invalid resources to these values to indicate that
resource has no mapping.

Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
into PCIe ports in mvebu_pcie_bind() function which allocates per-port
based struct mvebu_pcie, instead of using global state variables
mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
independent of global static variables (which store the state of
allocation) and allows to bind and unbind the driver more times.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
2022-01-14 07:47:57 +01:00
Pali Rohár
8f9e0f4d20 arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT
The only user of board_pex_config() weak function is A385 controlcenterdc
board. It looks like that code in its board_pex_config() function needs to
be executed after PCIe link is up. Therefore put this code into
spl_board_init() function which is called after a38x serdes initialization,
and therefore it is after the serdes hws_pex_config() function finishes
(which is the state before this change).

With this change completely remove board_pex_config() function as it is not
used anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Simon Glass
7f3b79af54 bloblist: Rename the SPL tag
Add a U_BOOT prefix to this tag since it is specific to the U-Boot
project.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Heinrich Schuchardt
880dbc5f80 sandbox: compatibility of os_get_filesize()
U-Boot define loff_t as long long. But the header
/usr/include/linux/types.h may not define it.
This has lead to a build error on Alpine Linux.

So let's use long long instead of loff_t for
the size parameter of function os_get_filesize().

Reported-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Tom Rini
743c562d0c Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Add Apple M1 watchdog timer (Mark)
2022-01-13 08:00:02 -05:00
Vagrant Cascadian
d1cab4f5f0 arch/arm/mach-keystone/ddr3.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
9413e3a175 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c: Fix spelling of "resetting". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
11872975fd arch/arm/mach-bcm283x/msg.c: Fix spelling of "Failed". 2022-01-13 07:57:49 -05:00
Mark Kettenis
9a8e3736da arm: apple: Use watchdog timer for system reset
Rely on the new watchdog timer driver and the sysreset uclass to
reset the system.  This gets rid of hard-coded addresses and
should work on systems based on the new M1 Pro and M1 Max SoCs
as well.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
2022-01-13 06:55:46 +01:00
Mark Kettenis
b0e6c73a79 arm: dts: apple: Add watchdog timer node
Add a node for the watchdog timer based on the proposed Linux
device tree bindings.

Remove the old reboot node which was a watchdog timert node in
disguise using a preliminary device tree binding.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
2022-01-13 06:55:46 +01:00
Henrik Grimler
00809bd4e9 board: samsung: fix menu entries for a{3,7}y17lte
a7y17lte is called SM-A720F, and a3y17lte SM-A320F.  a3y17lte also
should select PINCTRL_EXYNOS78x0, not the (non-existent)
PINCTRL_EXYNOS7880, and it has an Exynos 7870 SoC and not 7880.

Fixes: 3e2095e960 ("board: samsung: add support for Galaxy A series
of 2017 (a5y17lte)")
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2022-01-13 14:33:00 +09:00
Pali Rohár
c49f1fa892 m68k: mcf5445x: pci: Use PCI_CONF1_ADDRESS() macro
mcf5445x platform uses standard format of Config Address for PCI
Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
7598759d19 x86: pci: Use PCI_CONF1_ADDRESS() macro
x86 platform uses standard format of Config Address for PCI Configuration
Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Tom Rini
fe04d885fb Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-01-10 14:01:57 -05:00
Tom Rini
0dadad6d7c - disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
 - add changes to support VIM3/L android boot by using meson64_android.h config
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Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next

- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
2022-01-09 07:56:31 -05:00
Patrick Wildt
b05cebb5f2 imx8mq: Generate a single bootable flash.bin again
All i.MX8MQ boards have been converted to binman, which makes it
necessary to flash both flash.bin and u-boot.itb to get a bootable
system. Prior to the conversion, only flash.bin was needed.

Such new requirement breaks existing distro mechanisms to generate the
final binary because the extra u-boot.itb is now required.

Generate a final flash.bin that can be used again as a single bootable
binary to keep the original behavior.

After this change the SPL binary is called spl.bin, which is a more
descriptive name for its purpose, and can still be used standalone (for
example, for secure boot purposes).

Also update imx8mq_evk.rst to remove the u-boot.itb copy step.

This is a cherry-pick of 028abfd9b1 ("imx8mm-evk: Generate a single
bootable flash.bin again") adjusted to apply to i.MX8MQ.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-01-08 11:16:03 -05:00
Fabio Estevam
7ad0cee754 udoo: Select CMD_DM
CMD_DM is useful for showing the whole DM tree.

Enable it via "imply CMD_DM".

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
2022-01-08 11:16:03 -05:00
Fabio Estevam
6869bab6a1 ARM: dts: imx6qdl-udoo: Properly describe the SD card detect
GPIO7_IO00 is used as SD card detect.

Properly describe this in the devicetree.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2022-01-08 11:16:03 -05:00
Adam Ford
c225601c60 imx: imx8mm: imx8mm-kontron-n801x-s: Fix binman error
The binman node is part of the imx8mm-u-boot.dtsi file which
is duplicated in imx8mm-kontron-n801x-s-u-boot.dtsi and causes
a build error.  Remove the duplicate.

Fixes: 3cbb31f0e848 ("arm64: dts: imx8mm: use common binman configuration")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 17:38:01 -05:00
Adam Ford
83514ca08b board: phytec: imx8mm-phycore: Remove duplicate binman node
The binman node is part of the imx8mm-u-boot.dtsi file which
is duplicated in phycore-imx8mm-u-boot.dtsi and causes a build
error.  Remove the duplicate.

Fixes: 3cbb31f0e848 ("arm64: dts: imx8mm: use common binman configuration")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 17:38:01 -05:00
Tim Harvey
7d926c9544 imx8mm_venice: switch to use binman to pack images
Use binman to pack images.

Note that imx8mm_venice supports several boards via multiple DTB's thus
in the fit node we must use:
- fit,fdt-list = "of-list"
- fdt-SEQ
- config-SEQ

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 15:49:13 -05:00
Marcel Ziswiler
f17fb6cae4 arm64: dts: imx8mm-u-boot.dtsi: improve odd blob-ext naming
Rather than using odd implicit blob-ext naming, explicitly specify the
type to be of blob-ext and therefore also simplify the node naming.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
86b7f2069c arm64: dts: imx8mm-u-boot.dtsi: explicitly add spl filename
Explicitly add SPL aka u-boot-spl.bin filename.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
f08c3fee57 arm64: dts: imx8mm-u-boot.dtsi: alphabetically re-order properties
Alphabetically re-order properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
7cf5597b84 arm64: dts: imx8mm: use common binman configuration
With the move to using binman to generate SPL aka u-boot-spl-ddr.bin and
U-Boot proper aka u-boot.itb every board now covers such configuration
in its own U-Boot specific device tree include. Move the comon part of
that configuration to the common imx8mm-u-boot.dtsi include file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
e9c63ab0e3 arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: use common imx8mm-u-boot.dtsi
Use common imx8mm-u-boot.dtsi.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
2dc3ac5772 arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: alphabetically re-order
Alphabetically re-order nodes and properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Peng Fan
ea6ad1a42a imx: imx8mq use common imximage.cfg
After all these board switch to binman, we could use common imximage.cfg

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
2022-01-07 15:42:41 -05:00
Peng Fan
ddc890bc7e imx: pico-imx8mq: switch to use binman
Switch to use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
2022-01-07 15:42:41 -05:00
Peng Fan
f7f70ea216 imx: imx8mq_phanbell: switch to binman
Switch to binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
2022-01-07 15:42:41 -05:00
Peng Fan
c1ecd03d90 imx: imx8mq_evk: switch to binman
Switch to use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:41 -05:00
Adam Ford
2baacc75a5 imx8mn_beacon: Fix booting hang and switch to binman
Somewhere along the line, the board stopped being able to boot.
Rather than just fixing the issue, let's fix the issue and migrate
to binman to eliminate a warning when using custom imx tools for
generating the binary.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 15:41:58 -05:00
Adam Ford
80efad1342 imx8mm_beacon: Switch to binman for generating image
To eliminate a warning when using custom imx tools for generating
a binary, use binman to generate flash.bin.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-07 12:10:59 -05:00
Peter Robinson
2bbe1ba0c7 udoo_neo: Fixes for booting from the mSD card
This fixes booting from the mSD card from both SPL and when
using it for the OS booting. It also cleans up a few mmc
booting bits that are no longer needed.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 09:30:44 -05:00
Ovidiu Panait
fc7220f0c4 microblaze: branch to base vector address on reset
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze using the
CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the
reset routines to branch to this location instead.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
f149ee4c36 microblaze: start.S: add support for configurable vector base address
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze, so update the
__setup_exceptions routine to work with any vector base address.

The r4 register is reserved for the vector base address inside
__setup_exceptions and the function prologe/epilogue are also updated to
save and restore r4.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-9-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
83b175be16 microblaze: migrate CONFIG_SYS_USR_EXCEP to Kconfig
Migrate CONFIG_SYS_USR_EXCEP to Kconfig. Also, rename it to
XILINX_MICROBLAZE0_USR_EXCEP in order to match the naming convention of
microblaze-generic Kconfig options.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-7-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
70c68712ef microblaze: drop CONFIG_SYS_RESET_ADDRESS macro
Microblaze is one the last two users of the CONFIG_SYS_RESET_ADDRESS
macro (the other is arch/powerpc/cpu/mpc8xx/cpu.c, but the macro is not
defined anywhere in powerpc code, so it should be removed there too).

Replace CONFIG_SYS_RESET_ADDRESS usage in start.S with
CONFIG_SYS_TEXT_BASE. If the reset address should really be
user-configurable, a new Kconfig option could be added.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
48039c333f microblaze: start.S: use stack space as scratch memory for endian offset
To simpify the code, use stack space as scratch memory for endian offset
calculation, rather than saving/restoring the first unused MB vector.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-5-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
7a971dfbeb microblaze: Kconfig: SPL dependencies fixup
Enable SPL_LIBCOMMON_SUPPORT and SPL_LIBGENERIC_SUPPORT if CONFIG_SPL=y, in
order to fix the following link failures:
common/spl/spl.o: in function `board_init_r':
common/spl/spl.c:755: undefined reference to `puts'
...
common/spl/spl.o: in function `board_init_r':
common/spl/spl.c:756: undefined reference to `hang'
common/spl/spl.c:740: undefined reference to `memset'

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-4-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
b3fe1e8ff3 microblaze: spl: add board_boot_order() implementation
Microblaze has three boot modes defined in microblaze/include/asm/spl.h,
but only booting from NOR flash is currently useable. Add a custom
board_boot_order() implementation so that RAM and SPI boot modes can also
be selected if the corresponding load-image support is present.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-3-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:02 +01:00
Ovidiu Panait
edf0f9b15e microblaze: u-boot.lds: replace __end symbol with _end
board_fdt_blob_setup() uses the _end symbol to find the dtb in the non-spl
case. In order to allow microblaze builds to compile successfully with
CONFIG_OF_SEPARATE, the _end symbol must be defined. Align microblaze with
the other architectures and use _end symbol rather than __end to mark the
end of the u-boot binary.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-2-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:02 +01:00
Michal Simek
ca44216941 arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi
Remove clock-names from GEM nodes from clk-ccf because they should be only
present in zynqmp.dtsi. And as is visible both clock-names defined didn't
really match.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
87b50f9aea arm64: zynqmp: Add resets to all GEMs
There is a need to get IP out of reset to operate properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/041362197e8de8e9c696da64429107505bdc0c73.1637239345.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
19645a11de arm64: zynqmp: Add u-boot,dm-pre-reloc to dpsub node
u-boot,dm-pre-reloc is necessary for DP driver to allocate enough space for
framebuffer before relocation.
Power domain driver is called when video console is used for example by
loading BMP image.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5e93acee1746913a6e42741e5e797f0b4ab98d44.1637239230.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
T Karthik Reddy
3b441cf4e4 zynqmp: gpio: Add support for zynqmp gpio modepin driver
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Tom Rini
5fec3c853d Pull request of efi-next
Documentation:
 
 * Add Sunxi board description
 
 UEFI:
 
 * Improvements to U-Boot running on top of UEFI
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Merge tag 'efi-next' of https://source.denx.de/u-boot/custodians/u-boot-efi into next

Pull request of efi-next

Documentation:

* Add Sunxi board description

UEFI:

* Improvements to U-Boot running on top of UEFI
2021-12-31 07:28:36 -05:00
Simon Glass
40b172314b x86: efi: Show the system-table revision
Show the revision of this table as it can be important.

Also update the 'efi table' entry to show the actual address of the EFI
table rather than our table that points to it. This saves a step and the
intermediate table has nothing else in it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 07:34:34 +01:00
Simon Glass
7f5419a647 x86: efi: Add room for the binman definition in the dtb
At present only 4KB of spare space is left in the DTB when building the
EFI app. Increase this to 32KB so there is plenty of space to insert the
binman definition. This cannot be expanded later (as with OF_SEPARATE)
because the ELF image has already been built.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviwed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 06:45:01 +01:00
Simon Glass
440c6645aa x86: Don't process the kernel command line unless enabled
If the 'bootm' command is not enabled then this code is not available and
this causes a link error. Fix it.

Note that for the EFI app, there is no indication of missing code. It just
hangs!

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 06:45:01 +01:00
Simon Glass
6e7ad4a45f x86: Allow booting a kernel from the EFI app
At present this is disabled, but it should work so long as the kernel does
not need EFI services. Enable it and add a note about remaining work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-31 06:45:01 +01:00
Tom Rini
87a9aa604d - various fixes to the sandbox display support
- support for showing a logo without splash screen config
 - support for BMP drawing to depths other than 16bpp
 - tests for the different types of supported BMP images
 - support showing a logo when running coreboot via qemu
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Merge tag 'video-next-20211228' of https://source.denx.de/u-boot/custodians/u-boot-video into next

- various fixes to the sandbox display support
- support for showing a logo without splash screen config
- support for BMP drawing to depths other than 16bpp
- tests for the different types of supported BMP images
- support showing a logo when running coreboot via qemu
2021-12-28 11:28:31 -05:00
Tom Rini
440c00de69 Convert CONFIG_SYS_KWD_CONFIG to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_KWD_CONFIG

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
f98b3be287 Convert CONFIG_88F5182 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_88F5182
   CONFIG_BOARD_IS_OPENRD_BASE
   CONFIG_BOARD_IS_OPENRD_CLIENT
   CONFIG_BOARD_IS_OPENRD_ULTIMATE
   CONFIG_D2NET_V2
   CONFIG_FEROCEON
   CONFIG_FEROCEON_88FR131
   CONFIG_INETSPACE_V2
   CONFIG_KW88F6192
   CONFIG_KW88F6281
   CONFIG_KW88F6702
   CONFIG_NET2BIG_V2
   CONFIG_NETSPACE_LITE_V2
   CONFIG_NETSPACE_MAX_V2
   CONFIG_NETSPACE_MINI_V2
   CONFIG_NETSPACE_V2
   CONFIG_SHEEVA_88SV131

At this point mv-plug-common.h is now only an include of mv-common.h so
remove that indirection.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
e7b7c6761a Convert CONFIG_CPU_FREQ_HZ to Kconfig
This converts the following to Kconfig:
   CONFIG_CPU_FREQ_HZ

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
855e76b5cb Convert CONFIG_CPU_SH7751 to Kconfig
This converts the following to Kconfig:
   CONFIG_CPU_SH7751

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
3aca2b6bd7 Convert CONFIG_CPU_PXA27X to Kconfig
This converts the following to Kconfig:
   CONFIG_CPU_PXA27X

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
3569ac7afa ppc: mpc83xx: Remove unused CONFIG symbols
Neither of these symbols are referenced anywhere else, so remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
86e4c4f7b3 Convert CONFIG_83XX_PCICLK to Kconfig
This converts the following to Kconfig:
   CONFIG_83XX_PCICLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
2f8a6db5d8 Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig
In order to finish moving this symbol to Kconfig for all platforms, we
need to do a few more things.  First, for all platforms that define this
to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to
CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h.  This entails
also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk()
and updating a few preprocessor tests.

With that done, all platforms that define a value here can be converted
to Kconfig, and a fall-back of zero is sufficiently safe to use (and
what is used today in cases where code may or may not have this
available).  Make sure that code which calls this function includes
<clock_legacy.h> to get the prototype.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
e4c3ce7e28 CONFIG_SYS_CLK_FREQ: Consistently be static or get_board_sys_clk()
This CONFIG option is used in one of two ways.  The first way is that it
is defined to a static value, of an unsigned long size.  The second way
is that it is defined to something, typically a function, to determine
this value at run time.

However, in a few cases that function returns a static value.  Change
that to using the static value directly.

In the case of using something at run time, convert everything to using
a function of the same name and prototype.  This will allow for further
cleanups.

Finally, we have a few cases where the function is just not used, so
drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
2196a4a7ef arm: s5pc1xx: Move CONFIG_SYS_CLK_FREQ_C1x0 out of CONFIG namespace
The values CONFIG_SYS_CLK_FREQ_C100 and CONFIG_SYS_CLK_FREQ_C110 are
only used in one place and not changed by the board config file.  Move
these out of the CONFIG namespace and in to the CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
ba1ed5b022 Convert CONFIG_ARCH_MAP_SYSMEM to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_MAP_SYSMEM

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
1b46518736 Convert CONFIG_TPL_TEXT_BASE to Kconfig
This converts the following to Kconfig:
   CONFIG_TPL_TEXT_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
ada261f19a Finish converting CONFIG_SYS_FSL_CLK to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_CLK

We move the exiting option to common/Kconfig near the other options to
control the contents of board_init_f() and note that this is a legacy
option.  We further restrict this to where the call is going to be
non-empty, for the SoCs that had only been using this for some
MMC-related clocks.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
7856cd5a6d Convert CONFIG_SYS_PCI_64BIT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_PCI_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:17 -05:00
Tom Rini
d06e4b7e25 Finish CONFIG_VID et al conversion to Kconfig
This converts the following to Kconfig:
   CONFIG_VID
   CONFIG_VOL_MONITOR_INA220
   CONFIG_VOL_MONITOR_IR36021_READ
   CONFIG_VOL_MONITOR_IR36021_SET
   CONFIG_VOL_MONITOR_LTC3882_READ
   CONFIG_VOL_MONITOR_LTC3882_SET

To finish this migration, we first need to introduce CONFIG_SPL_VID as
some platforms only use this code in full U-Boot while others use it in
SPL as well.  To make the Kconfig logic clearer, guard all of the
sub-options with a if VID || SPL_VID check.  Finally, add Kconfig
options for the remaining related options that did not previously have
one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
be7dbb60c5 Convert CONFIG_SYS_IMMR to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_IMMR

We do this by consolidating the SYS_IMMR options we have and providing
defaults.

We also, in the few places where M68K was also sharing code with these
platforms, define it within the file to CONFIG_SYS_MBAR to match usage.
This should be cleaned up longer term.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
3847ba94f0 Finish converting CONFIG_WATCHDOG, HW_WATCHDOG and WDT to Kconfig
Because of how these symbols work, and the remaining board config.h file
uses, we need to do these at the same time.  In some cases we just get
to move rather directly to the defconfigs.  A few cases require manual
intervention.

For the case of the eb_cpu5282 we need to select HW_WATCHDOG for the
target, given how it's implemented.

For the cases of m53menlo, dh_imx6, display5, and display5_factory we
disable SPL watchdog support as the particular combination of options
they want would require either more symbols or enabling SPL_DM.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
f76750d111 Convert CONFIG_CONS_INDEX et al to Kconfig
This converts the following to Kconfig:
   CONFIG_CONS_INDEX
   CONFIG_DEBUG_UART_CLOCK
   CONFIG_FSL_TZPC_BP147
   CONFIG_GENERIC_ATMEL_MCI
   CONFIG_IDENT_STRING
   CONFIG_LIBATA
   CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE
   CONFIG_LPC32XX_GPIO
   CONFIG_MP
   CONFIG_MPC8XXX_GPIO
   CONFIG_MTD_PARTITIONS
   CONFIG_MVGBE
   CONFIG_MXC_GPIO
   CONFIG_NR_DRAM_BANKS
   CONFIG_OF_BOARD_SETUP
   CONFIG_OF_STDOUT_VIA_ALIAS
   CONFIG_OF_SYSTEM_SETUP
   CONFIG_PREBOOT
   CONFIG_ROCKCHIP_SERIAL
   CONFIG_RTC_ENABLE_32KHZ_OUTPUT
   CONFIG_RTC_MV
   CONFIG_SCSI_AHCI
   CONFIG_SF_DEFAULT_BUS
   CONFIG_SF_DEFAULT_CS
   CONFIG_SF_DEFAULT_SPEED
   CONFIG_SOFT_SPI
   CONFIG_SPI_FLASH_EON
   CONFIG_SPI_FLASH_MACRONIX
   CONFIG_SPI_FLASH_MTD
   CONFIG_SPI_FLASH_SPANSION
   CONFIG_SPI_FLASH_SST
   CONFIG_SPI_FLASH_STMICRO
   CONFIG_SUPPORT_RAW_INITRD
   CONFIG_SYS_ARCH_TIMER
   CONFIG_SYS_BOARD
   CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
   CONFIG_SYS_DCACHE_OFF
   CONFIG_SYS_FDT_SAVE_ADDRESS
   CONFIG_SYS_FLASH_CFI
   CONFIG_SYS_FSL_ERRATUM_ESDHC135
   CONFIG_SYS_HAS_SERDES
   CONFIG_SYS_L2CACHE_OFF
   CONFIG_SYS_LITTLE_ENDIAN
   CONFIG_SYS_LOAD_ADDR
   CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
   CONFIG_SYS_NS16550
   CONFIG_SYS_PLLFIN
   CONFIG_SYS_SPI_U_BOOT_OFFS
   CONFIG_TIMER_SYS_TICK_CH
   CONFIG_USB_EHCI_FSL
   CONFIG_U_QE
   CONFIG_VERSION_VARIABLE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
98ab831da7 Convert CONFIG_FSL_IFC to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_IFC

This is done via select statements to match previous logic.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:40:33 -05:00
Simon Glass
8657ad43f3 sandbox: video: Add BMP tests for 32bpp and 8bpp modes
Add a few more tests for BMP rendering. Use a back door into the sandbox
SDL driver to adjust the resolution at runtime.

The truetype code does not support 8bpp. Add this so that the display is
not blank when running in this mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
250e735c69 video: sandbox: Avoid duplicate display windows
When unit tests are run they currently create a new window. Update the
code so that the old one is removed first. This avoids the confusion as to
which one is active.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
0fe5e9481e sandbox: video: Support 8bpp depth
At present sandbox only supports 16 and 32bpp depths, since those are the
easy ones with SDL.

We can support other depths by manually converting the pixel formats. Add
support for this, to enable an 8ppp (monochrome) format.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
John Keeping
eaee44aaaa rockchip: boot_mode: fix fastboot command
The USB controller index must be separated from the type argument,
otherwise the preboot command fails with the error:

	Error: Wrong USB controller index format

Add the missing space to fix fastboot mode here.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 15:17:51 +08:00
Jagan Teki
0ade02526b engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.

PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:56:58 +08:00
Jagan Teki
19a4d31c12 arm64: dts: rockchip: Sync px30 from linux-next
Sync the px30 devicetree files from linux-next tree.

commit <14ce8069f48b> ("lib/stackdepot: allow optional init and
stack_table allocation by kvmalloc() - fixup3")

Note, this path even sync rk3326 files as it depends on px30.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:56:58 +08:00
Jagan Teki
43419b936c arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi
dmc node is specific to U-Boot, it is always better practice
to maintain U-Boot specific nodes into -u-boot.dtsi files
in order to maintain Linux dts file sync compatibility.

Move the dmc into px30-u-boot.dtsi, also add dmc node
explicitly in rk3326-odroid-go2-u-boot.dtsi since it is
using px30.dts.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:56:58 +08:00
Yifeng Zhao
f8b36089af dts: rockchip: rk3399: enable emmc phy for spl
adapting commit ac804143cf ("mmc: rockchip_sdhci: add phy and clock
config for rk3399") to fix the issue "Not found emmc phy device".

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> - on a Rock960
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se> - on a Pinebook Pro
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:46:25 +08:00
Nico Cheng
ef7f43084f rockchip: rk3568: add arch_cpu_init()
We configured the drive strength and security of EMMC in
arch_cpu_init().

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 11:10:24 +08:00
Nico Cheng
6b97f2d0ed arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node
Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 11:10:24 +08:00
Nico Cheng
daec31e5cc rockchip: Kconfig: Enable SPL support for rk3568
Enable SPL support in Kconfig and add some related option in
rk3568_common.h

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 11:10:24 +08:00
Chris Morgan
b774be9de5 rockchip: px30: add support for HW RNG for Odroid Go Advance
The Odroid Go Advance has a hardware random number generator present.
The device does not have an upstream Linux driver, but does have a
U-Boot driver. Add the appropriate node so that the hardware RNG can be
used in U-Boot.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 10:58:59 +08:00
Simon Glass
239d22c795 fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD
Use this new Kconfig instead of OF_BOARD, so we know for sure which boards
obtain their devicetree from a prior stage. Leave sandbox alone since it
does not. Also don't touch xilinx_versal_virt since it does not have a
specific TARGET Kconfig.

This option implies OF_BOARD for now, but with future work standard
passage may be used instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add rpi_4_32b and rpi_arm64 to the list of boards converted]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-23 11:19:17 -05:00
Simon Glass
975e0e04bb arm: highbank: Add devicetree files
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
c4607665da arm: qemu-ppce500: Add a devicetree file
This uses QEMU virt which creates its own devicetree.

Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
142918807d arm: bcm7xxx: Add a devicetree file
Add an empty devicetree file for these boards. It seems to be possible to
obtain a real one from another bootloader called 'bolt' but I will leave
this to the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
50d857ebc4 arm: xilinx_versal_virt: Add a devicetree file
Add an empty file to prevent build errors when building with
CONFIG_OF_SEPARATE enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
56a47ba21b arm: octeontx: Add an empty devicetree file
Add an empty file to prevent build errors when building with
CONFIG_OF_SEPARATE enabled.

Unfortunately there are no build instructions in the U-Boot tree to enable
a real file to be created.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
e5e6cc7cfa arm: xenguest_arm64: Add a empty devicetree file
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

The real devicetree is created by the Xen project on-the-fly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
aa26948b58 arm: vexpress: Add a devicetree files for juno
Sync these file, obtained from Linux v5.15.

Add a note for the maintainer, and SPDX lines where they are missing.
The added lines are:

   SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause

Note, this matches the text in those files, but is not the same as the
GPL-2.0 of some files.

[1] https://releases.linaro.org/android/reference-lcr/juno/7.1-17.05/

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-23 10:24:39 -05:00
Simon Glass
9ae600e9e2 arm: rpi: Sync rpi dts files from Linux
Sync these files, obtained from Linux v5.15.

This adds a devicetree file for rpi_4 which was not there before.

Testing shows no change so far as I can see:
- boots to U-Boot prompt on rpi0, rpi2
- boots to distro on rpi3
- boots to distro on rpi4

I am assuming that syncing with Linux is safe, but the maintainer should
know for sure.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
4027792090 riscv: qemu: Split devicetree files for qemu_riscv32/64
This uses QEMU virt which creates its own devicetree.

Copy the existing empty version of this file, so splitting the existing
qemu-virt into two, since anyone actually trying to use this will need a
different devicetree for 32- and 64-bit machines.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
9f4f5f1f4a arm: qemu: Add a devicetree file for qemu_arm64 virt
This uses QEMU virt which creates its own devicetree.

Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
4dc1d8318b arm: qemu: Add a devicetree file for qemu_arm
This uses QEMU virt which creates its own devicetree.

Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Tom Rini
4afab30cae Prepare v2022.01-rc4
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 fjvQ9OPLbnAfHVrad3ZeIkePrLOIF6XYwNQpsjt9aE2kU9IvV5sTa8TxZuQgasBU
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 -----END PGP SIGNATURE-----

Merge tag 'v2022.01-rc4' into next

Prepare v2022.01-rc4
2021-12-20 17:12:04 -05:00
Pali Rohár
2e5d0aa396 arm: mvebu: Use printf for printing fatal errors
There is no point to hide/disable fatal errors via debug() macro.
Print fatal errors loudly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Pali Rohár
9c0642d89b arm: mvebu: Remove commented example code
Include file debug_uart.h already contains documentation how to use it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00