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mach-sunxi: Add SPL SPI boot for SUNIV

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The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: adaptation to Upstream U-Boot]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Jesse Taube 2022-02-11 19:32:34 -05:00 committed by Andre Przywara
parent a08b04b5c7
commit 0dcdaff8b8
2 changed files with 18 additions and 7 deletions
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1
arch/arm/include/asm/arch-sunxi/gpio.h
View file

@ -160,6 +160,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI0 4
#define SUNIV_GPC_SPI0 2
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3

24
arch/arm/mach-sunxi/spl_spi_sunxi.c
View file

@ -90,6 +90,7 @@
#define SPI0_CLK_DIV_BY_2 0x1000
#define SPI0_CLK_DIV_BY_4 0x1001
#define SPI0_CLK_DIV_BY_32 0x100f
/*****************************************************************************/
@ -132,7 +133,8 @@ static uintptr_t spi0_base_address(void)
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
return 0x05010000;
if (!is_sun6i_gen_spi())
if (!is_sun6i_gen_spi() ||
IS_ENABLED(CONFIG_MACH_SUNIV))
return 0x01C05000;
return 0x01C68000;
@ -156,11 +158,16 @@ static void spi0_enable_clock(void)
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
/* Divide by 32, clock source is AHB clock 200MHz */
writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL);
} else {
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
}
if (is_sun6i_gen_spi()) {
/* Enable SPI in the master mode and do a soft reset */
@ -191,7 +198,8 @@ static void spi0_disable_clock(void)
SUN4I_CTL_ENABLE);
/* Disable the SPI0 clock */
writel(0, CCM_SPI0_CLK);
if (!IS_ENABLED(CONFIG_MACH_SUNIV))
writel(0, CCM_SPI0_CLK);
/* Close the SPI0 gate */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
@ -212,6 +220,8 @@ static void spi0_init(void)
if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6))
pin_function = SUN50I_GPC_SPI0;
else if (IS_ENABLED(CONFIG_MACH_SUNIV))
pin_function = SUNIV_GPC_SPI0;
spi0_pinmux_setup(pin_function);
spi0_enable_clock();