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Convert CONFIG_BTB to Kconfig

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This converts the following to Kconfig:
   CONFIG_BTB

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-02-23 12:28:15 -05:00
parent 3db7b2bb4c
commit a3041d934f
13 changed files with 10 additions and 12 deletions
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10
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -317,6 +317,7 @@ config ARCH_MPC8540
config ARCH_MPC8544
bool
select BTB
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125
@ -330,6 +331,7 @@ config ARCH_MPC8544
config ARCH_MPC8548
bool
select BTB
select FSL_LAW
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_NMG_DDR120
@ -352,6 +354,7 @@ config ARCH_MPC8560
config ARCH_P1010
bool
select BTB
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_HAS_SERDES
@ -400,6 +403,7 @@ config ARCH_P1011
config ARCH_P1020
bool
select BTB
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508
@ -496,6 +500,7 @@ config ARCH_P1025
config ARCH_P2020
bool
select BTB
select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
@ -772,6 +777,9 @@ config MPC85XX_HAVE_RESET_VECTOR
bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
depends on MPC85xx
config BTB
bool "toggle branch predition"
config BOOKE
bool
default y
@ -784,12 +792,14 @@ config E500
config E500MC
bool
select BTB
imply CMD_PCI
help
Enble PowerPC E500MC core
config E6500
bool
select BTB
help
Enable PowerPC E6500 core

1
include/configs/MPC8548CDS.h
View file

@ -30,7 +30,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
/*
* Only possible on E500 Version 2 or newer cores.

1
include/configs/P1010RDB.h
View file

@ -151,7 +151,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS

1
include/configs/P2041RDB.h
View file

@ -58,7 +58,6 @@
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS

1
include/configs/T102xRDB.h
View file

@ -121,7 +121,6 @@
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/T104xRDB.h
View file

@ -98,7 +98,6 @@
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/T208xQDS.h
View file

@ -88,7 +88,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/T208xRDB.h
View file

@ -83,7 +83,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/T4240RDB.h
View file

@ -65,7 +65,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/corenet_ds.h
View file

@ -59,7 +59,6 @@
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/kmcent2.h
View file

@ -152,7 +152,6 @@
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS

1
include/configs/p1_p2_rdb_pc.h
View file

@ -145,7 +145,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE
#define CONFIG_BTB
#define CONFIG_ENABLE_36BIT_PHYS

1
include/configs/socrates.h
View file

@ -42,7 +42,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */