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sama7g5 and other SoCs (sama5d3, sam9x60) define in the Reset Controller a RSTC_CR.EXTRST bit that asserts the nrst_out pin which resets external devices. This is particular useful for external devices that are configured in stateful modes which can not be undone without reconfiguring the device or without resetting the device. An example is an SPI NOR flash that is configured in octal mode. The do_reset u-boot cmd does not call any driver's remove method, but merely resets the CPU. As the code was, this left the flash in octal mode, being impossible for the first stage boot loaders to recover/identify the flash after a "software reset". RSTC_CR.EXTRST comes in handy here, as it can be set at "software reset" to assert low the nrst_out pin during a time defined by the RSTC_MR.ERSTL field and reset the external devices (including the SPI NOR flash in the example). nrst_out is always asserted at "user reset" and it resets the external devices correctly. Asserting nrst_out at "software reset" should behave in a similar way. The only difference that I could find between the two types of resets in regards to the nrst_out signal, is that at "user reset" timing diagram the "Processor and Peripherals Reset Line" rises after six MD_SLCK cycles after the nrst_out line rose, while at the "software reset" timing diagram the "Processor and Peripherals Reset Line" is active for 3 MD_SLCK cycles + 2 MCK cycles. In other words, in the "software reset" case the nrst_out signal can be active for a longer period of time than the "Processor and Peripherals Reset Line" active time, depending on the RSTC_MR.ERSTL value. Using the default value (zero) for RSTC_MR.ERSTL, worked just fine for the sama7g5 case. Tested QSPI0 and GMAC0/GMAC1 on sama7g5ek rev 4 after a software reset with RSTC_CR.EXTRST=1 and RSTC_MR.ERSTL=0. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> |
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