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https://github.com/AsahiLinux/u-boot
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arm: apple: Add M1 Pro/Max support
Choose the memory map based on the compatible property from the device tree passed to us by m1n1. Since DRAM on the M1 Pro/Max starts at a different address avoid hardcoding the top of usable memory. Also make sure that the addresses entered into the memory map are page aligned such that we don't crash in dcache_enable(). Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Tested on: Macbook M1 Max Tested-by: Janne Grunau <j@jannau.net>
This commit is contained in:
Mark Kettenis
Tom Rini
parent
55e9cef143
commit
a89fea7fd1
1 changed files with 173 additions and 44 deletions
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@ -14,12 +14,22 @@
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region apple_mem_map[] = {
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/* Apple M1 */
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static struct mm_region t8103_mem_map[] = {
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{
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/* I/O */
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.virt = 0x200000000,
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.phys = 0x200000000,
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.size = 8UL * SZ_1G,
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.size = 2UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x380000000,
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.phys = 0x380000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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@ -27,7 +37,7 @@ static struct mm_region apple_mem_map[] = {
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/* I/O */
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.virt = 0x500000000,
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.phys = 0x500000000,
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.size = 2UL * SZ_1G,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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@ -63,15 +73,110 @@ static struct mm_region apple_mem_map[] = {
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Empty entry for framebuffer */
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0,
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/* Framebuffer */
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = apple_mem_map;
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/* Apple M1 Pro/Max */
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static struct mm_region t6000_mem_map[] = {
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{
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/* I/O */
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.virt = 0x280000000,
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.phys = 0x280000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x380000000,
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.phys = 0x380000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x580000000,
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.phys = 0x580000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x5a0000000,
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.phys = 0x5a0000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x5c0000000,
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.phys = 0x5c0000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x700000000,
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.phys = 0x700000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0xb00000000,
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.phys = 0xb00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0xf00000000,
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.phys = 0xf00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x1300000000,
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.phys = 0x1300000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x10000000000,
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.phys = 0x10000000000,
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.size = 16UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Framebuffer */
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map;
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int board_init(void)
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{
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@ -80,38 +185,7 @@ int board_init(void)
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int dram_init(void)
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{
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ofnode node;
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int index, ret;
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fdt_addr_t base;
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fdt_size_t size;
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ret = fdtdec_setup_mem_size_base();
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if (ret)
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return ret;
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/* Update RAM mapping */
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index = ARRAY_SIZE(apple_mem_map) - 3;
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apple_mem_map[index].virt = gd->ram_base;
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apple_mem_map[index].phys = gd->ram_base;
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apple_mem_map[index].size = gd->ram_size;
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node = ofnode_path("/chosen/framebuffer");
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if (!ofnode_valid(node))
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return 0;
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base = ofnode_get_addr_size(node, "reg", &size);
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if (base == FDT_ADDR_T_NONE)
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return 0;
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/* Add framebuffer mapping */
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index = ARRAY_SIZE(apple_mem_map) - 2;
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apple_mem_map[index].virt = base;
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apple_mem_map[index].phys = base;
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apple_mem_map[index].size = size;
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apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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return 0;
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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@ -128,11 +202,66 @@ void *board_fdt_blob_setup(int *err)
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return (void *)fw_dtb_pointer;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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void build_mem_map(void)
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{
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/*
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* Top part of RAM is used by firmware for things like the
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* framebuffer. This gives us plenty of room to play with.
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*/
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return 0x980000000;
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ofnode node;
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fdt_addr_t base;
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fdt_size_t size;
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int i;
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if (of_machine_is_compatible("apple,t8103"))
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mem_map = t8103_mem_map;
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else if (of_machine_is_compatible("apple,t6000"))
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mem_map = t6000_mem_map;
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else if (of_machine_is_compatible("apple,t6001"))
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mem_map = t6000_mem_map;
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else
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panic("Unsupported SoC\n");
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/* Find list terminator. */
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for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
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;
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/* Align RAM mapping to page boundaries */
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base = gd->bd->bi_dram[0].start;
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size = gd->bd->bi_dram[0].size;
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size += (base - ALIGN_DOWN(base, SZ_4K));
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base = ALIGN_DOWN(base, SZ_4K);
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size = ALIGN(size, SZ_4K);
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/* Update RAM mapping */
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mem_map[i - 2].virt = base;
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mem_map[i - 2].phys = base;
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mem_map[i - 2].size = size;
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node = ofnode_path("/chosen/framebuffer");
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if (!ofnode_valid(node))
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return;
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base = ofnode_get_addr_size(node, "reg", &size);
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if (base == FDT_ADDR_T_NONE)
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return;
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/* Align framebuffer mapping to page boundaries */
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size += (base - ALIGN_DOWN(base, SZ_4K));
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base = ALIGN_DOWN(base, SZ_4K);
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size = ALIGN(size, SZ_4K);
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/* Add framebuffer mapping */
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mem_map[i - 1].virt = base;
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mem_map[i - 1].phys = base;
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mem_map[i - 1].size = size;
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}
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void enable_caches(void)
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{
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build_mem_map();
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icache_enable();
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dcache_enable();
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}
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u64 get_page_table_size(void)
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{
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return SZ_256K;
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}
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