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Merge branch '2022-02-21-platform-updates'

Browse source 
- Assorted updates / fixes for Apple, TI and Aspeed platforms
This commit is contained in:
Tom Rini 2022-02-21 08:53:24 -05:00
commit 17a0dc6abf
13 changed files with 234 additions and 118 deletions
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4
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
View file

@ -192,3 +192,7 @@
&serdes0 {
u-boot,dm-spl;
};
&main_r5fss0 {
ti,cluster-mode = <0>;
};

6
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
View file

@ -259,10 +259,10 @@
regulators: regulators {
u-boot,dm-spl;
buck12_reg: buck12 {
/*VDD_MPU*/
/*VDD_CPU*/
regulator-name = "buck12";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
u-boot,dm-spl;

1
arch/arm/include/asm/arch-omap3/mem.h
View file

@ -480,7 +480,6 @@ void mem_init(void);
u32 is_mem_sdr(void);
u32 mem_ok(u32 cs);
u32 get_sdr_cs_size(u32);
u32 get_sdr_cs_offset(u32);
#endif /* __ASSEMBLY__ */

9
arch/arm/include/asm/arch-omap3/sys_proto.h
View file

@ -33,11 +33,8 @@ struct board_sdrc_timings {
void prcm_init(void);
void per_clocks_enable(void);
void ehci_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
void get_board_mem_timings(struct board_sdrc_timings *timings);
int identify_nand_chip(int *mfr, int *id);
void emif4_init(void);
@ -45,16 +42,12 @@ void gpmc_init(void);
void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
u32 base, u32 size);
void set_gpmc_cs0(int flash_type);
void watchdog_init(void);
void set_muxconf_regs(void);
u32 get_cpu_family(void);
u32 get_cpu_rev(void);
u32 get_sku_id(void);
u32 is_gpmc_muxed(void);
u32 get_gpmc0_type(void);
u32 get_gpmc0_width(void);
u32 is_running_in_sdram(void);
u32 is_running_in_sram(void);
u32 is_running_in_flash(void);
@ -64,12 +57,10 @@ void invalidate_dcache(u32);
u32 wait_on_value(u32, u32, void *, u32);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
int omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
void save_omap_boot_params(void);
#endif

217
arch/arm/mach-apple/board.c
View file

@ -14,12 +14,22 @@
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region apple_mem_map[] = {
/* Apple M1 */
static struct mm_region t8103_mem_map[] = {
{
/* I/O */
.virt = 0x200000000,
.phys = 0x200000000,
.size = 8UL * SZ_1G,
.size = 2UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x380000000,
.phys = 0x380000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -27,7 +37,7 @@ static struct mm_region apple_mem_map[] = {
/* I/O */
.virt = 0x500000000,
.phys = 0x500000000,
.size = 2UL * SZ_1G,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -63,15 +73,110 @@ static struct mm_region apple_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* Empty entry for framebuffer */
0,
/* Framebuffer */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = apple_mem_map;
/* Apple M1 Pro/Max */
static struct mm_region t6000_mem_map[] = {
{
/* I/O */
.virt = 0x280000000,
.phys = 0x280000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x380000000,
.phys = 0x380000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5a0000000,
.phys = 0x5a0000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5c0000000,
.phys = 0x5c0000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x700000000,
.phys = 0x700000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0xb00000000,
.phys = 0xb00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0xf00000000,
.phys = 0xf00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x1300000000,
.phys = 0x1300000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* RAM */
.virt = 0x10000000000,
.phys = 0x10000000000,
.size = 16UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* Framebuffer */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map;
int board_init(void)
{
@ -80,38 +185,7 @@ int board_init(void)
int dram_init(void)
{
ofnode node;
int index, ret;
fdt_addr_t base;
fdt_size_t size;
ret = fdtdec_setup_mem_size_base();
if (ret)
return ret;
/* Update RAM mapping */
index = ARRAY_SIZE(apple_mem_map) - 3;
apple_mem_map[index].virt = gd->ram_base;
apple_mem_map[index].phys = gd->ram_base;
apple_mem_map[index].size = gd->ram_size;
node = ofnode_path("/chosen/framebuffer");
if (!ofnode_valid(node))
return 0;
base = ofnode_get_addr_size(node, "reg", &size);
if (base == FDT_ADDR_T_NONE)
return 0;
/* Add framebuffer mapping */
index = ARRAY_SIZE(apple_mem_map) - 2;
apple_mem_map[index].virt = base;
apple_mem_map[index].phys = base;
apple_mem_map[index].size = size;
apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
return 0;
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
@ -128,11 +202,66 @@ void *board_fdt_blob_setup(int *err)
return (void *)fw_dtb_pointer;
}
ulong board_get_usable_ram_top(ulong total_size)
void build_mem_map(void)
{
/*
* Top part of RAM is used by firmware for things like the
* framebuffer. This gives us plenty of room to play with.
*/
return 0x980000000;
ofnode node;
fdt_addr_t base;
fdt_size_t size;
int i;
if (of_machine_is_compatible("apple,t8103"))
mem_map = t8103_mem_map;
else if (of_machine_is_compatible("apple,t6000"))
mem_map = t6000_mem_map;
else if (of_machine_is_compatible("apple,t6001"))
mem_map = t6000_mem_map;
else
panic("Unsupported SoC\n");
/* Find list terminator. */
for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
;
/* Align RAM mapping to page boundaries */
base = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
size += (base - ALIGN_DOWN(base, SZ_4K));
base = ALIGN_DOWN(base, SZ_4K);
size = ALIGN(size, SZ_4K);
/* Update RAM mapping */
mem_map[i - 2].virt = base;
mem_map[i - 2].phys = base;
mem_map[i - 2].size = size;
node = ofnode_path("/chosen/framebuffer");
if (!ofnode_valid(node))
return;
base = ofnode_get_addr_size(node, "reg", &size);
if (base == FDT_ADDR_T_NONE)
return;
/* Align framebuffer mapping to page boundaries */
size += (base - ALIGN_DOWN(base, SZ_4K));
base = ALIGN_DOWN(base, SZ_4K);
size = ALIGN(size, SZ_4K);
/* Add framebuffer mapping */
mem_map[i - 1].virt = base;
mem_map[i - 1].phys = base;
mem_map[i - 1].size = size;
}
void enable_caches(void)
{
build_mem_map();
icache_enable();
dcache_enable();
}
u64 get_page_table_size(void)
{
return SZ_256K;
}

2
arch/arm/mach-omap2/omap3/emif4.c
View file

@ -35,7 +35,7 @@ u32 is_mem_sdr(void)
* get_sdr_cs_size -
* - Get size of chip select 0/1
*/
u32 get_sdr_cs_size(u32 cs)
static u32 get_sdr_cs_size(u32 cs)
{
u32 size = 0;

35
arch/arm/mach-omap2/omap3/sdrc.c
View file

@ -44,13 +44,28 @@ u32 is_mem_sdr(void)
return 0;
}
/*
* get_sdr_cs_size -
* - Get size of chip select 0/1
*/
static u32 get_sdr_cs_size(u32 cs)
{
u32 size;
/* get ram size field */
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
size &= 0x3FF; /* remove unwanted bits */
size <<= 21; /* multiply by 2 MiB to find size in MB */
return size;
}
/*
* make_cs1_contiguous -
* - When we have CS1 populated we want to have it mapped after cs0 to allow
* command line mem=xyz use all memory with out discontinuous support
* compiled in. We could do it in the ATAG, but there really is two banks...
*/
void make_cs1_contiguous(void)
static void make_cs1_contiguous(void)
{
u32 size, a_add_low, a_add_high;
@ -62,22 +77,6 @@ void make_cs1_contiguous(void)
}
/*
* get_sdr_cs_size -
* - Get size of chip select 0/1
*/
u32 get_sdr_cs_size(u32 cs)
{
u32 size;
/* get ram size field */
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
size &= 0x3FF; /* remove unwanted bits */
size <<= 21; /* multiply by 2 MiB to find size in MB */
return size;
}
/*
* get_sdr_cs_offset -
* - Get offset of cs from cs0 start
@ -128,7 +127,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
* true and a possible 2nd time depending on memory configuration from
* stack+global context.
*/
void do_sdrc_init(u32 cs, u32 early)
static void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
struct board_sdrc_timings timings;

39
arch/arm/mach-omap2/omap3/sys_info.c
View file

@ -55,7 +55,7 @@ void omap_die_id(unsigned int *die_id)
/******************************************
* get_cpu_type(void) - extract cpu info
******************************************/
u32 get_cpu_type(void)
static u32 get_cpu_type(void)
{
return readl(&ctrl_base->ctrl_omap_stat);
}
@ -64,7 +64,7 @@ u32 get_cpu_type(void)
* get_cpu_id(void) - extract cpu id
* returns 0 for ES1.0, cpuid otherwise
******************************************/
u32 get_cpu_id(void)
static u32 get_cpu_id(void)
{
struct ctrl_id *id_base;
u32 cpuid = 0;
@ -89,7 +89,7 @@ u32 get_cpu_id(void)
/******************************************
* get_cpu_family(void) - extract cpu info
******************************************/
u32 get_cpu_family(void)
__used u32 get_cpu_family(void)
{
u16 hawkeye;
u32 cpu_family;
@ -119,7 +119,7 @@ u32 get_cpu_family(void)
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
u32 get_cpu_rev(void)
__used u32 get_cpu_rev(void)
{
u32 cpuid = get_cpu_id();
@ -132,41 +132,12 @@ u32 get_cpu_rev(void)
/*****************************************************************
* get_sku_id(void) - read sku_id to get info on max clock rate
*****************************************************************/
u32 get_sku_id(void)
static u32 get_sku_id(void)
{
struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}
/***************************************************************************
* get_gpmc0_base() - Return current address hardware will be
* fetching from. The below effectively gives what is correct, its a bit
* mis-leading compared to the TRM. For the most general case the mask
* needs to be also taken into account this does work in practice.
* - for u-boot we currently map:
* -- 0 to nothing,
* -- 4 to flash
* -- 8 to enent
* -- c to wifi
****************************************************************************/
u32 get_gpmc0_base(void)
{
u32 b;
b = readl(&gpmc_cfg->cs[0].config7);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return b;
}
/*******************************************************************
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
*******************************************************************/
u32 get_gpmc0_width(void)
{
return WIDTH_16BIT;
}
/*************************************************************************
* get_board_rev() - setup to pass kernel board revision information
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)

1
configs/apple_m1_defconfig
View file

@ -3,7 +3,6 @@ CONFIG_ARCH_APPLE=y
CONFIG_DEFAULT_DEVICE_TREE="t8103-j274"
CONFIG_DEBUG_UART_BASE=0x235200000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x880000000
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set

33
doc/board/apple/m1.rst
View file

@ -7,18 +7,21 @@ Allows Apple Silicon Macs to boot U-Boot via the m1n1 bootloader
developed by the Asahi Linux project. At this point the machines with
the following SoCs work:
- Apple M1 SoC
- Apple M1 SoC (t8103)
- Apple M1 Pro SoC (t6000)
- Apple M1 Max SoC (t6001)
On these SoCs the following hardware is supported:
- S5L serial port
- SPI keyboard (on laptops)
- Framebuffer
- NVMe storage
- USB 3.1 Type-C ports
Device trees are currently provided for the M1 Mac mini (2020, J274)
and M1 MacBook Pro 13" (2020, J293). The M1 MacBook Air (2020) is
expected to work with the J293 device tree. The M1 iMac (2021) may
work with the J274 device tree.
Device trees are currently provided for the M1 Mac mini (2020, J274),
M1 MacBook Pro 13" (2020, J293), M1 MacBook Air (2020, J313) and M1
iMac (2021, J456/J457).
Building U-Boot
---------------
@ -57,3 +60,23 @@ Instructions on how to install U-Boot on your Mac can be found at:
https://github.com/AsahiLinux/docs/wiki/Developer-Quickstart
Just replace ``m1n1.macho`` with ``u-boot.macho`` in the instructions.
Debug UART
----------
Since the base address of the UART is SoC-dependent, the debug UART is
not enabled by default. To enable the debug UART the base address
needs to be adjusted and the CONFIG_DEBUG_UART option needs to be
enabled. The table below gives the correct base address for the
supported SoCs.
.. list-table::
:widths: 32 16
:header-rows: 1
* - SoC
- Base Address
* - M1 (t8103)
- 0x235200000
* - M1 Pro/Max (t6000/t6001)
- 0x39b200000

2
drivers/crypto/aspeed/aspeed_acry.c
View file

@ -103,7 +103,7 @@ static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t
while (1) {
reg = readl(acry->base + ACRY_RSA_INT_STS);
if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) {
writel(reg, ACRY_RSA_INT_STS);
writel(reg, acry->base + ACRY_RSA_INT_STS);
break;
}
udelay(20);

2
drivers/i2c/omap24xx_i2c.c
View file

@ -1015,7 +1015,7 @@ static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
struct omap_i2c *priv = dev_get_priv(bus);
return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
chip_addr);
chip_addr) ? -EREMOTEIO : 0;
}
static int omap_i2c_probe(struct udevice *bus)

1
drivers/iommu/apple_dart.c
View file

@ -48,6 +48,7 @@ static int apple_dart_probe(struct udevice *dev)
static const struct udevice_id apple_dart_ids[] = {
{ .compatible = "apple,t8103-dart" },
{ .compatible = "apple,t6000-dart" },
{ /* sentinel */ }
};