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Convert CONFIG_SYS_IMMR to Kconfig
This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
ff27af1244
commit
be7dbb60c5
20 changed files with 16 additions and 32 deletions
12
arch/Kconfig
12
arch/Kconfig
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@ -353,6 +353,18 @@ config SYS_DISABLE_DCACHE_OPS
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Note that, its up to the individual architectures to implement
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this functionality.
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config SYS_IMMR
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hex
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depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
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default 0xFF000000 if MPC8xx
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default 0xF0000000 if ARCH_MPC8313
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default 0xE0000000 if MPC83xx && !ARCH_MPC8313
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default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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default SYS_CCSRBAR_DEFAULT
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help
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Address for the Internal Memory-Mapped Registers (IMMR) window used
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to configure the features of many Freescale / NXP SoCs.
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config SKIP_LOWLEVEL_INIT
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bool "Skip the calls to certain low level initialization functions"
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depends on ARM || NDS32 || MIPS || RISCV
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@ -11,7 +11,6 @@
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#include <linux/bitops.h>
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#endif
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_DCSRBAR 0x20000000
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#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
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#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
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@ -9,7 +9,6 @@
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#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
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#define __ARCH_FSL_LSCH3_IMMAP_H_
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
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#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
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@ -11,7 +11,6 @@
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#define OCRAM_BASE_S_ADDR 0x10010000
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#define OCRAM_S_SIZE 0x00010000
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_DCSRBAR 0x20000000
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#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
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@ -179,13 +179,6 @@ config ARCH_MPC837X
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select SYS_CACHE_SHIFT_5
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select FSL_ELBC
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config SYS_IMMR
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hex "Value for IMMR"
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default 0xE0000000
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help
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Address for the Internal Memory-Mapped Registers (IMMR) window used
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to configure the features of the SoC.
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source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
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@ -115,9 +115,6 @@ disable_addr_trans:
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#ifndef CONFIG_DEFAULT_IMMR
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#error CONFIG_DEFAULT_IMMR must be defined
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#endif /* CONFIG_DEFAULT_IMMR */
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#ifndef CONFIG_SYS_IMMR
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#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
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#endif /* CONFIG_SYS_IMMR */
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/*
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* After configuration, a system reset exception is executed using the
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@ -84,9 +84,6 @@ config SYS_DER
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help
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Debug Event Register (37-47)
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config SYS_IMMR
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hex "Value for IMMR"
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source "board/cssi/MCR3000/Kconfig"
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endmenu
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@ -4,7 +4,6 @@ CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_SECT_SIZE=0x2000
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CONFIG_DEFAULT_DEVICE_TREE="mcr3000"
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CONFIG_MPC8xx=y
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CONFIG_SYS_IMMR=0xFF000000
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CONFIG_TARGET_MCR3000=y
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CONFIG_8xx_GCLK_FREQ=132000000
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CONFIG_CMD_IMMAP=y
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@ -8,7 +8,6 @@ CONFIG_SYS_CLK_FREQ=66000000
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CONFIG_MPC83xx=y
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CONFIG_HIGH_BATS=y
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CONFIG_TARGET_IDS8313=y
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CONFIG_SYS_IMMR=0xF0000000
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CONFIG_CORE_PLL_RATIO_2_1=y
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CONFIG_PCI_HOST_MODE_ENABLE=y
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CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
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@ -40,6 +40,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_M68K
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#endif
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#if !CONFIG_IS_ENABLED(DM_I2C)
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static const struct fsl_i2c_base *i2c_base[4] = {
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(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
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@ -38,7 +38,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@ -47,7 +47,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
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#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
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#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
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@ -67,7 +67,6 @@
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#define CONFIG_HOSTNAME "M5253DEMO"
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
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#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
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#define CONFIG_SYS_I2C_PINMUX_SET (0)
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@ -58,7 +58,6 @@
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#endif
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
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#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
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#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
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@ -53,7 +53,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@ -47,7 +47,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@ -49,7 +49,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_UDP_CHECKSUM
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@ -58,7 +58,6 @@
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#define CONFIG_MCFTMR
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/* I2C */
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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/*
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* Defines processor clock - important for correct timings concerning serial
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@ -185,8 +185,6 @@
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* I2C
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*/
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1338
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#define CONFIG_I2C_RTC_ADDR 0x68
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@ -60,8 +60,4 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
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#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
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CONFIG_SYS_CCSRBAR_PHYS_LOW)
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#ifndef CONFIG_SYS_IMMR
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
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#endif
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#endif /* __MPC85xx_H__ */
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