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Convert CONFIG_PHY_RESET_DELAY to Kconfig

Browse source 
This converts the following to Kconfig:
   CONFIG_PHY_RESET_DELAY

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-03-18 08:38:26 -04:00
parent 0b956e3987
commit 16199a8b96
19 changed files with 22 additions and 18 deletions
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7
README
View file

@ -1075,13 +1075,6 @@ The following options need to be configured:
The clock frequency of the MII bus
CONFIG_PHY_RESET_DELAY
Some PHY like Intel LXT971A need extra delay after
reset before any MII register access is possible.
For such PHY, set this option to the usec delay
required. (minimum 300usec for LXT971A)
CONFIG_PHY_CMD_DELAY (ppc4xx)
Some PHY like Intel LXT971A need extra delay after

3
arch/arm/include/asm/arch-bcmcygnus/configs.h
View file

@ -19,7 +19,4 @@
#define CONFIG_SYS_NS16550_CLK_DIV 54
#define CONFIG_SYS_NS16550_COM3 0x18023000
/* Ethernet */
#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
#endif /* __ARCH_CONFIGS_H */

2
common/miiphyutil.c
View file

@ -366,7 +366,7 @@ int miiphy_reset(const char *devname, unsigned char addr)
debug("PHY reset failed\n");
return -1;
}
#ifdef CONFIG_PHY_RESET_DELAY
#if CONFIG_PHY_RESET_DELAY > 0
udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
#endif
/*

1
configs/bcm968380gerg_ram_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6838=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_PHY=y
CONFIG_BCM6368_USBH_PHY=y
CONFIG_PINCTRL=y

1
configs/comtrend_ar5315u_ram_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6368_ETH=y
CONFIG_PHY=y

1
configs/comtrend_ar5387un_ram_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6368_ETH=y
CONFIG_PHY=y

1
configs/comtrend_ct5361_ram_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6348_ETH=y
CONFIG_PHY=y

1
configs/comtrend_vr3032u_ram_defconfig
View file

@ -52,6 +52,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6368=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6368_ETH=y
CONFIG_PHY=y

1
configs/comtrend_wap5813n_ram_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_BCM6368_ETH=y

1
configs/huawei_hg556a_ram_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6348_ETH=y
CONFIG_PHY=y

1
configs/netgear_cg3100d_ram_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_RESET=y
CONFIG_RESET_BCM6345=y
CONFIG_DM_SERIAL=y

1
configs/netgear_dgnd3700v2_ram_defconfig
View file

@ -47,6 +47,7 @@ CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_BCM6368_ETH=y

1
configs/sagem_f@st1704_ram_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6348_ETH=y
CONFIG_DM_RESET=y

1
configs/sfr_nb4-ser_ram_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_RESET_DELAY=20
CONFIG_DM_ETH=y
CONFIG_BCM6348_ETH=y
CONFIG_PHY=y

1
configs/stv0991_defconfig
View file

@ -35,6 +35,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_PHY_RESET_DELAY=10000
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
CONFIG_CADENCE_QSPI=y

8
drivers/net/phy/Kconfig
View file

@ -330,3 +330,11 @@ config PHY_NCSI
depends on DM_ETH
endif #PHYLIB
config PHY_RESET_DELAY
int "Extra delay after reset before MII register access"
default 0
help
Some PHYs need extra delay after reset before any MII register access
is possible. For such PHY, set this option to the usec delay
required.

2
drivers/net/phy/phy.c
View file

@ -872,7 +872,7 @@ int phy_reset(struct phy_device *phydev)
return -1;
}
#ifdef CONFIG_PHY_RESET_DELAY
#if CONFIG_PHY_RESET_DELAY > 0
udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
#endif
/*

3
include/configs/bmips_common.h
View file

@ -8,9 +8,6 @@
#include <linux/sizes.h>
/* ETH */
#define CONFIG_PHY_RESET_DELAY 20
/* UART */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 500000, 1500000 }

3
include/configs/stv0991.h
View file

@ -29,9 +29,6 @@
#define CONFIG_DW_ALTDESCRIPTOR
/* Command support defines */
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
/* Misc configuration */
/*