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arm: imx8m: add support for Advantech RSB-3720
Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Darren Huang <darren.huang@advantech.com.tw> Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by: Tim Liang <tim.liang@advantech.com.tw> Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com> Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>
This commit is contained in:
Ying-Chun Liu (PaulLiu)
Stefano Babic
parent
b345f177b9
commit
ddb56f371a
13 changed files with 4828 additions and 0 deletions
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@ -1204,6 +1204,10 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \
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imx8mm-cl-iot-gate-ied-tpm0.dtbo \
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imx8mm-cl-iot-gate-ied-tpm1.dtbo
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ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),)
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dtb-y += imx8mp-rsb3720-a1.dtb
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endif
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dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
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dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
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@ -182,8 +182,23 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
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select SUPPORT_SPL
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select IMX8M_LPDDR4
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select SUPPORT_EXTENSION_SCAN
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config TARGET_IMX8MP_RSB3720A1_4G
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bool "Support i.MX8MP RSB3720A1 4G"
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select BINMAN
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select IMX8MP
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select SUPPORT_SPL
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select IMX8M_LPDDR4
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config TARGET_IMX8MP_RSB3720A1_6G
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bool "Support i.MX8MP RSB3720A1 6G"
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select BINMAN
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select IMX8MP
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select SUPPORT_SPL
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select IMX8M_LPDDR4
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endchoice
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source "board/advantech/imx8mp_rsb3720a1/Kconfig"
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source "board/beacon/imx8mm/Kconfig"
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source "board/beacon/imx8mn/Kconfig"
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source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
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14
board/advantech/imx8mp_rsb3720a1/Kconfig
Normal file
14
board/advantech/imx8mp_rsb3720a1/Kconfig
Normal file
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@ -0,0 +1,14 @@
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if TARGET_IMX8MP_RSB3720A1_4G || TARGET_IMX8MP_RSB3720A1_6G
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config SYS_BOARD
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default "imx8mp_rsb3720a1"
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config SYS_VENDOR
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default "advantech"
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config SYS_CONFIG_NAME
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default "imx8mp_rsb3720"
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source "board/freescale/common/Kconfig"
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endif
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7
board/advantech/imx8mp_rsb3720a1/MAINTAINERS
Normal file
7
board/advantech/imx8mp_rsb3720a1/MAINTAINERS
Normal file
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@ -0,0 +1,7 @@
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i.MX8MP RSB3720 BOARD
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M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
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S: Maintained
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F: board/advantech/imx8mp_rsb3720a1/
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F: include/configs/imx8mp_rsb3720a1.h
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F: configs/imx8mp_rsb3720a1_4G_defconfig
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F: configs/imx8mp_rsb3720a1_6G_defconfig
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24
board/advantech/imx8mp_rsb3720a1/Makefile
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24
board/advantech/imx8mp_rsb3720a1/Makefile
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@ -0,0 +1,24 @@
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#
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# Copyright 2019 NXP
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# Copyright 2022 Linaro
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_6G
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obj-y += imx8mp_rsb3720a1.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_6G.o
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endif
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endif
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ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_4G
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obj-y += imx8mp_rsb3720a1.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_4G.o
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endif
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endif
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213
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
Normal file
213
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
Normal file
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@ -0,0 +1,213 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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* Copyright 2022 Linaro
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*/
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#include <common.h>
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#include <dwc3-uboot.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <spl.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/dma.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static const iomux_v3_cfg_t uart_pads[] = {
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MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static const iomux_v3_cfg_t wdog_pads[] = {
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MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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#ifdef CONFIG_NAND_MXS
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static void setup_gpmi_nand(void)
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{
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init_nand_clk();
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}
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#endif
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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init_uart_clk(2);
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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#define FEC_RST_PAD IMX_GPIO_NR(4, 2)
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static const iomux_v3_cfg_t fec1_rst_pads[] = {
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MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
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ARRAY_SIZE(fec1_rst_pads));
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gpio_request(FEC_RST_PAD, "fec1_rst");
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gpio_direction_output(FEC_RST_PAD, 0);
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mdelay(15);
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gpio_direction_output(FEC_RST_PAD, 1);
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mdelay(100);
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_fec();
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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return 0;
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}
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_DWC_ETH_QOS
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#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
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static const iomux_v3_cfg_t eqos_rst_pads[] = {
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MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_eqos(void)
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{
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imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
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ARRAY_SIZE(eqos_rst_pads));
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gpio_request(EQOS_RST_PAD, "eqos_rst");
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gpio_direction_output(EQOS_RST_PAD, 0);
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mdelay(15);
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gpio_direction_output(EQOS_RST_PAD, 1);
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mdelay(100);
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}
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static int setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_eqos();
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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return set_clk_eqos(ENET_125MHZ);
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}
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#endif /* CONFIG_DWC_ETH_QOS */
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int board_phy_config(struct phy_device *phydev)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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}
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return 0;
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}
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#define DISPMIX 13
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#define MIPI 15
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#define WDOG_TRIG IMX_GPIO_NR(4, 20)
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static iomux_v3_cfg_t wdt_trig[] = {
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MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_wdt(void)
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{
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imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
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gpio_request(WDOG_TRIG, "wdt_trig");
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gpio_direction_output(WDOG_TRIG, 1);
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}
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int board_init(void)
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{
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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#ifdef CONFIG_DWC_ETH_QOS
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/* clock, pin, gpr */
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setup_eqos();
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#endif
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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setup_iomux_wdt();
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return 0;
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}
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int board_late_init(void)
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{
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if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
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env_set("board_name", "RSB3720A1");
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env_set("board_rev", "iMX8MP");
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}
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return 0;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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#define UBOOT_RAW_SECTOR_OFFSET 0x40
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unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
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{
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u32 boot_dev = spl_boot_device();
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switch (boot_dev) {
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case BOOT_DEVICE_MMC2:
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return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
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default:
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return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
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}
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}
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#endif /* CONFIG_SPL_MMC_SUPPORT */
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11
board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg
Normal file
11
board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg
Normal file
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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* Copyright 2022 NXP
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*/
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#define __ASSEMBLY__
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ROM_VERSION v2
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BOOT_FROM sd
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LOADER u-boot-spl-ddr.bin 0x920000
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1847
board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c
Normal file
1847
board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c
Normal file
File diff suppressed because it is too large
Load diff
1875
board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c
Normal file
1875
board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c
Normal file
File diff suppressed because it is too large
Load diff
260
board/advantech/imx8mp_rsb3720a1/spl.c
Normal file
260
board/advantech/imx8mp_rsb3720a1/spl.c
Normal file
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Copyright 2022 Linaro
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <errno.h>
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#include <fsl_esdhc_imx.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <mmc.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <dm/uclass.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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#ifdef CONFIG_SPL_BOOTROM_SUPPORT
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return BOOT_DEVICE_BOOTROM;
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#else
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switch (boot_dev_spl) {
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case SD1_BOOT:
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case MMC1_BOOT:
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC2;
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case QSPI_BOOT:
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return BOOT_DEVICE_NOR;
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case NAND_BOOT:
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return BOOT_DEVICE_NAND;
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case USB_BOOT:
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return BOOT_DEVICE_BOARD;
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default:
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return BOOT_DEVICE_NONE;
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}
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#endif
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
|
||||
PAD_CTL_PE | \
|
||||
PAD_CTL_FSEL2)
|
||||
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
|
||||
#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS | \
|
||||
PAD_CTL_DSE4)
|
||||
|
||||
static const iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static const iomux_v3_cfg_t usdhc2_pads[] = {
|
||||
MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifndef USDHC3_BASE_ADDR
|
||||
#define USDHC3_BASE_ADDR 0x30B60000
|
||||
#endif
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR, 0, 8},
|
||||
};
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
int i, ret;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
init_clk_usdhc(1);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
|
||||
ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
break;
|
||||
case 1:
|
||||
init_clk_usdhc(2);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
|
||||
ARRAY_SIZE(usdhc3_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers");
|
||||
printf("(%d) than supported by the board\n", i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
default:
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *pdev;
|
||||
int ret;
|
||||
|
||||
ret = pmic_get("pca9450@25", &pdev);
|
||||
if (ret == -ENODEV) {
|
||||
printf("No pmic\n");
|
||||
return 0;
|
||||
}
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
||||
pmic_reg_write(pdev, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/*
|
||||
* increase VDD_SOC to typical value 0.95V before first
|
||||
* DRAM access, set DVS1 to 0.85v for suspend.
|
||||
* Enable DVS control through PMIC_STBY_REQ and
|
||||
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
|
||||
*/
|
||||
pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS0, 0x1C);
|
||||
pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS1, 0x14);
|
||||
pmic_reg_write(pdev, PCA9450_BUCK1CTRL, 0x59);
|
||||
|
||||
/* Kernel uses OD/OD freq for SOC */
|
||||
/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
|
||||
pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C);
|
||||
|
||||
/* set WDOG_B_CFG to cold reset */
|
||||
pmic_reg_write(pdev, PCA9450_RESET_CTRL, 0xA1);
|
||||
|
||||
/* Forced enable the I2C level translator*/
|
||||
pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
167
configs/imx8mp_rsb3720a1_4G_defconfig
Normal file
167
configs/imx8mp_rsb3720a1_4G_defconfig
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_SYS_I2C_MXC_I2C2=y
|
||||
CONFIG_SYS_I2C_MXC_I2C3=y
|
||||
CONFIG_SYS_I2C_MXC_I2C4=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_TARGET_IMX8MP_RSB3720A1_4G=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_CMD_BOOTEFI_SELFTEST=y
|
||||
CONFIG_CMD_ERASEENV=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_SHA1SUM=y
|
||||
CONFIG_CMD_BIND=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_UDP_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x5000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_UUU_SUPPORT=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_S35392A=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_SDP_LOADADDR=0x40480000
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_SHA512_ALGO=y
|
||||
CONFIG_SHA512=y
|
||||
CONFIG_SHA384=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_BZIP2=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_SET_TIME=y
|
||||
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
|
||||
CONFIG_EFI_CAPSULE_ON_DISK=y
|
||||
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
|
||||
CONFIG_EFI_SECURE_BOOT=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_POWER_I2C=y
|
||||
CONFIG_SPL_DM_I2C=y
|
||||
CONFIG_SPL_DM_PMIC=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
168
configs/imx8mp_rsb3720a1_6G_defconfig
Normal file
168
configs/imx8mp_rsb3720a1_6G_defconfig
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_SYS_I2C_MXC_I2C2=y
|
||||
CONFIG_SYS_I2C_MXC_I2C3=y
|
||||
CONFIG_SYS_I2C_MXC_I2C4=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_TARGET_IMX8MP_RSB3720A1_6G=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-rsb3720-a1"
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_IMX_CONFIG="board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb"
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_CMD_BOOTEFI_SELFTEST=y
|
||||
CONFIG_CMD_ERASEENV=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_SHA1SUM=y
|
||||
CONFIG_CMD_BIND=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_UDP_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x5000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_UUU_SUPPORT=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_S35392A=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_SDP_LOADADDR=0x40480000
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_SHA512_ALGO=y
|
||||
CONFIG_SHA512=y
|
||||
CONFIG_SHA384=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_BZIP2=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_SET_TIME=y
|
||||
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
|
||||
CONFIG_EFI_CAPSULE_ON_DISK=y
|
||||
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
|
||||
CONFIG_EFI_SECURE_BOOT=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_POWER_I2C=y
|
||||
CONFIG_SPL_DM_I2C=y
|
||||
CONFIG_SPL_DM_PMIC=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
223
include/configs/imx8mp_rsb3720.h
Normal file
223
include/configs/imx8mp_rsb3720.h
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* Copyright 2022 Linaro
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MP_RSB3720_H
|
||||
#define __IMX8MP_RSB3720_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x960000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
|
||||
|
||||
#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
|
||||
* GD_FLG_FULL_MALLOC_INIT \
|
||||
* set \
|
||||
*/
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#if defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_DMA
|
||||
#define CONFIG_SPL_NAND_MXS
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#define CONFIG_SPL_NAND_IDENT
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of \
|
||||
* first 64MB boot area \
|
||||
*/
|
||||
|
||||
/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full
|
||||
* boot image (not only FIT part) to the mtdpart, so we check both two offsets
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
|
||||
(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
/* ENET Config */
|
||||
/* ENET1 */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
|
||||
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 4
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#define DWC_NET_PHYADDR 4
|
||||
#ifdef CONFIG_DWC_ETH_QOS
|
||||
#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
|
||||
#endif
|
||||
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(CMD_MMC)
|
||||
# define BOOT_TARGET_MMC(func) \
|
||||
func(MMC, mmc, 2) \
|
||||
func(MMC, mmc, 1)
|
||||
#else
|
||||
# define BOOT_TARGET_MMC(func)
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(CMD_PXE)
|
||||
# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
|
||||
#else
|
||||
# define BOOT_TARGET_PXE(func)
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(CMD_DHCP)
|
||||
# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
|
||||
#else
|
||||
# define BOOT_TARGET_DHCP(func)
|
||||
#endif
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
BOOT_TARGET_MMC(func) \
|
||||
BOOT_TARGET_PXE(func) \
|
||||
BOOT_TARGET_DHCP(func)
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"splashimage=0x50000000\0" \
|
||||
"console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
|
||||
"fdt_addr=0x43000000\0" \
|
||||
"fdt_addr_r=0x43000000\0" \
|
||||
"boot_fit=no\0" \
|
||||
"dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"kernel_addr_r=0x40480000\0" \
|
||||
"pxefile_addr_r=0x40480000\0" \
|
||||
"ramdisk_addr_r=0x43800000\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
|
||||
"bootm ${loadaddr}; " \
|
||||
"else " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs ${jh_clk} console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
|
||||
"bootm ${loadaddr}; " \
|
||||
"else " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi;\0"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
/* Totally 6GB or 4G DDR */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
|
||||
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
|
||||
#define PHYS_SDRAM_2 0x100000000
|
||||
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
|
||||
#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
|
||||
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
|
||||
#define PHYS_SDRAM_2 0xC0000000
|
||||
#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
|
||||
#endif
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define CONFIG_IMX_BOOTAUX
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#ifdef CONFIG_FSL_FSPI
|
||||
#define FSL_FSPI_FLASH_SIZE SZ_32M
|
||||
#define FSL_FSPI_FLASH_NUM 1
|
||||
#define FSPI0_BASE_ADDR 0x30bb0000
|
||||
#define FSPI0_AMBA_BASE 0x0
|
||||
#define CONFIG_FSPI_QUAD_SUPPORT
|
||||
|
||||
#define CONFIG_SYS_FSL_FSPI_AHB
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x20000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
#endif /* CONFIG_NAND_MXS */
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#endif /* __IMX8MP_RSB3720_H */
|
||||
Loading…
Add table
Reference in a new issue