Commit graph

21493 commits

Author SHA1 Message Date
Ye Li
6f3858d732 arm: imx8ulp: add container support
i.MX8ULP support using ROM API to load container image,
it use same ROM API as i.MX8MN/MP, and use same container format
as i.MX8QM/QXP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
20ed81eaeb arm: imx: parse-container: guard included header files
Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure
for i.MX8ULP

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Ye Li
31f0085285 arm: imx8: Move container image header file to mach-imx
Since the container is shared among i.MX platforms, move its header file
to mach-imx

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Ye Li
7d84978c9c arm: imx8: Move container parser and image to mach-imx common folder
Since we will re-use the container parser on imx8ulp, move the codes
to mach-imx

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
9ef89ea9b0 arm: imx: basic i.MX8ULP support
Add basic i.MX8ULP support

For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
c17f5935cf imx: imx8ulp: add get reset cause
Add get reset cause function to show what triggerred reset.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
77c3b9cc98 arm: imx8ulp: support print cpu info
Support print cpu info. the clock function has not been added, it will
be added in following patches.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
5f17fef893 arm: imx: sys_proto: move boot mode define to common header
These defines could be reused by i.MX8ULP, so move them
to common header.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
331d40d701 arm: imx: add i.MX8ULP cpu type and helper
Add i.MX8ULP cpu type and helpers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Peng Fan
19b990b4f7 arm: imx: add i.MX8ULP basic Kconfig option
Add i.MX8ULP related basic Kconfig option, which will be used later.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09 14:46:50 +02:00
Fabio Estevam
1d1f3c8099 mx28evk: Convert to driver model
Make the conversion to driver model as it is mandatory.

Successfully tested booting Linux from the SD card.

Dropped support for networking and splash screen as these need
to be properly converted to DM and tested.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-08-09 14:46:50 +02:00
Sebastian Reichel
3bbc48e8f1 board: ge: bx50v3: Add PCIe reset to DT
Add PCIe reset gpio to the Bx50v3 devicetree and get get rid of
CONFIG_PCIE_IMX_PERST_GPIO.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2021-08-09 14:46:50 +02:00
Tim Harvey
a8a72c3ce9 board: gateworks: venice: add imx8mm-gw7902 support
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- LTE CAT M1 modem
- USB 2.0 HUB
- M.2 Socket with USB2.0, PCIe, and dual-SIM
- IMX8M FEC
- PCIe based GbE
- RS232/RS485/RS422 serial transceiver
- GPS
- CAN bus
- WiFi / Bluetooth
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- PMIC

Do the following to add support for it:
- add dts
- add PMIC config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09 14:46:50 +02:00
Tim Harvey
42bc70d14a arm: dts: imx8mm-venice-gw7901: use common u-boot dtsi
Use the common imx8mm-u-boot.dtsi

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09 14:46:50 +02:00
Tim Harvey
aea162c10e arm: dts: imx8mm-venice-gw700x: fix fifo-depth phy props
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties
not supported by U-Boot drivers/net/phy/dp83867.c with the proper
'ti,fifo-depth' property.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09 14:46:50 +02:00
Tim Harvey
98559e02f1 arm: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12
is the power-enable to the TPS25821 Source controller and power switch
responsible for monitoring the CC pins and enabling VBUS. Therefore
GPIO1_12 must always be enabled and the vbus output enable from the
IMX8MM can be ignored.

To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the
TPS25821 and change the regulator output to GPIO1_10 which is
unconnected.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09 14:46:50 +02:00
Tim Harvey
a194e6ed45 imx: ventana: remove hard-coded USB OTG pinmux
pinmux is now done via dt. Add missing OTG_OC pinmux for boards that
use it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09 14:46:50 +02:00
Tim Harvey
dd79c97b92 imx: ventana: fix UMS support
The Gateworks Ventana boards have always had usb0=usbh1 and usb1=usbotg
because OTG is often subloaded on these boards and a bit in the EEPROM
which flagging that OTG is subloaded is used to remove the dt node via the
alias.

U-Boot DM_USB UMS requires the usb0 alias be assigned to the usbotg
so fix the usb0 alias in order for UMS to work.

Fixes 72c46327f0: ("imx: ventana: enable dm support for USB")

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09 14:46:50 +02:00
Jan Kiszka
3823315cbe Revert "arm: bootm: Disable LMB reservation for command line and board info on arm64"
This reverts commit 2359fa7a87.

While the goal is valid and there is surely unused memory in that area,
we also have a lot of crucial things still located at the top-of-memory
while running lmb_alloc_base. Such things are the page table (tlb_addr),
relocated U-Boot and the active stack. Possibly more. So this patch was
premature, we will need relocations of those things first if we want to
use the range.

Fixes booting on the IOT2050, but likely also on other boards. It got
stuck on relocating the FDT - over the relocated U-Boot code.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-08-08 11:59:01 -04:00
Marek Vasut
2525fa3cb8 ARM: renesas: Turn on PIE for Gen3
Turn on PIE, so that the U-Boot binary can be started from any arbitrary
location in DRAM instead of a predefined fixed one. Note that this patch
is not setting SYS_TEXT_BASE=0x0 yet, since that triggers relocation bugs
in env code that are yet to be fixed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-08-08 12:27:04 +02:00
Simon Glass
22137b8d73 pci: ppc: Drop ftpci100 driver
This is not used in U-Boot at present. Drop it and related config options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-06 08:26:48 -04:00
Simon Glass
ebacc78e3e pci: arm: mvebu: Drop DM_PCI check from arch_early_init_r
We don't need this check anymore since when PCI is enabled, driver model
is always used.

Use CONFIG_PCI instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Correct macro usage)
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-06 08:20:45 -04:00
Fabio Estevam
3f24bd329b imx28-evk: Import devicetree file from Linux
Import the imx28-evk devicetree files from Linux kernel
version 5.11-rc7.

This is in preparation for converting the mx28evk_defconfig
target to driver model.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-08-06 13:26:08 +02:00
Simon Glass
63814a6986 pci: imx: Drop DM_PCI check from cpu driver
We don't need this check anymore since when PCI is enabled, driver model
is always used.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05 19:46:35 -04:00
Simon Glass
595232ad1f pci: powerpc: Drop old code
Drop the old pre-driver model code from these drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-05 16:14:36 -04:00
Tom Rini
b91c704333 Merge https://source.denx.de/u-boot/custodians/u-boot-samsung 2021-08-03 09:07:01 -04:00
Tom Rini
3b64774323 Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- Fixed broken ICH SPI driver in software sequencer mode
- Added "m25p,fast-read" to SPI flash node for x86 boards
- Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds
- Define a default TSC timer frequency for all x86 boards
- x86 MTRR MSR programming codes bug fixes
- x86 "hob" command bug fixes
- Don't program MTRR for DRAM for FSP1
- Move INIT_PHASE_END_FIRMWARE to FSP2
- Use external graphics card by default on Intel Crown Bay
- tangier: Fix DMA controller IRQ polarity in CSRT
2021-08-02 21:35:50 -04:00
Simon Glass
0b1284eb52 global: Convert simple_strtoul() with decimal to dectoul()
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 13:32:14 -04:00
Simon Glass
7e5f460ec4 global: Convert simple_strtoul() with hex to hextoul()
It is a pain to have to specify the value 16 in each call. Add a new
hextoul() function and update the code to use it.

Add a proper comment to simple_strtoul() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 13:32:14 -04:00
Bin Meng
c71d5fb717 x86: queensbay: Return directly if IGD / SDVO were already disabled
Initialize 'igd' and 'sdvo' to NULL so that we just need to test
them against NULL later, to be compatible with that case that IGD
and SDVO devices were already in disabled state.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-03 00:03:14 +08:00
Bin Meng
33e4ab31a9 x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE
For FSP1, there is no such INIT_PHASE_END_FIRMWARE.

Move board_final_cleanup() to fsp2 directory.

Fixes: 7c73cea442 ("x86: Notify the FSP of the 'end firmware' event")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
2021-08-03 00:01:38 +08:00
Bin Meng
02541601cb x86: fsp: Don't program MTRR for DRAM for FSP1
There are several outstanding issues as to why this does not apply
to FSP1:

* For FSP1, the system memory and reserved memory used by FSP are
  already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
  same RES_MEM_RESERVED resource type. Its address is programmed
  and reported by FSP to be near the top of 4 GiB space, which is
  not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
  to be exactly the power of 2. This causes reserved bits of the
  IA32_MTRR_PHYSMASK register to be written which generates #GP.

For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
2021-08-03 00:01:29 +08:00
Bin Meng
9a7c6fde07 x86: mtrr: Abort if requested size is not power of 2
The size parameter of mtrr_add_request() and mtrr_set_next_var()
shall be power of 2, otherwise the logic creates a mask that does
not meet the requirement of IA32_MTRR_PHYSMASK register.

Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:41 +08:00
Bin Meng
3bcd6cf89e x86: mtrr: Skip MSRs that were already programmed in mtrr_commit()
At present mtrr_commit() programs the MTRR MSRs starting from
index 0, which may overwrite MSRs that were already programmed
by previous boot stage or FSP.

Switch to call mtrr_set_next_var() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Bin Meng
596bd0589a x86: mtrr: Do not clear the unused ones in mtrr_commit()
Current mtrr_commit() logic assumes that MTRR MSRs are programmed
consecutively from index 0 to its maximum number, and whenever it
detects an unused one, it clears all other MTRRs starting from that
one. However this may not always be the case.

In fact, the clear is not much helpful because these MTRRs come out
of reset as disabled already. Drop the clear codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Bin Meng
c79cbb5952 x86: dts: Define a default TSC timer frequency
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.

Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Bin Meng
5824bc6d6f x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ
Currently there are two places to specify the x86 TSC timer frequency
with one in Kconfig used for early timer and the other one in device
tree used when the frequency cannot be determined from hardware.

This may potentially create an inconsistent config where the 2 values
do not match. Let's use the one specified in Kconfig in the device
tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Bin Meng
ffaa7abfc5 x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROM
These 2 options are no longer needed as now binman is used to build
u-boot.rom.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Andy Shevchenko
46db4bbac3 x86: tangier: Fix DMA controller IRQ polarity in CSRT
IRQ polarity in CSRT has the same definition as by ACPI specification
chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e.
ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller
IRQ polarity is ActiveHigh.

Note, in DSDT (see southcluster.asl) it's described correctly.

Fixes: 5e99fde34a ("x86: tangier: Populate CSRT for shared DMA controller")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Bin Meng
bd798eed55 x86: dts: Add "m25p,fast-read" to SPI flash node
Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should
have "m25p,fast-read" property present in their DT nodes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02 15:11:40 +08:00
Simon Glass
eec44c7218 dtoc: Support widening a bool value
At present if we see 'ranges' property (with no value) we assume it is a
boolean, as per the devicetree spec.

But another node may define 'ranges' with a value, forcing us to widen it
to an int array. At present this is not supported and causes an error.

Fix this and add some test cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
2021-08-01 09:05:24 -06:00
Simon Glass
cb8970092f sandbox: Reduce keyed autoboot delay
The autoboot tests are a recent addition to U-Boot, providing much-needed
coverage in this area.

A side effect of the keyed autoboot test is that this feature is enabled
in sandbox always. This changes the autoboot prompt and confuses the
pytests. Some tests become slower, for example the vboot tests take about
27s now instead of 3s.

We don't actually need this feature enabled to be able to run the tests.
Add a switch to allow sandbox to turn it on and off as needed. Use this
in the one test that needs it.

Add a command-line flag in case this is desired in normal use.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 25c8b9f298 ("test: add first autoboot unit tests")
Reviewed-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2021-08-01 09:05:24 -06:00
Tom Rini
5371593aed Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Move the PSCI runtime code for H3/A23/A33 into SRAM
- Pick the environment from the actual MMC boot device (SD card vs.
  eMMC)
- Plus a small improvement from Icenowy, just for good measure.
2021-07-31 20:51:24 -04:00
Icenowy Zheng
001ec430be sunxi: decide the inclusion of SCP by SCP_ADDR existence
There are more Allwinner SoCs that do not have a SCP now.

When there's no SCP_ADDR macro defined, we can assume there's no SCP
available.

Drop the scp part of FIT description when SCP_ADDR does not exist.

Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-08-01 00:11:34 +01:00
Samuel Holland
1ebfc0c631 sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
monitor code (providing PSCI runtime services). And while those SoCs do
not have the secure SRAM B like older SoCs, there is enough (secure)
SRAM A2 to put the monitor code and data in there instead.

Follow the design of 64-bit SoCs and use the first part for the monitor,
and the last 16 KiB for the SCP firmware. With this change, the monitor
no longer needs to reserve a region in DRAM.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: amend commit message, fix R40 and V3s build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-08-01 00:11:34 +01:00
Pali Rohár
2226ca1734 arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header
Now that proper load and execution addresses are set in v1 kwbimage we
can use it for loading and booting U-Boot proper.

Use the new spl_parse_board_header() function to implement parsing the
kwbimage v1 header. Use information from this header to locate offset and
size of the U-Boot proper binary, instead of using the legacy U-Boot
header which is prepended to the U-Boot proper binary stored at fixed
offset. This has the advantage that we do not need to relay on legacy
U-Boot header anymore and therefore U-Boot proper binary can be stored at
any offset, as is the case when loading & booting U-Boot proper by
BootROM. The CONFIG_SYS_U_BOOT_OFFS option is therefore not used by SPL
code anymore.

Also allow to compile U-Boot SPL without CONFIG_SPL_SPI_FLASH_SUPPORT,
CONFIG_SPL_MMC_SUPPORT or CONFIG_SPL_SATA_SUPPORT set. In this case
BootROM is used for loading and executing U-Boot proper. This reduces the
size of U-Boot's SPL image. By default these config options are enabled
and so BootROM loading is not used. In some cases BootROM reads from SPI
NOR at lower speed than U-Boot SPL. So people can decide whether they
want to have smaller SPL binary at the cost of slower boot.

Therefore dependency on CONFIG_SPL_DM_SPI, CONFIG_SPL_SPI_FLASH_SUPPORT,
CONFIG_SPL_SPI_LOAD, CONFIG_SPL_SPI_SUPPORT, CONFIG_SPL_DM_GPIO,
CONFIG_SPL_DM_MMC, CONFIG_SPL_GPIO_SUPPORT, CONFIG_SPL_LIBDISK_SUPPORT,
CONFIG_SPL_MMC_SUPPORT, CONFIG_SPL_SATA_SUPPORT and
CONFIG_SPL_LIBDISK_SUPPORT is changed from strict to related "imply"
(which can be selectivelly turned off and causes booting via BootROM).

Options CONFIG_SYS_SPI_U_BOOT_OFFS,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR and
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET have to to be set to
zero as they define the location where kwbimage header starts. It is the
location where BootROM expects start of the kwbimage from which it reads,
parses and executes SPL part. The same applies to option
CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR, which has to be set to one.

Update all config files to set correct values of these options and set
CONFIG_SYS_U_BOOT_OFFS to the correct value - the offset where U-Boot
proper starts.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-31 09:59:58 +02:00
Pali Rohár
abbf2179b2 arm: mvebu: Use U-Boot's SPL BootROM framework for booting from NAND/UART
Current code uses hack in board_init_f() which calls return_to_bootrom()
to skip U-Boot SPL code and return back to BootROM to load U-Boot via
UART or from NAND.

This change migrates that hack from the board_init_f() function and
changes it to return BOOT_DEVICE_BOOTROM instead of returning to BootROM
directly, so that U-Boot's SPL framework is used for returning to
BootROM.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
2021-07-31 09:49:32 +02:00
Pali Rohár
9d0225b7fa arm: mvebu: Implement return_to_bootrom() via U-Boot's SPL framework
U-Boot's SPL framework already has an API for loading U-Boot via
BootROM.

Implement the function board_return_to_bootrom() for mvebu SPL code.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
2021-07-31 09:49:32 +02:00
Pali Rohár
e1cd0d424c arm: mvebu: Mark return_to_bootrom() as a noreturn function
This function does not return, so add the appropriate compiler flag.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
2021-07-31 09:49:32 +02:00
Pali Rohár
4375598c52 arm: mvebu: Fix return_to_bootrom()
Register r0 should be set to return value 0x0 - NO_ERR.

Set r0 with return value after all registers are restored from the
stack, so that the return value is always correct.

Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 944c7a3176 ("arm: mvebu: Add option to use UART xmodem protocol via kwboot")
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
2021-07-31 09:49:32 +02:00
Mattijs Korpershoek
0e577643f5 Revert "ARM: meson: Add support for fastboot_set_reboot_flag()"
With the introduction of a generic reboot flag implemented in commit
a362ce214f ("fastboot: Implement generic fastboot_set_reboot_flag"), we
no longer need the custom PSCI implementation to handle the reboot reason.

This reverts commit 9a34dedfae.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-07-30 14:54:03 +02:00
Tom Rini
15f7e0dc01 Merge branch '2021-07-28-assorted-fixes'
- Assorted bugfixes
2021-07-29 12:10:55 -04:00
Tom Rini
38436abd5e Merge tag 'ti-v2021.10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Add MMC High speed modes for AM64 and J7200
- Add Sierra/Torrent SERDES driver
- Minor clean-ups for R5F boot from SPL
2021-07-29 08:20:06 -04:00
Patrice Chotard
268f6ac1f9 arm64: Update memcpy_{from, to}io() helpers
At early U-Boot stage, before relocation, MMU is not yet configured
and disabled. DDR may not be configured with the correct memory
attributes (can be configured in MT_DEVICE instead of MT_MEMORY).

In this case, usage of memcpy_{from, to}io() may leads to synchronous
abort in AARCH64 in case the normal memory address is not 64Bits aligned.

To avoid such situation, forbid usage of normal memory cast to (u64 *) in
case MMU is not enabled.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: mark.kettenis@xs4all.nl
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-28 19:30:22 -04:00
Patrick Delaunay
558e699d15 arm: use the correct prototype for reset_cpu function
Align reset_cpu function with the next prototypes in
sysreset.h or in cpu_func.h to solve compilation issue:

  void reset_cpu(void);

This patch solves the prototype conflict when cpu_func.h is
included.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-28 19:30:22 -04:00
Simon Glass
975e7cf301 i2c: Rename SPL/TPL_I2C_SUPPORT to I2C
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-28 14:29:37 -04:00
Simon Glass
69d9eda4da i2c: Rename CONFIG_SYS_I2C to CONFIG_SYS_I2C_LEGACY
It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and
CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less
than a year away.

Also we want to have a CONFIG_I2C for U-Boot proper just like we have
CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules.

Rename this symbol so it is clear it is going away.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-28 14:29:37 -04:00
Simon Glass
9ca00684db Rename DRIVERS_MISC_SUPPORT to DRIVERS_MISC
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:29:37 -04:00
Simon Glass
83061dbd1c Rename GPIO_SUPPORT to GPIO
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:29:36 -04:00
Simon Glass
333e4a621d Rename SPL_USB_HOST_SUPPORT to SPL_USB_HOST
Rename this option so that CONFIG_IS_ENABLED can be used with it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:27:54 -04:00
Simon Glass
078111b9c0 Rename SPL_WATCHDOG_SUPPORT to SPL_WATCHDOG
Rename this option so that CONFIG_IS_ENABLED can be used with it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:27:54 -04:00
Simon Glass
89ddb0bfeb Rename SPL_MUSB_NEW_SUPPORT to SPL_MUSB_NEW
Rename this option so that CONFIG_IS_ENABLED can be used with it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:27:54 -04:00
Simon Glass
f2d7a36ec2 Rename SPL_ETH_SUPPORT to SPL_ETH
Rename this option so that CONFIG_IS_ENABLED can be used with it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-28 14:27:54 -04:00
Simon Glass
933b2f09cb Rename SPL_POWER_SUPPORT to SPL_POWER
Rename this option so that CONFIG_IS_ENABLED can be used with it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-28 14:27:54 -04:00
Tom Rini
55efa84d0f - Add SMBIOS info for Khadas VIM boards
- Fix meson-axg-mipi PHY build
 - Fix VIM3 board phy-names property setup
 - Return correct value for non emmc boot sources on VIM3
 - add kernel compression vars
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Merge tag 'u-boot-amlogic-20210727' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- Add SMBIOS info for Khadas VIM boards
- Fix meson-axg-mipi PHY build
- Fix VIM3 board phy-names property setup
- Return correct value for non emmc boot sources on VIM3
- add kernel compression vars
2021-07-27 11:42:31 -04:00
Artem Lapkin
e10481be1e ARM: dts: meson: Use devicetree for SMBIOS settings for Khadas VIM boards
Khadas vim series: Use devicetree for SMBIOS settings
Add settings and enable the default sysinfo driver so that these can come
from the device tree.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Artem Lapkin <art@khadas.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-07-27 10:32:59 +02:00
Alexandru Gagniuc
65b3f56d42 ARM: dts: stm32mp: Add OP-TEE reserved memory to SPL dtb
Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-27 09:48:11 +02:00
Alexandru Gagniuc
8533263c85 stm32mp1: spl: Configure TrustZone controller for OP-TEE
OP-TEE is very particular about how the TZC should be configured.
When booting an OP-TEE payload, an incorrect TZC configuration will
result in a panic.

Most information can be derived from the SPL devicetree. The only
information we don't have is the split between TZDRAM and shared
memory. This has to be hardcoded. The rest of the configuration is
fairly easy, and only requires 3 TZC regions. Configure them.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-07-27 09:48:11 +02:00
Alexandru Gagniuc
8d7f5edd86 arm: stm32mp: Implement support for TZC 400 controller
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API presented here is
intended to allow exactly that.

UCLASS support is not implemented, because it would not be too useful.
Changing TZC permissions needs to be done with care, so as not to cut
off access to memory we are currently using. One place where we can
use this is at the end of SPL, right before jumping to OP-TEE.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-27 09:48:09 +02:00
Marek Vasut
59000ebe0b ARM: dts: stm32: Fix AV96 eMMC pinmux
Commit 500327e2ea ("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.8-rc1")
renamed sdmmc2_d47_pins_b phandle to sdmmc2_d47_pins_c, but without updating
the AV96 DT which uses that phandle. Linux missed similar update as well and
it was only added in commit 1ad6e36ec266 ("ARM: dts: stm32: Fix sdmmc2 pins
on AV96") .

Update the AV96 DT pinmux phandle, otherwise eMMC 8bit mode does not work
and access to eMMC takes a very long time to fall back to 4bit mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-27 09:47:40 +02:00
Patrick Delaunay
2a7034c77d stm32mp1: add pull-up for gpio button PA13 and PA14
When a push-button is released and PA13/PA14 are defined as input (high-Z)
the LED should not be active as the circuit is open but a small current
leak through PCB or push-button close the circuit and allows a small LED
bias giving erroneous level voltage.

So it is recommended to activate an internal pull-up in order to clearly
fix the voltage at PA13/PA14 when button is released and to wait
a short delay before to read the GPIO value only when the pull-up is
correctly configured.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-27 09:47:40 +02:00
Patrick Delaunay
8b71b20e0e arm: stm32mp1: force boot_device variable for invalid TAMP register value
When the TAMP register 20 have an invalid value (0x0 for example after
TAMPER error) the "boot_device" U-Boot env variable have no value and
no error is displayed in U-Boot log.

The STM32MP boot command bootcmd_stm32mp failed with strange trace:
  "Boot over !"

and the next command in bootcmd_stm32mp failed with few indication:
  if test ${boot_device} = serial || test ${boot_device} = usb;
	then stm32prog ${boot_device} ${boot_instance};

As it is difficult to investigate, the current patch avoids this issue:
- change the debug message to error: "unexpected boot mode" is displayed
- display trace "Boot over invalid!" in bootcmd_stm32mp
- execute "run distro_bootcmd" to try all the possible target

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-27 09:47:40 +02:00
Suman Anna
24f3fb6547 arm: dts: k3-j721e-r5: Remove MAIN R5FSS0 cluster from SPL
The MAIN R5FSS0 cluster and corresponding nodes are no longer required
to be enabled in R5 SPL after removing the support for booting any core
from this cluster on R5 SPL. So, remove these from the relevant dts
files.

This is essentially a revert of the additions done in commit 2984b82b3b
("arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL").

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-5-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Suman Anna
ea985f6d92 arm: mach-k3: Cleanup common start_non_linux_remote_cores()
The mach-k3 common code defined a weak start_non_linux_remote_cores()
function so that the proper implementation can be plugged in the
SoC-specific source files. This won't be needed anymore, so remove the
the common code.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-4-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Suman Anna
536f633d8a arm: mach-k3: j721e: Cleanup MAIN R5 boot code from R5 SPL
The common J7 specific start_non_linux_remote_cores() override function
implements the logic to load and boot the Main R5FSS Core0 from R5 SPL.
This won't be supported any more for either J721E or J7200 after the R5
SPL rearchitecture for the System Firmware split into TI Foundation
Security (TIFS) and Device Management (DM) firmwares. So, cleanup the
corresponding code and the related SPL env variables.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-3-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Suman Anna
05e858aefe arm: mach-k3: j721e: Move booting of Main R5FSS Core0 to A72 U-Boot
The Main R5FSS Core0 on J721E SoCs is originally booted from R5 SPL
itself to achieve certain product-level early-boot metrics. This is
no longer supported after the R5 SPL re-architecture (support merged
for v2021.10-rc1). Move the booting of this core altogether from R5
SPL to A72 U-Boot.

The env variables are left as is for now, and will be cleaned up
in a subsequent patch.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-2-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Suman Anna
31b3d7a018 arm: dts: k3-am65: Fix up MCU R5FSS cluster mode back to Split-mode
The default U-Boot environment variables and design are all set up to
have the MCU R5FSS cluster to be in Split-mode. This is the setting
in v2021.01 U-Boot and the dt nodes are synched with the kernel binding
property names in commit 468ec2f3ef ("remoteproc: k3_r5: Sync to
upstreamed kernel DT property names") merged in v2021.04-rc2.

The mode for the cluster got switched back to LockStep mode by mistake
in commit e497876343 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts
into U-Boot") also in v2021.04-rc2. This throws the following warning
messages when early-booting the cores using default env variables,

  k3_r5f_rproc r5f@41400000: Invalid op: Trying to start secondary core 2 in lockstep mode
  Load Remote Processor 1 with data@addr=0x82000000 65268 bytes: Failed!

Fix this by switching back the cluster to the expected Split-mode.
Make this mode change in the u-boot specific dtsi file to avoid such
sync overrides in the future until the kernel dts is also switched to
Split-mode by default.

Fixes: e497876343 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726162213.28719-1-s-anna@ti.com
2021-07-27 11:00:10 +05:30
Aswath Govindraju
0817dd5432 arch: dts: am642-sk-u-boot: Disable main_sdhci0 DT node and define alias index 1 for main_sdhci1 node
A Wilink wireless device is connected to MMCSD0 subsystem and is not
supported in U-Boot. Therefore, disable main_sdhci0 device tree node in
U-Boot.

If main_sdhci0 device tree node is disabled then the the index of
main_sdhci1 node becomes 0 which leads to break in boot flow. Therefore,
add an alias to fix the index to 1.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-3-a-govindraju@ti.com
2021-07-27 10:58:49 +05:30
Aswath Govindraju
2140d6b0ff arch: arm: mach-k3: am642_init: Correct the function name spl_boot_mode() to spl_mmc_boot_mode()
Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the
boot mode for a given boot device. This function was renamed to
spl_mmc_boot_mode() by commit e97590654a.

Therefore, rename spl_boot_mode to spl_mmc_boot_mode.

Fixes: 57dba04afb ("arm: mach-k3: am642: Add support for boot device detection")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-2-a-govindraju@ti.com
2021-07-27 10:58:49 +05:30
Aswath Govindraju
08189ffd15 arm: dts: k3-j7200-common-proc-board-u-boot: Add u-boot tags for torrent serdes
Add u-boot tags for torrent serdes. This has properties specific to
u-boot on top of DT in v5.13 Linux Kernel.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-15-kishon@ti.com
2021-07-27 10:57:12 +05:30
Aswath Govindraju
cbea79867e arm: dts: k3-j7200-common-proc-board: Enable SERDES DT
Add default lane function for torrent serdes. This is in sync
with v5.13 Linux Kernel.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com
2021-07-27 10:57:12 +05:30
Aswath Govindraju
6c4be8eb7e arm: dts: k3-j7200-main: Add DT node for torrent serdes
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-13-kishon@ti.com
2021-07-27 10:57:12 +05:30
Kishon Vijay Abraham I
ad256cc894 ARM: dts: k3-j721e: Add support for USB3 in USB0 instance
Configure the parent clock of wiz3_pll0_refclk to the internal clock
required for USB3 to be functional and also remove "ti,usb2-only"
property as it now supports USB3 mode. This has properties specific to
u-boot on top of DT present in v5.13 of Linux Kernel.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-12-kishon@ti.com
2021-07-27 10:57:12 +05:30
Paul Barker
124b3030f5 arm: dts: Import am335x-sancloud-bbe devicetree
This device tree is imported from Linux 5.13.1 and enabled via the
am335x board file and the am335x evm defconfig.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2021-07-27 10:56:09 +05:30
Paul Barker
942853dd96 arm: dts: Resync BeagleBone device trees
These device trees are updated to match the versions in Linux 5.13.1.
The tick-timer entry in am335x-bone-common.dtsi is preserved.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2021-07-27 10:56:09 +05:30
Aswath Govindraju
455f9dddc8 arm: dts: k3-j7200-main: Add support for HS400 and update delay select values for MMCSD subsystems
HS400 speed mode is now supported in J7200 SoC[1]. Therefore add
mmc-hs400-1_8v tag in sdhci0 device tree node.

Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].

[1] - section 12.3.6.1.1 MMCSD Features, in
      https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf,
      (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021)

[2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf,
      (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210525093826.10390-3-a-govindraju@ti.com
2021-07-27 10:56:09 +05:30
Simon Glass
5e19f4aa13 samsung: exynos: Convert SROMC interface to a driver
Add a bus driver for this and use it to configure the bus parameters for
the Ethernet interface. Drop the old pre-driver-model code.

Switch over to use driver model for Ethernet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2021-07-27 10:34:27 +09:00
Manish Narani
15ca9ebb07 arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB node
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:26:41 +02:00
Piyush Mehta
d036f4f2c6 arm64: dts: zynqmp: Enable USB2.0 for zc1751-xm016-dc2
The board zynqmp-zc1751-xm016-dc2 support only USB2.0.
This patch removes USB3.0 DT configuration for DC2 board.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:18:45 +02:00
Tom Rini
ec22c365e3 Pull request for efi-2021-10-rc1-3
Documentation:
 	provide Makefile documentation
 
 SMBIOS:
 	generate BIOS release date based on UEFI version
 	improve error handling in SMBIOS table generation
 
 UEFI:
 	correct handling of signed capsule if authentication if off
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Merge tag 'efi-2021-10-rc1-3' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2021-10-rc1-3

Documentation:
	provide Makefile documentation

SMBIOS:
	generate BIOS release date based on UEFI version
	improve error handling in SMBIOS table generation

UEFI:
	correct handling of signed capsule if authentication if off
2021-07-24 16:41:25 -04:00
Heinrich Schuchardt
c193d9bd28 smbios: error handling for invalid addresses
SMBIOS tables only support 32bit addresses. If we don't have memory here
handle the error gracefully:

* on x86_64 fail to start U-Boot
* during UEFI booting ignore the missing table

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-24 10:49:51 +02:00
Peter Hoyes
c48fec6e7c armv8: Initialize CNTFRQ if at highest exception level
CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.

This patch moves the initialization outside of the switch_el
block and uses a new macro branch_if_not_highest_el which
dynamically detects whether it is at the highest supported
exception level.

Linux's docs state that CNTFRQ_EL0 should be initialized by the
bootloader. If not set, the the U-Boot prompt countdown hangs.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-07-23 18:53:46 -04:00
Stephan Gerhold
0204d1b56b board: dragonboard410c: Load U-Boot directly without LK
At the moment the U-Boot port for the DragonBoard 410c is designed
to be loaded as an Android boot image after Qualcomm's Little Kernel (LK)
bootloader. This is simple to set up but LK is redundant in this case,
since everything done by LK can be also done directly by U-Boot.

Dropping LK entirely has at least the following advantages:
  - Easier installation/board code (no need for Android boot images)
  - (Slightly) faster boot
  - Boot directly in 64-bit without a round trip to 32-bit for LK

So far this was not possible yet because of unsolved problems:

  1. Signing tool: The firmware expects a "signed" ELF image with extra
     (Qualcomm-specific) ELF headers, usually used for secure boot.
     The DragonBoard 410c does not have secure boot by default but the
     extra ELF headers are still required.

  2. PSCI bug: There seems to be a bug in the PSCI implementation
     (part of the TrustZone/tz firmware) that causes all other CPU cores
     to be started in 32-bit mode if LK is missing in the boot chain.
     This causes Linux to hang early during boot.

There is a solution for both problems now:

  1. qtestsign (https://github.com/msm8916-mainline/qtestsign)
     can be used as a "signing" tool for U-Boot and other firmware.

  2. A workaround for the "PSCI bug" is to execute the TZ syscall when
     entering U-Boot. That way PSCI is made aware of the 64-bit switch
     and starts all other CPU cores in 64-bit mode as well.

Simplify the dragonboard410c board by removing all the extra code that
is only used to build an Android boot image that can be loaded by LK.
This allows dropping the custom linker script, special image magic,
as well as most of the special build/installation instructions.

CONFIG_REMAKE_ELF is used to build a new ELF image that has both U-Boot
and the appended DTB combined. The resulting u-boot.elf can then be
passed to the "signing" tool (e.g. qtestsign).

The PSCI workaround is placed in the "boot0" hook that is enabled
with CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK. The extra check for EL1 allows
compatibility with custom firmware that enters U-Boot in EL2 or EL3,
e.g. qhypstub (https://github.com/msm8916-mainline/qhypstub).

As a first step these changes apply only to DragonBoard410c.
Similar changes could likely also work for the DragonBoard 820c.

Note that removing LK wouldn't be possible that easily without a lot of
work already done three years ago by Ramon Fried. A lot of missing
initialization, pinctrl etc was already added back then even though
it was not strictly needed yet.

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-07-23 18:53:45 -04:00
Masami Hiramatsu
11cd1d6a34 dts: synquacer: Add partition information to the spi-nor
Add partition information to the spi-nor flash.
This is required for accessing NOR flash via mtdparts.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-07-23 18:53:45 -04:00
Nandor Han
c74675bd90 reboot-mode: read the boot mode from RTC memory
RTC devices could provide battery-backed memory that can be used for
storing the reboot mode magic value.

Add a new reboot-mode back-end that uses RTC to store the reboot-mode
magic value. The driver also supports both endianness modes.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-23 10:16:39 -04:00
Nandor Han
f9db2f16cb reboot-mode: read the boot mode from GPIOs status
A use case for controlling the boot mode is when the user wants
to control the device boot by pushing a button without needing to
go in user-space.

Add a new backed for reboot mode where GPIOs are used to control the
reboot-mode. The driver is able to scan a predefined list of GPIOs
and return the magic value. Having the modes associated with
the magic value generated based on the GPIO values, allows the
reboot mode uclass to select the proper mode.

Signed-off-by: Nandor Han <nandor.han@vaisala.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-23 10:16:39 -04:00
Tom Rini
a15fa1ba67 dtoc improvements to show better warnings
minor test build fixes
 sandbox fixes for SDL2 and running TPL
 bloblist resize feature
 binman multithreading
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Merge tag 'dm-pull-21jul21' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

dtoc improvements to show better warnings
minor test build fixes
sandbox fixes for SDL2 and running TPL
bloblist resize feature
binman multithreading
2021-07-22 11:15:52 -04:00
Tom Rini
806734f41b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
fsl-qoriq: Update mc firmware size, address in LS1088A, LS2088A, LX2
Updates on ls1043aqds, ls1043ardb
Refactor I2C MUX Code on fsl-qoriq platforms.
2021-07-22 08:45:32 -04:00
Heinrich Schuchardt
fd25ca3275 sandbox: don't set SA_NODEFER in signal handler
The sandbox can handle signals. Due to a damaged global data pointer
additional exceptions in the signal handler may occur leading to an endless
loop. In this case leave the handling of the secondary exception to the
operating system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:35 -06:00
Simon Glass
6b165ab2b7 sandbox: mmc: Support fixed MMC devices
Add support for reading devicetree flags for MMC devices. With this we
can distinguish between fixed and removable drives. Note that this
information is only available when the device is probed, not when it is
bound, since it is read in the of_to_plat() method. This could be changed
if needed later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-21 10:27:35 -06:00
Simon Glass
350b1d3b68 sandbox: Use hinting with the display
SDL provides a hinting feature which provides a higher-quality image
with the double-display option (-K). Enable it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
fcb7e31082 sandbox: Add work-around for SDL2 display
At present the display does not show on some machines, e.g. Ubunutu
20.04 but the reason is unknown. Add a work-around until this can be
determined.

Also include more error checking just in case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Simon Glass
f178bebf55 sandbox: Support executables for more phases
The SPL header has a function for obtaining the phase in capital letters,
e.g. 'SPL'. Add one for lower-case also, as used by sandbox.

Use this to generalise the sandbox logic for determining the filename of
the next sandbox executable. This can provide support for VPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-21 10:27:34 -06:00
Zong Li
e52b83ab13 board: sifive: drop stuff related to unmatched revision 1
This patch reverts the following commits:
 - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1")
 - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board")

We won't plan to support unmatched that the revision below 3 in u-boot,
so they can be dropped because they might be useless.

Changed in v2:
 - rebase codebase to the latest master branch

Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-21 16:39:57 +08:00
Vitaly Wool
6ba8eeb6f1 riscv: booti: do not force relocation if force_reloc is not set
If force_reloc flag is not set and booti is called for an address
ouside RAM (i. e. QSPI NOR flash), we should honor that and not try
to force relocation in a bogus fashion.

Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-21 16:38:26 +08:00
Marek Vasut
3d5f45c95c ARM: dts: rmobile: Disable RPC HF by default
The RPC HF might be locked by ATF, and any access to its register
space would result in complete hang. Disable the RPC HF by default.
The ATF should be patched to set RPC node status = "okay" in the DT
fragment it passes to U-Boot in case the RPC HF access is unlocked,
and that way U-Boot could access the RPC HF safely.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-07-20 23:33:54 +02:00
Marek Vasut
91c6a3a459 ARM: rmobile: Align CPU: print with other prints
The CPU: print only has one space after it, while the other prints
from U-Boot align the value to offset 7. Align the CPU: print too.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-07-20 23:33:54 +02:00
Marek Vasut
778fbe2668 ARM: dts: rmobile: Add sysinfo extras on R-Car Gen3
Add sysinfo node and phandle to the board ID EEPROM on all boards
where this functionality is described in DT, which is Salvator-X(S),
ULCB and Ebisu. The u-boot,dm-pre-reloc is necessary here, since the
sysinfo must be available early during boot. The V3M and V3H boards
currently do not describe this board ID EEPROM in upstream DT, but
that could be easily added later, once the DTs contain the necessary
nodes.

ULCB and Ebisu needs the full EEPROM node in the u-boot extras DT,
since the EEPROM node is still missing in the upstream DTs. Ebisu
also needs extra compatible string override for the i2c_dvfs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-07-20 23:33:54 +02:00
Camelia Groza
af956271f6 arm: dts: ls1043ardb: configure the RGMII ports with rgmii-id
The RGMII ports on LS1043ARDB platforms require both RX and TX internal
delays to be enabled. The device tree reports only the TX ID because the
RX ID used to be enabled by default.

With the addition of RX ID support for the Realtek 8211F PHY driver in
commit e32e4d0f58 ("net: phy: realtek: add rx delay support for
RTL8211F"), the RX ID is disabled by the driver if not reported explicitly.
This causes the RX to no longer work.

Change the phy-connection-type for the RGMII ports to "rgmii-id" in order
to enable both RX and TX internal delays.

Fixes: be1d758969 ("ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB")
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-07-20 14:53:43 +05:30
Tom Rini
dd3dfa50d8 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Marvell SheevaPlug: Convert Ethernet and SATA to Driver Model (Tony)
- Zyxel NSA310S NAS: Convert to Driver Model (Tony)
- Turris_omnia: Add `u-boot-env` NOR partition (Marek)
- Turris_omnia: Fixup MTD partitions in Linux' DTB (Marek)
- Espressobin: Enable 'mtd' command and define SPI NOR partitions (Pali)
2021-07-19 08:41:04 -04:00
Tom Rini
83befb4466 Merge tag 'ti-v2021.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Enabled distro boot for all TI platforms.
- Cleanup for AM335x Guardian Board
- PRUSS rproc on AM65 platform.
- Add PMIC support for J7200
- Misc fixes for Nokia RX-51

# Conflicts:
#	arch/arm/mach-omap2/am33xx/Kconfig
2021-07-19 08:29:24 -04:00
Pali Rohár
a675eb14bd arm: mvebu: Espressobin: Enable 'mtd' command and define SPI NOR partitions
U-Boot now supports parsing SPI NOR partitions from Device Tree. So enable
'mtd' command support for Espressobin board and define partition layout in
U-Boot Espressobin DTS file. Access to SPI NOR via 'sf' command is old
method and 'mtd' command is now preferred variant.

From include file remove '#define CONFIG_MTD_PARTITIONS' as this option is
now defined and enabled in defconfig file. This change is required to fix
compile error:

      CC      arch/arm/lib/asm-offsets.s
    In file included from include/config.h:4,
                     from include/common.h:16,
                     from lib/asm-offsets.c:14:
    include/configs/mvebu_armada-37xx.h:63: warning: "CONFIG_MTD_PARTITIONS" redefined
     #define CONFIG_MTD_PARTITIONS  /* required for UBI partition support */

    In file included from ././include/linux/kconfig.h:4,
                     from <command-line>:
    include/generated/autoconf.h:44: note: this is the location of the previous definition
     #define CONFIG_MTD_PARTITIONS 1

After enabling support for mtd command, output from 'mtd list' on
Espressobin board is:

    => mtd list
    List of MTD devices:
    * w25q32dw
      - device: spi-flash@0
      - parent: spi@10600
      - driver: jedec_spi_nor
      - path: /soc/internal-regs/spi@10600/spi-flash@0
      - type: NOR flash
      - block size: 0x1000 bytes
      - min I/O: 0x1 bytes
      - 0x000000000000-0x000000400000 : "w25q32dw"
              - 0x000000000000-0x0000003f0000 : "firmware"
              - 0x0000003f0000-0x000000400000 : "u-boot-env"
    =>

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-19 09:05:30 +02:00
Marek Behún
644b986470 ARM: dts: armada-385-turris-omnia: add u-boot-env NOR partition
Specify a separate partition `u-boot-env` for U-Boot's env settings for
the Turris Omnia board.

Do this only in U-Boot's specific DTS. We do not want to do this in
Linux' official DTS, because Omnia's stock U-Boot stores env at a
different address, and there are still boards with stock U-Boot.

In a subsequent patch will add board code that fixes Linux's DTB before
booting Linux.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-19 09:05:30 +02:00
Tony Dinh
ee48f53722 arm: kirkwood: NSA310S: Add device tree DTS for Zyxel NSA310S board
Add device tree kirkwood-nsa310s.dts for Zyxel NSA310S board to
convert to Driver Model.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-19 08:44:02 +02:00
Tom Rini
be5c0608b8 usb: Enforce DM_USB migration for USB_HOST devices.
As the deadline for migration to DM_USB, when using a USB host
controller has now gone two years past the deadline, enforce migration.
This is done by:

- Ensuring that all host controller options (other than the very legacy
  old MUSB ones) now select USB_HOST.  USB_HOST now enforces DM_USB and
  OF_CONTROL.
  - Remove other parts of Kconfig logic that had platforms pick DM_USB.
  - To keep Kconfig happy, have some select statements test for USB_HOST
    as well.
- Re-order some Kconfig entries and menus so that we can cleanly pick
  host or gadget roles.  For the various HCD options that have platform
  glue options, group them together and update dependencies in some
  cases.
- As SPL_DM_USB is not required, on platforms that had not yet enabled
  it, disable it.

Cc: Marek Vasut <marex@denx.de>
Cc: Icenowy Zheng <icenowy@aosc.io>
Cc: Samuel Holland <samuel@sholland.org>
Cc: FUKAUMI Naoki <naobsd@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:05:31 -04:00
Tom Rini
96b97fa311 m68k: Remove M52277EVB board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is also the last in family remove the related
support as well.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:03:57 -04:00
Tom Rini
a732f621bc m68k: Remove M54451EVB board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is also the last in family remove the related
support as well.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:03:57 -04:00
Tom Rini
5e770daa3c m68k: Remove M54418TWR board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:03:57 -04:00
Tom Rini
563cae7c46 m68k: Remove M54455EVB board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-18 21:03:57 -04:00
Daniel Schwierzeck
526ceb4387 MIPS: malta: enable PCI driver model
Enable DM_PCI and DM_ETH on MIPS Malta.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-07-18 20:37:39 +02:00
Daniel Schwierzeck
73be5636f4 MIPS: malta: add DT bindings for PCI host controller
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-07-18 20:37:39 +02:00
Tom Rini
d5dbc661c3 i.MX
----
 
 - mx7ulp : fix  WDOG
 - imx8 : Phytec
 - USB3 support for i.MX8
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
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Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX
----

- mx7ulp : fix  WDOG
- imx8 : Phytec
- USB3 support for i.MX8

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17 10:52:21 -04:00
Ye Li
4a837d433c arm: imx8mq: Add USB clock init function
Add clock function to setup relevant clocks for USB3.0 controllers and
PHYs on i.MX8MQ

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-17 13:12:23 +02:00
Ye Li
4390e9f997 arm: dts: imx8mq: Add alias for two usb controllers
Add alias for two DWC3 usb controllers to fix the seq index.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-17 13:12:23 +02:00
Tom Rini
c39946a2e2 Merge branch '2021-07-15-assorted-fixes'
- Large number of Coverity reported issues addressed
- m41t62 bugfix
- Support more Android image compression formats
- FIT + DTO bugfix
2021-07-16 09:15:59 -04:00
Patrick Delaunay
db1ab52e15 ARM: dts: stm32mp15: remove mmc alias
Remove the mmc alias no more required as the sequence number
of mmc device is used for boot_instance.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
3c1057c548 stm32mp: use device sequence number in boot_instance variable
Use the device sequence number in boot_instance variable
and no more the SDMMC instance provided by ROM code/TF-A.

After this patch we don't need to define the mmc alias in
device tree, for example:
  mmc0 = &sdmmc1;
  mmc1 = &sdmmc2;
  mmc2 = &sdmmc3;
to have a correct mapping between the ROM code boot device =
"${boot_device}${boot_instance}" and the MMC device in U-Boot.

With this patch the 'mmc0' device (used in mmc commands) is
always used when only one instance sdmmc is activated in device
tree, even if it is only the sdmmc2 or sdmmc3.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
b18c3abdea stm32mp: stm32prog: use defines for virtual partition size
Use the existing defines PMIC_SIZE and OTP_SIZE and a new define
CMD_SIZE for virtual partition size.

This patch corrects the size for OTP partition in alternate name
(1024 instead of 512) and avoids other alignment issues.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
7c55249307 stm32mp: syscon: manage clock when present in device tree
Enable the clocks during syscon probe when they are present in device tree.

This patch avoids a freeze when the SYSCFG clock is not enabled by
TF-A / OP-TEE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
7e54934532 arm: dts: stm32mp15: alignment with v5.13
Device tree alignment with Linux kernel v5.13
- ARM: dts: stm32: Add PTP clock to Ethernet controller
- ARM: dts: stm32: enable the analog filter for all I2C nodes in
  stm32mp151
- ARM: dts: stm32: fix usart 2 & 3 pinconf to wake up with flow control
- ARM: dts: stm32: Add wakeup management on stm32mp15x UART nodes
- ARM: dts: stm32: add #clock-cells property to usbphyc node on stm32mp151
- ARM: dts: stm32: Add STM32MP1 I2C6 SDA/SCL pinmux
- ARM: dts: stm32: Rename mmc controller nodes to mmc@
- ARM: dts: stm32: Add additional init state for SDMMC1 pins

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
80cfc6c692 stm32mp: cmd_stm32key: add subcommand close
The expected sequence to close the device

1/ Load key in DDR with any supported load command
2/ Update OTP with key: STM32MP> stm32key read <addr>

At this point the device is able to perform image authentication but
non-authenticated images can still be used and executed.
So it is the last moment to test boot with signed binary and
check that the ROM code accepts them.

3/ Close the device: only signed binary will be accepted !!
   STM32MP> stm32key close

Warning: Programming these OTP is an irreversible operation!
         This may brick your system if the HASH of key is invalid

This command should be deactivated by default in real product.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
d3551b8eef stm32mp: cmd_stm32key: add read OTP subcommand
Allow to read the OTP value and lock status with the command
$> stm32key read.

This patch also protects the stm32key fuse command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
e00e1f394c stm32mp: cmd_stm32key: add get_misc_dev function
Add a helper function to access to BSEC misc driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
3da2552a22 stm32mp: cmd_stm32key: lock of PKH OTP after fuse
Lock the OTP value of key's hash after the command
$> stm32key fuse <address>

This operation forbids a second update of these OTP as they are
ECC protected in BSEC: any update of these OTP with a different value
causes a BSEC disturb error and the closed chip will be bricked.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
fe24090eb7 stm32mp: cmd_stm32key: handle error in fuse_hash_value
Handle errors in fuse_hash_value function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
bc78d5f25a stm32mp: cmd_stm32key: use sub command
Simplify parsing the command argument by using
the macro U_BOOT_CMD_WITH_SUBCMDS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
3a99481159 stm32mp: configs: activate the command stm32key only for ST boards
This command is used to evaluate the secure boot on stm32mp SOC,
it is deactivated by default in real products.

We activate this command only in STMicroelectronics defconfig
used with the evaluation boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-07-16 09:28:46 +02:00
Patrick Delaunay
edca8c3f8e stm32mp: stm32prog: fix the content of short help message
Reduce the content of short help message for stm32prog command and
removed the carriage return to fix the display of 'help' command when
this command is activated.

Fixes: 954bd1a923 ("stm32mp: add the command stm32prog")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-16 09:28:46 +02:00
Simon Glass
9a72bea6cb sandbox: Silence coverity warning in state_read_file()
In this case the value seems save to pass to os_free(). Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 165109)
2021-07-15 18:42:05 -04:00
Tom Rini
d3fc3da9a4 Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- x86: various improvements made in getting Chromium OS verified boot
  running on top of coreboot, booting into U-Boot.
2021-07-15 11:06:24 -04:00
Gowtham Tammana
2094e70692 arm/dts: k3-j7200-r5-common: Hook buck1_reg to vtm supply
Hook buck1_reg to vtm avs supply.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210714205300.17424-5-g-tammana@ti.com
2021-07-15 17:56:04 +05:30
Gowtham Tammana
fcdf03aab9 arm/dts: k3-j7200-r5-common: Add VTM node
Add voltage and thermal management (VTM) node. The efuse values for the
OPPs are stored under the VTM, and is needed for AVS class 0 support.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210714205300.17424-4-g-tammana@ti.com
2021-07-15 17:56:04 +05:30
Gowtham Tammana
6fb8706bcb arm/dts: k3-j7200-r5-common: Add pmic lp876441 node
Add pmic lp876411 node needed for CPU AVS support.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210714205300.17424-3-g-tammana@ti.com
2021-07-15 17:56:04 +05:30
Adam Ford
4f9b15eac1 arm: omap3: Make secure_unlock_mem() static
secure_unlock_mem() is only used in one file, so make it static
in that file.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-4-aford173@gmail.com
2021-07-15 17:56:04 +05:30
Adam Ford
46bf58d9f6 arm: omap3: Make secureworld_exit() static
secureworld_exit() is only used in one file, so make it static
to that file and remove it from sys_proto.h. This
may help with some further optimization in the future.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-3-aford173@gmail.com
2021-07-15 17:56:04 +05:30
Adam Ford
1ddd0ed34a arm: omap3: Make try_unlock_memory() static
try_unlock_memory() is only used in one file, so make it static
in that file,remove it from the sys_proto header file, and relocate
it into the #ifdef section that call it. This will make it only built
under the conditions when it is called, and it may help with some
further optimization in the future.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210625192308.277136-2-aford173@gmail.com
2021-07-15 17:56:04 +05:30
Gowtham Tammana
ba7455a796 arm: mach-k3: am642_init: Add missing ddr guard
The `struct udevice *` reference is needed for either of the
K3_LOAD_SYSFW, K3_AM64_DDRSS config guards. Adding the missing
K3_AM64_DDRSS guard.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210624171614.14244-1-g-tammana@ti.com
2021-07-15 17:56:04 +05:30
Lokesh Vutla
c81e7f8d17 arm: dts: ti: k3-am65-main: Add ICSSG nodes
Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a PRUSS subsystem node. These nodes are enabled by
default.

DT nodes are fetch from Linux 5.13 Kernel.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210622063431.3151-5-lokeshvutla@ti.com
2021-07-15 17:56:04 +05:30
Lokesh Vutla
654b60a8fd arm: dts: k3-am654-base-board: Add r5 specific u-boot dtsi
So far all the u-boot specific properties for both r5 and a53 are
placed in k3-am654-base-board-u-boot.dtsi. But there are few a53
nodes that should be updated but doesn't belong to r5. So create a
separate r5 specific u-boot dtsi.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210622063431.3151-4-lokeshvutla@ti.com
2021-07-15 17:56:04 +05:30
Aswath Govindraju
776e25788c arm: dts: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.

Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.

[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210616163821.20457-3-a-govindraju@ti.com
2021-07-15 17:56:04 +05:30
Aswath Govindraju
5242c6a432 configs: am64x_evm_a53_defconfig: Move TF-A load address to 0x701c0000
Earlier, the region 0x701c0000 to 0x701dffff was firewalled off because of
a bug in SYSFW. In the v2021.05 release of SYSFW this bug has been fixed
and this region can now be used for other allocations.

Therefore, move TF-A's load address to 0x701c0000 and update its location
in the device tree node. Also, increase the size allocated for TF-A to
account for future expansions.

Fixes: defd62ca13 ("arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its max size")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210616163821.20457-2-a-govindraju@ti.com
2021-07-15 17:56:04 +05:30
Gireesh Hiremath
9cd380ef5f am335x, guardian: Enable panel driver Himax HX8238D
- Enable lcd controller
- Display splash screen

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210611161350.2141-16-Gireesh.Hiremath@in.bosch.com
2021-07-15 17:56:03 +05:30
Moses Christopher
cea76a4f42 am335x, guardian: Update pinmux configuration
pinmux update for guardian board
- control ASP Board Power: GPIO, on/off ASP Board Power
- control Coincell Voltage Measurement: GPIO, enable/disable
  ADC measurements
- powerOff Device GPIO-PowerOff, cut the PMIC supply

Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210611161350.2141-7-Gireesh.Hiremath@in.bosch.com
2021-07-15 17:56:03 +05:30
Moses Christopher
050531db00 am335x, guardian: mem: Add board dependent mem values
- Add mem-guardian.h derived from am33xx/mem.h

    * Add GPMC config values optimized for Bosch Guardian Board
    * NAND Chip used by Bosch Guardian Board is Micron MT29F4G08ABBFA

Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210611161350.2141-3-Gireesh.Hiremath@in.bosch.com
2021-07-15 17:56:03 +05:30
Simon Glass
2f91fc4003 x86: Ensure the e820 map is installed in all cases
This is a revert of a recent logic change in setup_zimage(). We do
actually need to install this information always. Change it to install
from the Coreboot tables if available, else the normal source.

Fixes: e7bae8283f ("x86: Allow installing an e820 when booting from coreboot")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:56:16 +08:00
Simon Glass
54e0bd1728 x86: cros: Check ROM exists before building vboot
All the x86 devicetree files are built at once, whichever board is
actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
is not defined and samus cannot build Chromium OS verified boot. Add
this condition to avoid errors about CONFIG_ROM_SIZE being missing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-15 19:50:25 +08:00
Simon Glass
4dfe4b44cc x86: coreboot: Use vendor in the Kconfig
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
defined TARGET_COREBOOT.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:50:21 +08:00
Simon Glass
c5c62155c5 x86: Add function comments to cb_sysinfo.h
Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:50:17 +08:00
Simon Glass
7052968707 x86: Do cache set-up by default when booting from coreboot
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.

If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:50:09 +08:00
Simon Glass
0f5ca1d1f1 x86: Update the MP constants to avoid conflicts
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.

Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.

This fixes the 'mtrr' command when CONFIG_SMP is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:50:04 +08:00
Simon Glass
92873f83d1 x86: Don't set up MTRRs if previously done
When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.

Skip that step in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15 19:50:00 +08:00
Pali Rohár
cbd7ef70bc arm: a37xx: pci: Optimize a3700_fdt_fix_pcie_regions() when fixup offset is zero
If fixup offset is zero then there is nothing to fix. All calculation in
this case just increase addresses by value zero which results in identity.
So in this case skip whole fixup re-calculation as it is not needed.

This is just an optimization for special case when fix_offset is zero which
skips code path which does only identity operations (meaning nothing). No
functional changes.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-07-15 10:53:05 +02:00
Stephan Gerhold
e2f82f93f8 board: stemmy: Copy atags for booting downstream/vendor kernel
The U-Boot "stemmy" board is mainly intended to simplify booting
mainline Linux on various smartphones from Samsung based on ST-Ericsson
Ux500. While the mainline kernel is working great, there are still some
features missing there. In particular, it is currently not possible to
charge the battery when using the mainline kernel.

This means that it is still necessary to boot the downstream/vendor
kernel from Samsung sometimes to charge the device. That kernel is
ancient, still uses board files + ATAGS instead of device trees and
relies on a strange very long kernel command line hardcoded in the
Samsung bootloader.

Actually, since mainline is booted with device trees there is a very
simple way to make the old downstream kernel work as well: We can
simply take most of the ATAGS passed to U-Boot from the Samsung
bootloader and copy them as-is when booting a kernel without device
tree. That way the long command line and other needed ATAGS are copied
as-is without having to bother with them.

The only exception is the ATAG_INITRD - since the initrd is loaded
by U-Boot, the atag for that should be generated in U-Boot so it points
to the correct address. All other ATAGS are copied as-is and not
generated in U-Boot.

Also use the chance and provide a serial# for U-Boot by parsing the
ATAG_SERIAL that is also passed by the Samsung bootloader.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-14 16:48:12 -04:00
Stephan Gerhold
03585d52fc board: stemmy: Parse atags to get available memory
At the moment the "stemmy" board attempts to detect the RAM size with
a simple memory test (get_ram_size()). Unfortunately, this does not work
correctly for devices with 768 MiB RAM (e.g. Samsung Galaxy Ace 2
(GT-I8160), "codina"). Reading/writing memory after the 768 MiB RAM
succeeds but actually overwrites some earlier parts of the memory.

For U-Boot this does not result in any major problems, but on Linux
this will eventually lead to strange crashes because of the memory
corruption.

Since the "stemmy" U-Boot port is designed to be chainloaded from
the original Samsung bootloader, the most reliable way to get the
available amount of RAM is to look at the ATAGS passed by the Samsung
bootloader. Fortunately, the header used to generate ATAGS in U-Boot
(asm/setup.h) can also be easily used to parse them.

Also clarify and simplify stemmy.h a bit to make it more clear where
some of the magic values in there are actually coming from.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-14 16:48:11 -04:00
Kunihiko Hayashi
9e9074bcdd ARM: dts: uniphier: Add support for Akebi96
Add the device tree for Akebi96. Akebi96 is a 96boards certified
development board based on UniPhier LD20.
( https://www.96boards.org/product/akebi96/ )

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14 16:48:10 -04:00
Stephan Gerhold
548b89f8ad arm: mach-snapdragon: pinctrl: Place pin_name in .data section
According to arch/arm/lib/crt0_64.S, the BSS section is "UNAVAILABLE"
and uninitialized before relocation. Also, it overlaps with the
appended DTB before relocation, so writing data into a variable
in the BSS section might corrupt the appended DTB.

Unfortunately, pinctrl-apq8016.c and pinctrl-apq8096.c do place the
"pin_name" variable in the BSS section (since it's uninitialized).
It's also used before relocation, when setting up the pinctrl for
the serial driver.

On DB410c this causes "GPIO_5" to be written into some part of an
appended DTB, e.g.:

80111820: edfe0dd0 9f100000 38000000 c00e0000    ...........8....
80111830: 28000000 11000000 10000000 00000000    ...(............
80111840: 4f495047 8800355f 00000000 00000000    GPIO_5..........
80111850: 00000000 00000000 01000000 00000000    ................
80111860: 03000000 04000000 00000000 02000000    ................
80111870: 03000000 04000000 0f000000 02000000    ................
80111880: 03000000 2d000000 1b000000 6c617551    .......-....Qual
80111890: 6d6d6f63 63655420 6c6f6e68 6569676f    comm Technologie

Depending on the part of the DTB that is corrupted this might not
cause any problems, but it can also result in strange reboots
without any serial output.

Fortunately, in practice this does not cause issues on DB410c yet
because board_fdt_blob_setup() in dragonboard410c.c currently
overrides the appended DTB with the one passed by the previous
bootloader (LK) (which does not get corrupted).

DB820c does not have board_fdt_blob_setup() so I would expect it to
be affected by this problem. Perhaps everyone was just fortunate to
not compile an U-Boot configuration where the pin_name corrupts an
important part of the DTB.

Make sure "pin_name" is explicitly placed in the .data section
instead of .bss to fix this.

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-14 16:48:01 -04:00
Marek Vasut
a5ee05cf71 ARM: imx: Pick correct eMMC boot partition from ROM log
In case the iMX8M boot from eMMC boot partition and the primary image
is corrupted, the BootROM is capable of starting a secondary image in
the other eMMC boot partition as a fallback.

However, the BootROM leaves the eMMC BOOT_PARTITION_ENABLE setting as
it was, i.e. pointing to the boot partition containing the corrupted
image, and the BootROM does not provide any indication that this sort
of fallback occured.

According to AN12853 i.MX ROMs Log Events, Rev. 0, May 2020, it is
possible to determine whether fallback event occurred by parsing the
ROM event log. In case ROM event ID 0x51 is present, fallback event
did occur.

This patch implements ROM event log parsing and search for event ID
0x51 for all iMX8M SoCs, and based on that corrects the eMMC boot
partition selection. This way, the SPL loads the remaining boot
components from the same eMMC boot partition from which it was
started, even in case of the fallback.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Harald Seiler <hws@denx.de>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
2021-07-10 18:12:42 +02:00
Tim Harvey
1cb87b929e arm: dts: imx8mm-venice-gw7901.dts: fix dsa switch configuration
Fix the dsa switch config:
- remove the unnecessary phy-mode from the switch itself
- added the necessary fixed-link node to the non-cpu ports required
  for U-Boot DSA

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10 18:12:42 +02:00
Tim Harvey
c9f7ef37f9 board: gateworks: venice: add imx8mm-gw7901 support
The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
 - i.MX8M Mini SoC
 - LPDDR4 DRAM
 - eMMC FLASH
 - SPI FRAM
 - Gateworks System Controller (GSC)
 - Atmel ATECC Crypto Authentication
 - USB 2.0
 - Microchip GbE Switch
 - Multiple multi-protocol RS232/RS485/RS422 Serial ports
 - onboard 802.11ac WiFi / BT
 - microSD socket
 - miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets
 - Wide range DC power input
 - 802.3at PoE

To add support for this board:
 - add dts from Linux (accepted for v5.14)
 - add SPL PMIC config

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10 18:12:41 +02:00
Kacper Kubkowski
a5dc91febd arm/mach-imx: Fix macros in mmdc_size.c
Make macros actually use passed parameter instead of local variables
that happen
to be named the same as symbols in macro expansion.

Signed-off-by: Kacper Kubkowski <kkubkowski@fluence.pl>
2021-07-10 16:53:34 +02:00
Teresa Remmet
bbf04b28d2 board: phytec: imx8mp-phycore: Switch to binman
Use now binman for image creation.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10 16:53:34 +02:00
Teresa Remmet
f11e3dafb3 arm: dts: imx8mp-phyboard-pollux-rdk-u-boot: Add wdog pinctrl entry
Add missing pinctrl entry in spl.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-07-10 16:53:34 +02:00
Teresa Remmet
1feac813fe board: phytec: phycore_imx8mp: Change debug UART
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10 16:53:34 +02:00
Teresa Remmet
3240d9c63a arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel
This update includes eqos support and some minor changes.

Synced with kernel commit
412627f6ffe3 ("arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl entry")

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10 16:53:34 +02:00
Teresa Remmet
dafb164f61 arm: dts: imx8mp: Add common u-boot dtsi
Factor out the common node settings for dm-spl and dm-pre-reloc
and move them to imx8mp-u-boot.dtsi

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10 16:53:34 +02:00
Teresa Remmet
6bd1db0a0c arm: dts: imx8mp: Resync imx8mp device tree include
Sync imx8mp include with kernel commit:
d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps, dwc3"")

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10 16:53:34 +02:00
Tim Harvey
c1f6fd2bb7 pci: imx: use reset-gpios if defined by device-tree
If reset-gpio is defined by device-tree use that if
CONFIG_PCIE_IMX_PERST_GPIO is not defined.

Note that after this the following boards which define
CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
 - mx6sabresd
 - mx6sxsabresd
 - novena
 - tbs2910
 - vining_2000

Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does
not have reset-gpios defined it it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds
reset-gpios.

Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD)
Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD)
Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-07-10 16:53:34 +02:00
Frieder Schrempf
e27bddff4b imx8m: Restrict usable memory to space below 4G boundary
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.

We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the
whole family is affected by this.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-07-10 16:03:01 +02:00
Tom Rini
490101a5e5 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Aside from the usual fixes and updates one visible change is the
MMC update, which fixes some lingering bugs and gives a decent speed
increase on some boards (9->19 MB/s on H6, 21->43 MB/s on A64 eMMC).
I am keeping an watchful eye on bug reports here, to spot any correctness
regressions.
Another change is finally the enablement of the first USB host port on
many boards without micro-USB (data) sockets, like the Pine64 family.
That doubles the number of usable USB ports from 1 to 2 on those boards.

Some smaller fixes, 4GB DRAM support (on the H616) and a new board (ZeroPi)
conclude this first round of changes.

Compile-tested for all 157 sunxi boards, boot-tested on Pine H64,
Pine64-LTS, OrangePi Zero 2 and BananaPi M2 Berry.

Summary:
- DT update for H3/H5/H6
- Enable first USB port on boards without micro-USB
- ZeroPi board support
- 4GB DRAM support for H616 boards
- MMC fixes and speed improvement
- some fixes
2021-07-09 21:08:52 -04:00
Andre Przywara
9faae5457f mmc: sunxi: Increase MMIO FIFO read performance
To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.

However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).

As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.

To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.

We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.

This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
b6e3bf1e0d mmc: sunxi: Enable "new timing mode" on all new SoCs
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so
called "new timing mode", so enable this in Kconfig for those SoCs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
937ee31e32 mmc: sunxi: Fix MMC clock parent selection
Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.

Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.

Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
b8747854de sunxi: H616: Enable full 4GB of DRAM
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.

Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.

As not all devices are actually capable of dealing with more than 32
bits (the DMA in the EMAC for instance), we also limit U-Boot's own
DRAM usage to 4GB on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Yu-Tung Chang
2527b24f39 sunxi: h3: Add initial ZeroPi support
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.

ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply

Signed-off-by: Yu-Tung Chang <mtwget@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
f9d1324775 sunxi: clock: H6/H616: Fix PLL clock factor encodings
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.

This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000

Also the CPU frequency (PLL1) was a tad too high before.

For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
8fcf1fa246 arm: dts: sunxi: h3: Update DT files
Update the H3 DT files from the Linux 5.12 release.

The changes update some boards, and don't affect U-Boot, but fix Gigabit
Ethernet when this DT is passed on to the Linux kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
58f68611df arm: dts: sunxi: h5: Update DT files
Update the H5 DT files from the Linux 5.12 release.

The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
this DT is passed on to the Linux kernel. It also introduces DVFS.

This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
that are of no concern to U-Boot.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Andre Przywara
127e57c671 arm: dts: sunxi: h6: Update DT files
Update the H6 DT files from the Linux 5.12 release.

The changes are minimal (many LED node renames), but also help to enable
USB port 0 in U-Boot (later), enable the RSB device (not yet used in
U-Boot), and also introduce an MMC frequency limit.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Tom Rini
f7b845bfe0 arm: armv8: Fix warning about redeclaring global functions as weak
As seen with clang-12:
warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK

As we indeed use ENTRY and then declare the function weak manually.  Use
the WEAK declarative from <linux/linkage.h> instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-09 12:15:41 -04:00
Marek Vasut
2359fa7a87 arm: bootm: Disable LMB reservation for command line and board info on arm64
On arm64, board info is not applicable and kernel command line patched into
the DT, so the LMB reservation here makes no sense anymore. On legacy arm32,
this might still be necessary on systems which do not use DT or use legacy
ATAGS. Disable this LMB reservation on arm64.

This also permits Linux DT to specify reserved memory node at address close
to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after
boot, U-Boot will be no more, this is OK.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>
2021-07-09 12:15:41 -04:00
Patrice Chotard
ee0fbf4ef7 arch: cache: cp15: Add mmu_set_region_dcache_behaviour() when SYS_DCACHE_OFF is enable
Fix following compilation issue when SYS_DCACHE_OFF is enable:
drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour'

when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be
defined.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-07-09 11:36:12 -04:00
Mark Kettenis
bfb798461a armv8: Handle EL2 Host mode
On implementations that support VHE, the layout of the CPTR_EL2
register depends on whether HCR_EL2.E2H is set.  If the bit is
set, CPTR_EL2 uses the same layout as CPACR_EL1 and can in fact
be accessed through that register.  In that case, jump to the
EL1 code to enable access to the FP/SIMD registers.  This allows
U-Boot to run on systems that pass control to U-Boot in EL2 with
EL2 Host mode enabled such as machines using Apple's M1 SoC.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Marc Zyngier <maz@kernel.org>
2021-07-09 11:36:12 -04:00
Tom Rini
4ee73b00ba Revert "arm: Remove nsa310s board"
While this platform has not yet been converted, there is active efforts
to do so.  Keep the platform for now.

This reverts commit aa697e6904.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:55:41 -04:00
Tom Rini
570c3dcfc1 arm: Remove spear600 boards and the rest of SPEAr support
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
d7221d0d66 arm: Remove spear320 boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
also the last SPEAR3XX platform, remove that symbol as well.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
1dc77c290f arm: Remove spear310 boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
0e377bbabb arm: Remove spear300 boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
aa697e6904 arm: Remove nsa310s board
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove it

Cc: Gerald Kerma <dreagle@doukki.net>
Cc: Tony Dinh <mibodhi@gmail.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
dee08b1999 arm: Remove gplugd board
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove it

Cc: Ajay Bhargav <contact@8051projects.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
bc08dc563e arm: Remove edb9315a board
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove it.

This is also the last PL010_SERIAL using board, so remove those
references.

Cc: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
f4a6f75b48 arm: Remove at91rm9200ek boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.

Cc: Andreas Bießmann <andreas@biessmann.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 22:22:42 -04:00
Tom Rini
ec6b37cef4 ppc: Remove T4160RDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the last
ARCH_T4160 platform, remove that support as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:24 -04:00
Tom Rini
1567e3255d ppc: Remove MPC832XEMDS boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:24 -04:00
Tom Rini
6c332e2b8c ppc: Remove MPC8323ERDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:24 -04:00
Tom Rini
139ff3be23 ppc: Remove MPC8315ERDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the last
ARCH_MPC8315 platform, remove that support as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:24 -04:00
Tom Rini
1c58857ad7 ppc: Remove sbc8641d board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  This is also the last
of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.

Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-07 19:52:24 -04:00
Tom Rini
ed7fe2bee1 ppc: Remove xpedite boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove them.  As this includes
the last ARCH_MPC8572 platform, remove that as well.

Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
2021-07-07 19:52:24 -04:00
Tom Rini
806968935c ppc: Remove MPC8568MDS board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the last
ARCH_MPC8568 platform, remove that support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
6c3d99335c ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the only ARCH_T1023 platform left, remove that support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
98898601b4 ppc: Remove MPC8555CDS boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove them.  As this is the only
ARCH_MPC8555 platform left, remove that support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
a8571337d7 ppc: Remove MPC8541CDS board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.  As this is the only
MPC8541 target left, remove that architecture support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
5fe4c0cc6e ppc: Remove TQM834x board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM.  Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
bb656c687b ppc: Remove sbc8548 boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and are
also missing conversion to CONFIG_DM.  Remove them.

Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
6843862342 ppc: Remove caddy2 / vme8349 boards
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.

Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
7458f18e5c ppc: Remove MPC8313ERDB boards
These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
af96210ae7 ppc: Remove ve8313 board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
2021-07-07 19:52:23 -04:00
Tom Rini
b617d40c50 ppc: Remove mpc8308_p1m board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.

Cc: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
008e9965a5 ppc: Remove many T104x boards
These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or
in some cases CONFIG_DM itself by the deadline.  Remove them.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
3588e20060 ppc: Remove sbc8349 board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:23 -04:00
Tom Rini
9b7993bba9 m68k: Remove M5475x boards
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them.  As this is the last of the mcf547x_8x family of boards,
remove that support as well.

Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:22 -04:00
Tom Rini
eb83d10b42 m68k: Remove M5485 boards
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them.  As this is all of the CONFIG_M548x platforms as well,
remove that code.

Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 19:52:08 -04:00
Tom Rini
7e58a3a148 various minor sandbox improvements
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Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dm

various minor sandbox improvements
2021-07-07 13:34:42 -04:00
Tom Rini
5b8a83551d Merge branch '2021-07-06-update-to-gcc11-clang11'
- Update CI to use gcc-11.1 and clang-11 to build everything.  This
  requires a few fixes to the code that these newer compilers have
  exposed.
2021-07-07 13:32:22 -04:00
Tom Rini
54fb6e396d Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-07-07 11:34:29 -04:00
Bin Meng
cfa5189811 x86: Drop _X86EMU_env definition when CONFIG_BIOSEMU is used
With x86 we can execute an option ROM either natively or using the
x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share
the _X86EMU_env variable, with the native code using it to hold
register state during interrupt processing.

At present, in 32-bit U-Boot, the variable is declared twice, once
in common code and once in code only compiled with CONFIG_BIOSEMU.

With GCC 11 this causes a 'multiple definitions' error on boards
with CONFIG_BIOSEMU.

Drop the emulator definition when CONFIG_BIOSEMU is used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-07 10:17:54 -04:00
Tom Rini
cb80ff20f2 bootstage: Eliminate when not enabled
When we do not have bootstage enabled, rather than include an empty
dummy function, we just don't reference it.  This saves us space in some
tight builds.  This also shows a few cases where show_boot_progress was
incorrectly guarded before.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-07 10:17:54 -04:00
Tom Rini
008604c3b8 First set of u-boot-atmel fixes for 2021.10 cycle
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Merge tag 'u-boot-atmel-fixes-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2021.10 cycle:

This small fixes set is dedicated to fixing the onewire subsystem for
the at91 boards which was broken since 2020.04.
2021-07-07 08:52:14 -04:00
Tianrui Wei
c9135d5a7a riscv: dts: add OpenPiton RISC-V board dts support
Previous device tree for OpenPiton emits a warning during compilation.
This commit fixes the previous warning adds dts to the OpenPiton RISC-V
board and added the device tree to MAINTAINER file.

Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-07 20:34:02 +08:00
Tom Rini
5617efd2c8 Merge branch '2021-07-06-platform-updates'
- mpc8379erdb DM_USB, DM_PCI and DM_ETH support.
- Drop PCI support from the integrator family of boards
- Add synquacer support
- Assorted lpc32xx updates and improvements
- snapdragon (and related) fixes, Broadcom iproc update
2021-07-06 18:10:10 -04:00
Stephan Gerhold
698c1df4d1 arm: dts: db410c: Add missing cd-gpios for SD card detection
It looks like SD card detection is broken at the moment for DB410c.
The eMMC is detected correctly, but the SD card is not.

This is probably similar to the issue fixed in commit 8505147403
("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC,
except that the SD card does not have a property like "non-removable"
that skips the card detection.

The SDHCI on DB410c cannot detect itself if a SD card is inserted,
so add the necessary cd-gpios to make SD card detection work again.

While at it, fix the #gpio-cells for the soc_gpios to avoid DTC
warnings - the soc_gpios are actually already used with two cells
for the gpio-leds so this was just wrong all the time.

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 14:12:15 -04:00
Sheep Sun
6d430e11a8 arm: snapdragon: Fix typo in clk_bcr_update()
Fix typo in clock-snapdragon.c

Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
2021-07-06 14:12:15 -04:00
Sheep Sun
9b6b25c635 arm: snapdragon: Use correct GICC register on APQ8016
The GICC register used by u-boot is 0x0a20c000, which is actually a GICC
for WCNSS, the WLAN processor. U-boot runs on the Application Processor,
therefore it should use APCS GICC instead. Hence, correct it with APCS GICC
register address.

Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
2021-07-06 14:12:15 -04:00
Trevor Woerner
faf78fd464 arm: lpc32xx: add EA LPC3250 DevKitv2 board support
Add basic support for running U-Boot on the Embedded Artists LPC3250
Developer's Kit v2 board by launching U-Boot from the board's s1l loader
(which comes pre-installed on the board).

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06 14:12:14 -04:00
Trevor Woerner
eb5807e68f lpc32xx: import device tree from Linux
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board
directly and unmodified from the latest Linux kernel.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2021-07-06 14:11:50 -04:00
Trevor Woerner
bd4dbf9e43 lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX
There's nothing special or unique to the lpc32xx that requires its own config
parameter for specifying the console uart index. Therefore instead of using
the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
already-available CONFIG_CONS_INDEX from Kconfig.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 14:11:50 -04:00
Masami Hiramatsu
5cd4a355e0 board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.

For more information, see this page;
  https://www.96boards.org/product/developerbox/

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06 14:11:50 -04:00
Masami Hiramatsu
2f1f797efa ARM: dts: synquacer: Add device trees for DeveloperBox
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2

commit 83d38b0b4c0f240d4488c600bbe87cea391f3922

as-is (except for the changes #include path and some macros).

And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06 14:11:49 -04:00
Masami Hiramatsu
7a672057dc gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
Since some SoCs and boards do not hae extra asm/arch/gpio.h,
introduce CONFIG_GPIO_EXTRA_HEADER instead of adding
!define(CONFIG_ARCH_XXXX) in asm/gpio.h.

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-07-06 14:07:36 -04:00
Chris Packham
9fe79ca0ac arm: iproc: Add higher speed configurations
Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on
equivalent code in Broadcom's LDK 5.0.6.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2021-07-06 14:07:36 -04:00
Sinan Akman
c8be85f3ff mpc8379erdb: enable DM_USB DM_PCI DM_ETH
Signed-off-by: Sinan Akman <sinan@writeme.com>
2021-07-06 14:07:36 -04:00
Alper Nebi Yasak
e712245d08 sandbox: cros-ec: Add tests for the Chromium OS EC PWM driver
This patch adds a limited pulse-width modulator to sandbox's Chromium OS
Embedded Controller emulation. The emulated PWM device supports multiple
channels but can only set a duty cycle for each, as the actual EC
doesn't expose any functionality or information other than that. Though
the EC supports specifying the PWM channel by its type (e.g. display
backlight, keyboard backlight), this is not implemented in the emulation
as nothing in U-Boot uses this type specification.

This emulated PWM device is then used to test the Chromium OS PWM driver
in sandbox. Adding the required device node to the sandbox test
device-tree unfortunately makes it the first PWM device, so this also
touches some other tests to make sure they still use the sandbox PWM.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Heinrich Schuchardt
825a9a94e1 sandbox: fix sandbox_reset()
state_uninit() and dm_uninit() are mutually exclusive:

state_uninit() prints via drivers. So it cannot be executed after
dm_uninit().

dm_uninit() requires memory. So it cannot be executed after state_uninit()
which releases all memory.

Just skip dm_uninit() when resetting the sandbox. We will wake up in a new
process and allocate new memory. So this cleanup is not required. We don't
do it in sandbox_exit() either.

This avoids a segmentation error when efi_reset_system_boottime() is
invoked by a UEFI application.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Heinrich Schuchardt
3beba4ad34 sandbox: ensure that state->ram_buf is in low memory
Addresses in state->ram_buf must be in the low 4 GiB of the address space.
Otherwise we cannot correctly fill SMBIOS tables. This shows up in warnings
like:

    WARNING: SMBIOS table_address overflow 7f752735e020

Ensure that state->ram_buf is initialized by the first invocation of
os_malloc().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Simon Glass
85f718f64d sandbox: Support signal handling only when requested
At present if sandbox crashes it prints a message and tries to exit. But
with the recently introduced signal handler, it often seems to get stuck
in a loop until the stack overflows:

Segmentation violation

Segmentation violation

Segmentation violation

Segmentation violation

Segmentation violation

Segmentation violation

Segmentation violation
...

The signal handler is only useful for a few tests, as I understand it.
Make it optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Tom Rini
b5f9d2f3aa Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-07-06 12:22:39 -04:00
Zong Li
ffe9a394df riscv: dts: add dts for unmatched rev1
The difference between unmatched rev3 and rev1 is DDR timing, the rev3
uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06 20:24:26 +08:00
Zong Li
05e254862f board: sifive: Add an interface to get PCB revision
There are different DDR parameter settings for different board
revisions. Add a new interface to get the PCB revision to determine
which DT should be selected at runtime.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06 20:24:25 +08:00
Zong Li
564d630e26 riscv: sifive: fu740: Support i2c in spl
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
i2c node.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06 20:24:25 +08:00
Zong Li
e2172aa83d riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller
Enable the Opencores I2C controller on FU740

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06 20:24:25 +08:00
Eugen Hristev
89bd68a748 ARM: dts: at91: fix the GPIO polarity for onewire
The GPIO polarity for onewire must be GPIO_ACTIVE_HIGH.
On previous versions this used to work as it looks like the right flag values
are being passed since :
https://lists.denx.de/pipermail/u-boot/2020-April/407195.html

And that series broke the old functionality for onewire nodes.
Some boards had the correct value for the polarity, but it wasn't clear
so I replaced it with the right macro for the flag, instead of an empty value.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-07-06 15:17:10 +03:00
Tianrui Wei
8a44fe6943 board: riscv: add openpiton-riscv64 SoC support
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper

Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06 13:50:56 +08:00
Michael Walle
515ed9df24 board: sl28: add DSA support for variant 2
Now that u-boot gained DSA support, and it is already enabled for the
kontron_sl28 board, add the last missing piece and enable the
corresponding devices it in the device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
bec7d5342d arm: dts: ls1028a: disable enetc-2 by default
The enetc-2 port is used as DSA master (connected back-to-back to
mscc_felix_port4). Since the convention is to not enable ports in the
common SoC dtsi unless they are used on the board, then enable enetc-2
only when mscc_felix_port4 itself is enabled.

All existing device trees appear to adhere to this rule, so disable
enetc-2 in the SoC dtsi.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
9feb636680 arm: dts: ls1028a: declare the fixed-link speeds for the internal ENETC ports
To comply with the device tree bindings expectations for an Ethernet
controller, as well as to simplify the driver code, declare fixed-link
nodes for the internal ENETC ports (attached to the mscc_felix switch).

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
aee4479a85 arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS AR8035 PHY
There are no PCB trace delays on this board, so the PHY needs to enable
its internal ones in order to have a proper electrical connection to the
enetc MAC.

Fixes: b32e9a7578 ("arm: dts: ls1028a updates for network interfaces")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Vladimir Oltean
39dca76c34 arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDS
Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix
switch got accepted with all ports disabled by default and with no link
to the DSA master - this needs to be done on a per board basis.

Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but
presumably at some point it might become. Explicitly enable it in the
QDS device trees anyway, to proactively avoid issues when that happens.

Fixes: a7fdac7e2a ("arm: dts: ls1028a: define QDS networking protocol combinations")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-07-06 05:22:41 +03:00
Tom Rini
6b69f15fd6 Xilinx changes for v2021.10
clk:
 - Add driver for Xilinx Clocking Wizard IP
 
 fdt:
 - Also record architecture in /fit-images
 
 net:
 - Fix plat/priv data handling in axi emac
 - Add support for 10G/25G speeds
 
 pca953x:
 - Add missing dependency on i2c
 
 serial:
 - Fix dependencies for DEBUG uart for pl010/pl011
 - Add setconfig option for cadence serial driver
 
 watchdog:
 - Add cadence wdt expire now function
 
 zynq:
 - Update DT bindings to reflect the latest state and descriptions
 
 zynqmp:
 - Update DT bindings to reflect the latest state and descriptions
 - SPL: Add support for ECC DRAM initialization
 - Fix R5 core 1 handling logic
 - Enable firmware driver for mini configurations
 - Enable secure boot, regulators, wdt
 - Add support xck devices and 67dr
 - Add psu init for sm/smk-k26 SOMs
 - Add handling for MMC seq number via mmc_get_env_dev()
 - Handle reserved memory locations
 - Add support for u-boot.itb generation for secure OS
 - Handle BL32 handoffs for secure OS
 - Add support for 64bit addresses for u-boot.its generation
 - Change eeprom handling via nvmem aliases
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Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.10

clk:
- Add driver for Xilinx Clocking Wizard IP

fdt:
- Also record architecture in /fit-images

net:
- Fix plat/priv data handling in axi emac
- Add support for 10G/25G speeds

pca953x:
- Add missing dependency on i2c

serial:
- Fix dependencies for DEBUG uart for pl010/pl011
- Add setconfig option for cadence serial driver

watchdog:
- Add cadence wdt expire now function

zynq:
- Update DT bindings to reflect the latest state and descriptions

zynqmp:
- Update DT bindings to reflect the latest state and descriptions
- SPL: Add support for ECC DRAM initialization
- Fix R5 core 1 handling logic
- Enable firmware driver for mini configurations
- Enable secure boot, regulators, wdt
- Add support xck devices and 67dr
- Add psu init for sm/smk-k26 SOMs
- Add handling for MMC seq number via mmc_get_env_dev()
- Handle reserved memory locations
- Add support for u-boot.itb generation for secure OS
- Handle BL32 handoffs for secure OS
- Add support for 64bit addresses for u-boot.its generation
- Change eeprom handling via nvmem aliases
2021-07-01 08:57:23 -04:00
Tom Rini
8fba49bc8e Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next
- V3U Falcon board support
2021-06-28 18:32:07 -04:00
Tom Rini
6d0453d889 Prepare v2021.07-rc5
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Merge tag 'v2021.07-rc5' into next

Prepare v2021.07-rc5

# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	configs/am64x_evm_r5_defconfig
2021-06-28 16:22:13 -04:00
Kunihiko Hayashi
534f0fbd65 arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y
If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled,
wherever original env is placed anywhere, it should be relocated to
the right address.

Relocation offset gd->reloc_off is calculated with SYS_TEXT_BASE in
setup_reloc() and env address gd->env_addr is relocated by the offset in
initr_reloc_global_data().

gd->env_addr
  = (orig env) + gd->reloc_off
  = (orig env) + (gd->relocaddr - SYS_TEXT_BASE)

However, SYS_TEXT_BASE isn't always runtime base address when
POSITION_INDEPENDENT is enabled. So the relocated env_addr might point to
wrong address. For example, if SYS_TEXT_BASE is zero, gd->env_addr is
out of memory location and memory exception will occur.

There is a difference between linked address such as SYS_TEXT_BASE and
runtime base address. In _main, the difference is calculated as
"run-vs-link" offset. The env_addr should also be added to the offset
to fix the address.

gd->env_addr
  = (orig env) + ("run-vs-link" offset)   + gd->reloc_off
  = (orig env) + (SYS_TEXT_BASE - _start) + (gd->relocaddr - SYS_TEXT_BASE)
  = (orig env) + (gd->relocaddr - _start)

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
2021-06-28 14:47:10 -04:00
Piyush Mehta
436978b1d8 arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node
This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for
zc1751-xm017-dc3 board.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-28 09:35:27 +02:00
Tom Rini
4d8c21da41 Fixes for 2021.07
-----------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7903
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Merge tag 'u-boot-imx-20210625' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2021.07
-----------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7903
2021-06-25 13:33:47 -04:00
Adam Ford
12ef801673 ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards
The board detection is incorrectly stating it's an rcar3 variant
instead of an RZ/G2 variant on all the r8a774*1_beacon boards.
Set the flag to correctly display as RZ/G2[M/N/H]

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-06-24 20:22:31 +02:00
Hai Pham
0beaae223d ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon
Enable basic PSCI support for R8A779A0 V3U Falcon

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:18 +02:00
Hai Pham
4cfdcf3948 ARM: renesas: Add R8A779A0 V3U Falcon board code
Add board code for the R8A779A0 V3U Falcon board.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
--
Marek: - various small rebase fixes and clean ups
2021-06-24 20:22:18 +02:00
Hai Pham
0f08fa4964 ARM: renesas: Add R8A779A0 V3U platform code
Add platform code to support R8A779A0 V3U SoC.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:18 +02:00
Marek Vasut
ae3c0d42fa ARM: dts: renesas: Add RPC node to R8A779A0 V3U
The R-Car V3U does support RPC interface, however the support for it is
missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"),
add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:18 +02:00
Hai Pham
b35fc0dabd ARM: dts: renesas: Add R8A779A0 V3U DT extras
Add R8A779A0 V3U DT extras for U-Boot.

Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs"
by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:17 +02:00
Marek Vasut
6232d0a740 ARM: dts: renesas: Add R8A779A0 V3U Falcon DTs
Import R8A779A0 V3U Falcon DTs from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:17 +02:00
Marek Vasut
b6ec11b62d ARM: dts: renesas: Add R8A779A0 V3U DTs and headers
Import R8A779A0 V3U DTs and headers from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-06-24 20:22:17 +02:00
Tom Rini
fcf3981161 Merge https://source.denx.de/u-boot/custodians/u-boot-x86
- x86: Discard .note.gnu.property sections
- nvme: Skip block device creation for inactive namespaces
- nvme: Convert NVMe doc to reST, and various minor fixes
2021-06-23 08:46:26 -04:00
Tom Rini
076c7bfb1f global_data: Ensure we have <config.h> when symbols are not in Kconfig yet
All symbols that are defined in Kconfig will always be defined (or not)
prior to preprocessing due to the -include directive while building.
However, symbols which are not yet migrated will only be defined (or
not) once the board config.h is included, via <config.h>.  While the end
goal must be to migrate all symbols, today we have cases where the size
of gd will get mismatched within the build, based on include order.
Mitigate this by making sure that any <asm/global_data.h> that uses
symbols not in Kconfig does start with <config.h>.  Remove this when not
needed.

Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Huan Wang <alison.wang@nxp.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-06-23 08:45:03 -04:00
Tom Rini
8f0f26eb59 Revert "powerpc: fix regression in arch_initr_trap()"
With the changes in commit 588efcdd72fc ("powerpc: Don't use relative
include for config.h in global_data.h") fixing the root of the problem,
we no longer need this re-inclusion.

This reverts commit f6c0d365d3.

Cc: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-06-23 08:45:03 -04:00
Tom Rini
8b95deafc5 powerpc: Don't use relative include for config.h in global_data.h
As there is an arch/powerpc/include/asm/config.h file using "" to get
config.h here can lead to using that rather than include/config.h.  This
in turn can lead to a mismatch in the size of gd.

Cc: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
2021-06-23 08:45:03 -04:00
Bin Meng
6fbe06a6ce x86: Discard .note.gnu.property sections
When switching to kernel.org x86_64 gcc 11.1.0 toolchain, u-boot.rom
built from qemu-x86_defconfig no longer boots anymore. Investigation
shows that U-Boot fails at a very early stage during the boot process,
in fdtdec_prepare_fdt() where fdt_check_header() complains that there
is not a valid device tree found at gd->fdt_blob which points to _end.
Now _end points to an allocated section .note.gnu.property which of
course is wrong.

This issue is however not seen when using the default Ubuntu 20.04 gnu
toolchain (gcc 9.3.0 with binutils 2.34). Further investigation shows
that it is caused by a behavior change of binutils v2.36 which is part
of the kernel.org gcc 11.1.0 toolchain, via the following commit:

  939b95c77bf2 ("Linux/x86: Configure gas with --enable-x86-used-note by default")

In fact, there was already a regression bug report [1] for binutils two
months ago, but the binutils folks did not think it is a bug :(

To resolve this, there are several options:

* pass -Wa,-mx86-used-note=no to gas
* pass -R .note.gnu.property to objcopy
* discard the section in the linker script

Linux kernel uses the discard way [2], so let's do the same for U-Boot.

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=27753
[2] commit 4caffe6a28d3 ("x86/vdso: Discard .note.gnu.property sections in vDSO")

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-06-23 17:21:14 +08:00
Michal Simek
3972ae65e4 arm64: zynqmp: Add missing year in Kria dts files
DT files have been added this year but forgot to update it that's why do it
in separate patch now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
9899f3e6b9 arm64: zynqmp: Add psgtr description to zc1751 dc1 board
Wire psgtr for zc1751 dc1 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
52caf2c12b arm64: zynqmp: Remove gpio from aliases list
It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
83dc13384b arm64: zynqmp: Enable USB3.0 for dc2/dc3
Both boards are usb3.0 capable. dc3 was also missing enabling dwc3* nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
cb4380abfd arm64: zynqmp: Update usb dwc3 DT description
Align USB nodes with the latest dt-bindings. It is adding resets, new
interrupt and also some quirks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
b6d8d4b100 arm64: zynqmp: Use overlay sugar syntax for Kria SOM
dtc supports new sugar syntax which is easier compare to previous one
that's why also covert overlays for SOM to it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
3dbd53144c arm64: zynqmp: Remove revA compatibility string from kv260 revB/1
kv260-revB is different compare to revA (usbhub is wired via i2c) that's
why remove revA compatible string.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
4d3de8abff arm64: zynqmp: Add support for 64bit addresses in its
Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also
generate u-boot.its with 64bit load/entry addresses to also support
different configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
6a2ce6ec24 arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
e0f99280ee arm64: zynqmp: Remove information about dma clock on zcu106
Clock setting is not static anymore that's why it depends on firmware setup
that's why remove this comment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
d245d0dfd8 arm64: zynqmp: Remove unused property from SD/USB
Linux kernel is not using these properties that's why they can be removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
0c79419d35 arm64: zynqmp: Remove can aliases from zc1751
Networking subsystem is not using aliases that's why remove them for CAN
devices. There is also no any other Xilinx ZynqMP DT file with them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
43086886ad arm64: zynqmp: Remove si5328 and si5382 nodes
There are no drivers for these devices that's why remove that nodes
completely. This change is done based on Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com
2021-06-23 09:48:35 +02:00
Michal Simek
531abcb71e xilinx: Convert xlnx,eeprom property to nvmem alias
Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is
done based on discussion in the link below.

Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Srinivas Neeli
ee6b3c54e9 arm64: zynqmp: rtc: Update rtc calibration value
As per the design specification
"The 16-bit Seconds Calibration Value represents the number of
 Oscillator Ticks that are required to measure the largest time
 period that is less than or equal to 1 second.
 For an oscillator that is 32.768 KHz, this value will be 0x7FFF."

Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
5fa9672248 arm64: zynqmp: Sync psgtr location on zcu100/zcu106
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
abd30371d3 arm64: zynqmp: Sync dp port location on zc1751 dc4
Historically dpdma and dpsub are placed at the end of files. Move nodes
there for easier comparison among dts files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
af04516992 arm64: zynqmp: Remove unused dp_aclk clock
dp_aclk is not used anywhere that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
70fbcdb825 arm64: zynqmp: Remove addition newline from zc1751 dc1
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
184309b8c6 arm64: zynqmp: Add maximum-speed property for dwc3 nodes
dwc3 can be used only for higher speeds than super-speed that's why
explicitly set it up.
This is also aligned with other ZynqMP dts files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
7c3ad8f6a3 arm64: zynqmp: Remove additional header from zc1232 DT
Remove unused phy.h from zc1232 DTS.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
02860e1562 zynqmp: Remove u-boot,dm-pre-reloc for uart instances
Uarts already have u-boot,dm-pre-reloc via zynqmp.dtsi that's why there is
no need to have them in platform DT files too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
653736c243 zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure
There is need to pass entry about secure OS when bl32_entry is defined.
Currently only 64bit support is added but /fit-images node have been
extended to also record if this is 32bit or 64bit secure OS. When this is
tested the code will be update to support this configuration too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
84c88d6ef2 zynqmp: Generate u-boot.its also with TEE dynamically
The first change is to trying to find out TF-A load address based on
reading elf file. Expectation is that bl31.bin is in the same folder as
bl31.elf. It brings new flexibility to place TF-A to any address (DDR
included).

And also enable TEE generation also with TEE configuration.
Expecation is the same as above that tee.bin and tee.elf are in the same
folder.

User has to just define link to BL31/BL32 binary files and the rest should
be handled by the script.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
447fb8db02 arm64: zynqmp: Update Copyright years to 2021
Trivial change for all files I have touched recently.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
eca0376b54 arm64: zynqmp: Add label for zynqmp_ipi
Add label which is used by bootloader for adding bootloader specific flag.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Michal Simek
f2b5dd38de arm64: zynqmp: Move DP nodes to the end of file (zcu106)
Just sync it with others for easier comparison.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
fee3e307f2 arm64: zynqmp: Add reset description for sata
Sata needs to get reset before configuration that's why add property for it
there.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Stefano Stabellini
ce42bd2fa3 arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
The SMMU is disabled in device tree so this change has no impact.
The benefit is that this way it is in sync with xen.dtsi. Xen enables
the SMMU and makes use of it.

Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
d9be8b4f2f arm64: zynqmp: Disable CCI by default
There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
1242a6b13d arm64: zynqmp: Update psgtr clocks index for boards
Update the psgtr clock indexing for couple of zynqmp boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
767aa16d41 ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."

Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml

Similar change has been done for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Michal Simek
351b9f5f95 arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285
Enable gpio driver on these boards. GPIOs can be used on any board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Ashok Reddy Soma
aee1ed87e7 arm64: zynqmp: Fix application loading on R5 core1
From U-Boot, loading application on RPU core 0 is fine but loading on
core 1 is not handled properly. Lock-step mode needs both the R5 cores
to be initialized and it is working fine. Whereas in SPLIT mode individual
R5 cores needs to be initialized as they need to execute differenet
applications. Handle both these lock-step and split modes by propagating
mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions
and by adding conditions in those functions.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
e246dc49cf ARM: zynq: Fix OCM mapping to be aligned with binding on zc702
The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to
json-schema") converted binding to yaml and some missing required
properties started to be reported. Align binding based on it.

The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Michal Simek
742fdd1e6b ARM: zynq: Convert at25 binding to new description on zc770-xm013
The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding
document to yaml") converted binding to yaml and 3 deprecated properties
pop up.

The patch is fixing these warnings:
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
>From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml

by converting them to new binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Jorge Ramirez-Ortiz
01c7714a7b zynqmp: spl: support DRAM ECC initialization
Use the ZDMA channel 0 to initialize the DRAM banks. This avoid
spurious ECC errors that can occur when accessing unitialized memory.

The feature is enabled by setting the option
CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data:

 SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize
 SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex)
 SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize
 SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex)

Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Vignesh Raghavendra
95eca8612b ARM: dts: k3-j7200-common-proc-board-u-boot.dtsi: Fix dtc warnings
Fix following dtc warning by explicitly setting up #size-cells
and #address-cells when overriding node in -u-boot.dtsi

arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format):
/bus@100000/bus@28380000/mcu-navss/ringacc@2b800000:reg: property has
invalid length (80 bytes) (#address-cells == 2, #size-cells == 1)

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2021-06-21 13:18:17 -04:00
Fabio Estevam
31b3829f74 o4-imx-nano: Fix dtc warnings
Remove the LED unit addresses and reg properties to
fix the following dtc build warnings:

arch/arm/dts/o4-imx-nano.dtb: Warning (reg_format): /leds/led@0:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
...
arch/arm/dts/o4-imx-nano.dtb: Warning (avoid_default_addr_size): /leds/led@0: Relying on default #address-cells value

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Oleh Kravchenko <oleg@kaa.org.ua>
2021-06-21 13:31:40 +02:00
Tom Rini
28afb71646 Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
- New SoC platform support: rk3568;
- rockchip pcie Code compile issue fix;
- Board fix for rk3399 Khadas Edge;
- Add Rockchip NFC driver;
2021-06-19 08:20:12 -04:00
Michael Walle
82a3c9ef20 net: use the same alias stem for ethernet as linux
Linux uses the prefix "ethernet" whereas u-boot uses "eth". This is from
the linux tree:

$ grep "eth[0-9].*=.*&" arch/**/*dts{,i}|wc -l
0
$ grep "ethernet[0-9].*=.*&" arch/**/*dts{,i}|wc -l
633

In u-boot device trees both prefixes are used. Until recently the only
user of the ethernet alias was the sandbox test device tree. This
changed with commit fc054d563b ("net: Introduce DSA class for Ethernet
switches"). There, the MAC addresses are inherited based on the devices
sequence IDs which is in turn given by the device tree.

Before there are more users in u-boot and both worlds will differ even
more, rename the alias prefix to "ethernet" to match the linux ones.
Also adapt the test cases and rename any old aliases in the u-boot
device trees.

Cc: David Wu <david.wu@rock-chips.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-18 11:29:17 +03:00
Patrick Delaunay
1f2e3d5599 stm32mp: stm32prog: handle dfu error
Handle DFU stack error in STM32CubeProgrammer protocol.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
d4cb402577 stm32mp: stm32prog: change one message level to debug
Move the message "Invalid or missing layout file."
to debug level as it is a normal behavior and not an error
and add the missing '\n'.

This patch avoids the strange trace :
  Boot over usb0!
  Invalid or missing layout file.DFU alt info setting: done

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
69446dee37 stm32mp: stm32prog: use get_cpu_dev for GetID command
Use get_cpu_dev() in uart getID command and remove the defines
DEVICE_ID_BYTE1 and 2 defines.

This patch prepare the support for new SOC family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
b57efb24c9 stm32mp: stm32prog: correctly handle DM_PMIC
Correctly handle number of alternate when DM_PMIC is not activated.
This patch remove the last UNKNOWN partition in this case.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
be4182bf23 stm32mp: stm32prog: handle the next phase after USB re-enumeration
Handle the second USB enumeration only when the flashlayout is received
and when phase is PHASE_FLASHLAYOUT. This patch removes the call of
stm32prog_next_phase as it is already done in stm32prog_dfu_init().

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
90ed215dd5 stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATURE
When CONFIG_FIT_SIGNATURE is activated, CONFIG_LEGACY_IMAGE_FORMAT
is deactivated and the define IMAGE_FORMAT_LEGACY don't exist with
include/image.h:
  #if defined(CONFIG_LEGACY_IMAGE_FORMAT)
  #define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
  #endif

This patch adds the needed check on compilation flag
CONFIG_LEGACY_IMAGE_FORMAT to avoid the compilation error
for command stm32prog:

cmd_stm32prog.c:81:8: error: ‘IMAGE_FORMAT_LEGACY’ undeclared
(first use in this function); did you mean ‘IMAGE_FORMAT_FIT’?
   81 |    if (IMAGE_FORMAT_LEGACY ==
      |        ^~~~~~~~~~~~~~~~~~~
      |        IMAGE_FORMAT_FIT

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
d68e53b279 stm32mp: stm32prog: add support of initrd in flashlayout
Add the support in command stm32prog of kernel load and start
with initrd file, identify by the partition Type "Binary" in
the flashlayout.tsv, for example:

- 0x01 fsbl	Binary none 0x0 tfa.stm32
- 0x03 fip	Binary none 0x0 fip.bin
P 0x10 kernel System ram0 0xC2000000 uImage.bin
P 0x11 dtb FileSystem ram0 0xC4000000 board.dtb
P 0x12 initrd Binary ram0 0xC4400000 <initrd>

The <initrd> file can be a legacy image "uInitrd", generated
with mkimage, or a RAW initrd image "initrd.gz".

After a DFU detach the bootm command with be executed
with the associated address, for example:

$> bootm 0xC2000000 0xC4400000:<size> 0xC4000000

When the "Binary" partition type is absent, the 'bootm'
command starts the kernel without ramdisk, for example:

$> bootm 0xC2000000 - 0xC4000000

With this paths, it is no more mandatory to generate FIT
including the kernel, DT and initrd:

- 0x01 fsbl Binary none 0x0 tfa.stm32
- 0x03 fip Binary none 0x0 fip.bin
P 0x10 fit System ram0 0xC2000000 fit.bin

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
d4358a648c stm32mp: stm32prog: add timeout in stm32prog_serial_get_buffer
Handle timeout in stm32prog_serial_get_buffer to sent NACK
to STM32CubeProgrammer when the buffer is not fully received.

This patch avoids to reach the STM32CubeProgrammer timeout and
the associated unrecoverable error.

  Timeout error occurred while waiting for acknowledgment.

  Error: Write Operation fails at packet number 4165 at address 0x1044FF

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Patrick Delaunay
5f14e2fe9d stm32mp: stm32prog: remove all the header check for UART download
This patch removes the header check for UART download;
the check of checksum is not mandatory with even parity and chuck
checksum for each 256 received bytes and it is only done for
STM32 image (FSBL = TF-A BL2), not for FIT image.

This patch solve issue of duplicated 0x100 byte written with FIP header.

Fixes: 4fb7b3e108 ("stm32mp: stm32prog: add FIP header support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 10:09:41 +02:00
Joseph Chen
695693b2d0 board: rockchip: Add rk3568 evb support
Add support for rk3568 evaluation board.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Joseph Chen
2a950e3ba5 rockchip: Add rk3568 architecture core
RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Joseph Chen
636ffbd25c arm: dts: rockchip: Add dts for rk3568 evb
Add dts for rk3568 evb, sync from the linux kernel
upstream list [0].

[0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Joseph Chen
a4a9ce1660 arm: dts: Sync rockchip-pinconf.dtsi from kernel
Sync from linux kernel:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Elaine Zhang
4a262feba3 rockchip: rk3568: add clock driver
Add rk3568 clock driver and cru structure definition.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:06 +08:00
Grzegorz Szymaszek
95a34eb42e arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL
Enable the SDMMC2 device tree node, as well as the pins it uses, in
U-Boot SPL.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 08:34:16 +02:00
Grzegorz Szymaszek
7db3307848 arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode
Enable the SDMMC2 eMMC high-speed DDR mode as it is done in the
corresponding Linux kernel device tree.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 08:34:16 +02:00
Grzegorz Szymaszek
51a2ac966e arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply
Set the SDMMC2 VQMMC supply to vdd (buck3). Note that in the
corresponding Linux kernel device tree, the supply is set to v3v3
(buck4), which is wrong.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 08:34:16 +02:00
Grzegorz Szymaszek
b1c8ad53f5 arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes
Add the “sdmmc2_d47_pins_d” pins to the SDMMC2 pinctrls. Increase the
bus width from four to eight.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 08:34:16 +02:00
Grzegorz Szymaszek
b40a034a63 arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties
The SDMMC2 interface hosts an eMMC. Replace the interface properties
that would only apply to SD cards—“broken-cd” and “disable-wp”—with
relevant ones: “non-removable”, “no-sd” and “no-sdio”.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-06-18 08:34:16 +02:00
Tom Rini
a94b2aad05 First set of u-boot-atmel features for the 2021.10 cycle
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Merge tag 'u-boot-atmel-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for the 2021.10 cycle:

This feature set converts the boards pm9261 and pm9263 Ethernet support
to DM; enables hash command for all SAM boards; fixes the NAND pmecc
bit-flips correction; adds Falcon boot for sama5d3_xplained board; and
other minor adjustments.
2021-06-17 11:46:44 -04:00
Tom Rini
a298d4fbcd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.
2021-06-17 08:44:56 -04:00
Tom Rini
7e585b5a61 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
- ae350 related dts fixes.
2021-06-17 08:44:23 -04:00
Ran Wang
390c73b417 armv8: Update erratum number to align with doc
Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.

Fixes 0cfa00cdb9 (“armv8: Add workaround for USB erratum A-050106”)
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Camelia Groza
13ea307f79 board: freescale: t208xrdb: add a config option for rev D dts fixups
Under DM, we rely on u-boot's device tree to provide the correct PHY
addresses. The board_fix_fdt callback is intended to be used for
device tree fixups before relocation. Unfortunately, this isn't an
option when booting from flash since the device tree isn't writable
before relocation.

This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a
board revision D or up is the target. The config option is used to set
the correct Aquantia PHY address in the board's u-boot device tree.

Defconfig files with the option enable explicitly are added for
convenience.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Aleksandar Gerasimovski
a7fd6fa1c2 board/km: add support for expu1 design based on nxp
The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.

The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Lasse Klok Mikkelsen
fb6c96f14e arm: dts: ls1021a.dtsi: Fix invalid reg on gpio nodes
Address and size cells on SOC are set to 1. But gpio nodes are specified
with 2 cells. This fixes the gpio nodes to correct cells.

Signed-off-by: Lasse Klok Mikkelsen <lkmi@prevas.dk>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Yangbo Lu
38d1a18750 arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1
Add properties related to eMMC HS400 mode for esdhc1.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Chaitanya Sakinam
ff64e9a9f0 armv8: ls1012a: Pass PPFE firmware to Linux through FDT
Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)

Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Yangbo Lu
addec3511f armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A
Enable eMMC HS400 workarounds for LX2160A/LX2162A.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Jiafei Pan
84c2e044a9 armv8: layerscape: add PSCI support for cpu release
For cpu release command, check whether PSCI is supported firstly,
if supported, use PSCI to kick off secondary cores, otherwise still
use spin table.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
[Fixed checkpatch alignment CHECKs]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-17 11:46:11 +05:30
Sean Anderson
9cd637f84b k210: dts: Set PLL1 to the same rate as PLL0
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:40:58 +08:00
Bin Meng
62ce0a02f9 riscv: andes_plic: Fix riscv_get_ipi() mask
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().

Fixes: 8b3e97badf ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
2021-06-17 09:39:46 +08:00
Bin Meng
77eae0ebe6 riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The
intention was to use gdb to load device tree before running U-Boot
SPL/proper from RAM. When we switch to OF_SEPARATE we will have to
use our own DT but without "u-boot,dm-spl" in several essential
nodes, SPL does not boot.

Let's add all the required "u-boot,dm-spl" for SPL config.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-06-17 09:39:08 +08:00
Bin Meng
048aff6d26 riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:39:08 +08:00
Bin Meng
f050dd2b26 riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
PLIC nodes don't have child nodes, so #address-cells is not needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:39:08 +08:00
Bin Meng
5c267e0033 riscv: ae350: dts: Remove the unnecessary space in bootargs
There are two spaces before "debug' in bootargs. Drop one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17 09:39:08 +08:00
Bin Meng
2ff6b799a8 riscv: ae350: dts: Add SPDX license header
The SPDX license header is currently missing. Add one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-06-17 09:39:08 +08:00
Tom Rini
b2c4b7f665 u-boot-imx-20210616
-------------------
 
 - imxrt : fixes, USB, imxrt1020-evk
 - imx8m:
 	fix for verdin-imx8mm
 	Add conga-QMX8 board
 - imx6 :
 	documentation for pico-imx6:
 	Add SeeedStudio NPI-IMX6ULL Support
 	ventana: DM PCI
 - imx7d:
 	added SMEGW01 board
 
 CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7765
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Merge tag 'u-boot-imx-20210616' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20210616
-------------------

- imxrt : fixes, USB, imxrt1020-evk
- imx8m:
	fix for verdin-imx8mm
	Add conga-QMX8 board
- imx6 :
	documentation for pico-imx6:
	Add SeeedStudio NPI-IMX6ULL Support
	ventana: DM PCI
- imx7d:
	added SMEGW01 board

CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7765
2021-06-16 11:18:11 -04:00
Michael Walle
2bf4658b8c board: sl28: fix RGMII clock and voltage
It was noticed that the clock isn't continuously enabled when there is
no link. This is because the 125MHz clock is derived from the internal
PLL which seems to go into some kind of power-down mode every once in a
while. The LS1028A expects a contiuous clock. Thus enable the PLL all
the time.

Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-06-16 18:14:08 +05:30
Vignesh Raghavendra
2af181b53e ARM: dts: k3: Add cfg register space for ringacc and udmap
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING
CFG, TCHAN CFG and RCHAN CFG address ranges.
Note that these registers are present within respective IPs but are
not populated in Linux DT nodes (as they are configured via TISCI APIs)
and hence are added to -u-boot.dtsi for now.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Vignesh Raghavendra
00d6fc9c71 ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node
Add DM firmware node which will provide DM services during R5 SPL stage.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210607141753.28796-5-vigneshr@ti.com
2021-06-11 19:18:52 +05:30
Tom Rini
c4737cd594 Xilinx changes for v2021.07-rc5
zynqmp:
 - Fix ANALOG_BUS value after powerup
 - Disable EFI_CAPSULE_ON_DISK_EARLY
 
 zynqmp-gqspi:
 - Fix write issue
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Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.07-rc5

zynqmp:
- Fix ANALOG_BUS value after powerup
- Disable EFI_CAPSULE_ON_DISK_EARLY

zynqmp-gqspi:
- Fix write issue
2021-06-11 08:29:34 -04:00
Tero Kristo
bb318d8dc8 arm: dts: k3-j72xx: correct MCU timer1 frequency
MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.

Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused an error to the clock by a factor of 8
with j7 devices. This problem surfaced once the omap-timer was fixed.

Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
61305e00c7 arm: mach-k3: j721e_init: Force early probe of clk-k3 driver
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reported-by: Keerthy <j-keerthy@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
925698daac arm: mach-k3: sysfw-loader: pass boardcfg to sciserver
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
7acd4d7142 arm: mach-k3: common: Drop main r5 start
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
0714580346 arm: mach-k3: do board config for PM only if supported
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
547b277cd9 arm: mach-k3: add support for detecting firmware images from FIT
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
277729eaf3 arm: mach-k3: Add platform data for j721e and j7200
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
df5363a67f tools: k3_fit_atf: add DM binary to the FIT image
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Lokesh Vutla
481d394e77 common: fit: Update board_fit_image_post_process() to pass fit and node_offset
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
99214c1f48 arm: mach-k3: introduce new config option for sysfw split
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, add
new config option which can be used to detect presence of RM/PM sysfw
services.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Adrian Fiergolski
3414712ba8 arm64: zynqmp: Writing correct value to ANALOG_BUS
The default register configuration after powerup for PSSYSMON_ANALOG_BUS
register is incorrect. Hence, fix this in SPL by writing correct fixed
value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c")
in Xilinx:embeddedsw[1].

[1] https://github.com/Xilinx/embeddedsw

Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-11 09:24:58 +02:00
Marek Behún
f221333400 arm: mvebu: dts: turris_mox: add nodes for SPI NOR partitions
Add nodes for SPI NOR partitions to the device tree of Turris MOX, as
are in Linux' device tree.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-10 07:18:06 +02:00
Marek Behún
e04bf43681 arm: mvebu: dts: turris_mox: add button and LED nodes
Add nodes for indicator LED and reset button so that board code can
implement board factory reset mechanism.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-06-10 07:18:06 +02:00
Dario Binacchi
62af440e21 arm: dts: sync rtc node of am335x boards with Linux 5.9-rc7
There have been some changes to the am335x-<board> DTs related to the
rtc node, so let's re-syncs them with Linux.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210602203805.11494-7-dariobin@libero.it
2021-06-09 22:23:44 +05:30
Aswath Govindraju
defd62ca13 arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its max size
Due to a limitation for USB DFU boot mode, SPL load address has to be less
than  or equal to 0x70001000. So, load address of SPL and ATF have been
moved to 0x70000000 and 0x701a0000 respectively.

Also, the maximum size of ATF has been increased to 0x1c000 [1].

Therefore, update ATF's location and maximum size accordingly in the device
tree file.

[1] - https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=2fb5312f61a7de8b7a70e1639199c4f14a10b6f9

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-10-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
26f32c32b2 configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode
For USB DFU boot mode there is a limitation on the load address of boot
images that they have to be less than 0x70001000. Therefore, move the
SPL_TEXT_BASE address to 0x70000000.

Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at
0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move
the location of ATF to a latter location in SRAM, past the SPL image. Also
rearrange the EEPROM and BSS data on top of ATF.

Given below is the placement of various data sections in SRAM

     ┌──────────────────────────────────────┐0x70000000
     │                                      │
     │                                      │
     │                                      │
     │    SPL IMAGE (Max size 1.5 MB)       │
     │                                      │
     │                                      │
     │                                      │
     ├──────────────────────────────────────┤0x7017FFFF
     │                                      │
     │           SPL STACK                  │
     │                                      │
     ├──────────────────────────────────────┤0x70192727
     │          GLOBAL DATA(216 B)          │
     ├──────────────────────────────────────┤0x701927FF
     │                                      │
     │       INITIAL HEAP (32 KB)           │
     │                                      │
     ├──────────────────────────────────────┤0x7019A7FF
     │                                      │
     │          BSS  (20 KB)                │
     ├──────────────────────────────────────┤0x7019F7FF
     │         EEPROM DATA (2 KB)           │
     ├──────────────────────────────────────┤0x7019FFFF
     │                                      │
     │                                      │
     │            ATF (123 KB)              │
     │                                      │
     │                                      │
     ├──────────────────────────────────────┤0x701BEBFB
     │   BOOT PARAMETER INDEX TABLE (5124 B)│
     ├──────────────────────────────────────┤0x701BFFFF
     │                                      │
     │SYSFW FIREWALLED DUE TO A BUG (128 KB)│
     │                                      │
     ├──────────────────────────────────────┤0x701DFFFF
     │                                      │
     │      DMSC CODE AREA (128 KB)         │
     │                                      │
     └──────────────────────────────────────┘0x701FFFFF

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-9-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
1c8b404b88 arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to peripheral for USB subsystem
Add U-Boot tags and fix the dr_mode as peripheral in U-Boot to support DFU
by default.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-8-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
7803a5bda9 arm: dts: k3-am642-*-evm: Add USB support
AM64 EVM board has a micro USB 2.0 AB connector and the USB0_VBUS is
connected with a resistor divider in between. USB0_DRVVBUS pin is muxed
between USB0_DRVVBUS and GPIO1_79 signals.

Add the corresponding properties and set the pinmux mode for USB subsystem
in the evm dts file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-7-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
cdb738411f arm: dts: k3-am64-main: Add USB DT nodes
Add DT node for the single USB subsystem in main dtsi file.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-6-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
669a03e0ff arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modes
U-Boot either supports USB host or device mode for a node at a time in the
device tree nodes. To support both host and dfu bootmodes, dr_mode is set
to "peripheral" by default and then fixed based on the mode selected by
the boot mode config dip switches on the board.

This needs to happen before the cdns3 generic layer binds the usb device
to a host or a device driver. Therefore, use fdtdec_setup_board()
implementation to fixup the device tree property.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-4-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
3ae127c4e2 arm: mach-k3: am642_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-3-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
0c51509224 tools: k3_fit_atf: Add support for providing ATF load address using a Kconfig symbol
Add support for providing ATF load address with a Kconfig symbol.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-2-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Kevin Scholz
dc9f1009b1 arm: dts: k3-j7200: ddr: Update to 0.5.0 version of DDR for LPDDR 2666MTs
Update the ddr settings to use the DDR reg config tool rev 0.5.0.
This enables 2666MTs LPDDR configuration on J7200.

Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210603131453.11414-1-praneeth@ti.com
2021-06-09 22:23:44 +05:30
Fabio Estevam
40496ac3b7 mx7d: Add Storopack's SMEGW01 board
Add support for Storopack's SMEGW01 board, which is an
IoT gateway based on the i.MX7D SoC.

Based on the original U-Boot work done by Phytec.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2021-06-09 13:34:38 +02:00
Navin Sankar Velliangiri
a3a0bc85c0 imx: Add SeeedStudio NPI-IMX6ULL Support
CPU:   Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 49C
Reset cause: POR
Model: Seeed NPi iMX6ULL Dev Board with NAND
Board: Seeed NPi i.MX6ULL Dev Board
DRAM:  512 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial@2020000
Out:   serial@2020000
Err:   serial@2020000
Net:   FEC0

Working:
- Eth0
- MMC/SD
- NAND
- UART 1
- USB host

Signed-off-by: Navin Sankar Velliangiri <navin@linumiz.com>

Note:

Changes in v2:

 * removed unnecessary space in imx6ull-seeed-npi-imx6ull-dev-board.dts file.
 * Used SZ_2M for CONFIG_SYS_MALLOC_LEN size allocation.
2021-06-09 13:34:18 +02:00
Oliver Graute
fe133eb192 imx: support for conga-QMX8 board
Add i.MX8QM qmx8 congatec board support

U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200)

CPU:   NXP i.MX8QM RevB A53 at 1200 MHz

Model: Congatec QMX8 Qseven series
Board: conga-QMX8
Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9
Boot:  SD2
DRAM:  6 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
switch to partitions #0, OK
mmc2 is current device
Net:
Error: ethernet@5b040000 address not set.
No ethernet found.

Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-06-09 13:34:09 +02:00
Andrey Zhizhikin
6ac4d44806 arm: imx: imx8mm: correct unrecognized fracpll frequency
Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
macro, which expands the value provided to the Hz range without taking into
account the precise Hz setting. This causes the frequency of 266 MHz not ot
be found in the imx8mm_fracpll_tbl, since it is entered there with a
precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
fracpll frequency cannot be determined.

Correct the value in imx8mm_fracpll_tbl to match the one expanded by
MHZ(266) macro, rounding it down to MHz range only.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-06-09 13:34:01 +02:00
Tim Harvey
cd18f1e6e6 imx: ventana: enable dm support for PCI and FEC ethernet
Enable driver model support for FEC ethernet which allows us to remove
the iomux and board_eth_init function. Replace the toggling of the ethernet
phy reset with dt configuration.

Enable driver model support for PCI which allows us to remove the
eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for
PCI devices on init such as the e1000 that is present on the GW552x.

Convert board_pci_fixup to use dm callback and remove pcidisable env
variable which is not supported for DM_PCI and thus leave PCI always
enabled during init.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-06-09 13:33:35 +02:00
Andrey Zhizhikin
d9a7f1a913 arm: imx: imx8mm: clock: make debug output more descriptive
Clock initialization functionality has ambitious debug messages, which are
printed out when failures are triggered during execution:
- Separate frequency table lookup functions have the the same output that
  makes it impossible to understand which function failed and produced the
  output
- PLL decoding routine has a generic debug statement printed, which does
  not state the actual value failed to be found

Extend the output for both cases with prefixing table lookup functions
output with function name, and report the failed value in PLL decoding
routine.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-06-09 13:33:26 +02:00
Oleh Kravchenko
1180baec98 Add EV-iMX280-NANO-X-MB board
A simple prototyping board with one microSD port, one Ethernet port,
2 USB ports, I2C, SPI, GPIO, and UART interfaces.

Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Stefano Babic <sbabic@denx.de>
2021-06-09 13:32:49 +02:00
Oleh Kravchenko
3675ac081a Add out4.ru O4-iMX-NANO board
Board designed for quick prototyping and has one microSD port,
2 Ethernet ports, 2 USB ports, I2C, SPI, CAN, RS-485, GPIO,
UART interfaces, and 2 RGB LEDs.

Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Cc: Stefano Babic <sbabic@denx.de>
2021-06-09 13:32:42 +02:00
Giulio Benetti
42b967216e ARM: dts: imxrt1050-evk: enable usbotg1 node as host
Enable usbotg1 port node as host usb.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:04:00 +02:00
Giulio Benetti
9b91484a89 ARM: dts: imxrt1050: add usbotg1, usbphy1 and usbmisc nodes
Usb is now supported so add all required nodes for it in imxrt1050.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:03:54 +02:00
Giulio Benetti
e7e81e8959 usb: ehci-mx6: add support for i.MXRT
Add support for usb1 and usb2 present on i.IMXRT.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:03:47 +02:00
Giulio Benetti
0d90dec182 ARM: IMXRT: introduce is_imxrt*() macros and get_cpu_rev()
We need those macros to instruct drivers on how to behave for SoC specific
quirks, so let's add it as done for other i.MX SoCs.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:03:33 +02:00
Giulio Benetti
d7308dbd86 ARM: dts: imxrt1020: add gpio5 node to this SoC
i.MXRT1020 supports gpio5, so let's add a node for it.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:03:26 +02:00
Giulio Benetti
dc54f82901 ARM: dts: imxrt1020-evk: move all u-boot, dm-spl to imxrt1020-evk-u-boot.dtsi file
At the moment a lot of u-boot,dm-spl properties are present in board .dts
file but this is not correct since u-boot,dm-spl property is u-boot
specific and must be listed into the separate imrt1020-evk-u-boot.dtsi
file. So let's move every u-boot,dm-spl property present in
imxrt1020-evk.dts to imxrt1020-evk-u-boot.dtsi file.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:03:19 +02:00
Giulio Benetti
1f3555d906 ARM: dts: imxrt1050-evk: move all u-boot, dm-spl to imxrt1050-evk-u-boot.dtsi file
At the moment a lot of u-boot,dm-spl properties are present in board .dts
file but this is not correct since u-boot,dm-spl property is u-boot
specific and must be listed into the separate imrt1050-evk-u-boot.dtsi
file. So let's move every u-boot,dm-spl property present in
imxrt1050-evk.dts to imxrt1050-evk-u-boot.dtsi file.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:03:08 +02:00
Giulio Benetti
31f0e58527 ARM: dts: imxrt1050-evk: remove u-boot,dm-spl
We don't need lcdif to be enable in SPL, so let's remove u-boot,dm-spl.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:01:33 +02:00
Giulio Benetti
a9a5c33d57 ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver
Lcdif needs both "pix" and "axi" clocks to be enabled so let's add them to
lcdif node.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:01:33 +02:00
Giulio Benetti
f2d91e606b ARM: dts: imxrt1050: move lcdif assigned clock to dtsi
Since we assume pll5 is the default lcdif clock source let's move
assigned-clocks(-parents) properties to .dtsi file.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:01:33 +02:00
Giulio Benetti
6f6f03af0e ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node
Now device_type = "memory" is mandatory to allow u-boot to read memory
node, so let's add it to memory node.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-06-09 13:01:33 +02:00