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board: sl28: fix RGMII clock and voltage

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It was noticed that the clock isn't continuously enabled when there is
no link. This is because the 125MHz clock is derived from the internal
PLL which seems to go into some kind of power-down mode every once in a
while. The LS1028A expects a contiuous clock. Thus enable the PLL all
the time.

Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Michael Walle 2021-04-13 17:54:17 +02:00 • committed by Priyanka Jain
parent fb4e64ef9d
commit 2bf4658b8c
2 changed files with 4 additions and 2 deletions
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3
arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
View file

@ -41,8 +41,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddh>;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";

3
arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
View file

@ -32,8 +32,9 @@
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddh>;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";