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riscv: add functions for reading the IPI status
Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
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4 changed files with 43 additions and 0 deletions
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@ -117,6 +117,17 @@ int riscv_clear_ipi(int hart)
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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PLIC_BASE_GET();
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*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
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gd->arch.boot_hart));
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*pending = !!(*pending & SEND_IPI_TO_HART(hart));
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return 0;
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}
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static const struct udevice_id andes_plic_ids[] = {
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{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
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{ }
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@ -23,3 +23,14 @@ int riscv_clear_ipi(int hart)
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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/*
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* The SBI does not support reading the IPI status. We always return 0
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* to indicate that no IPI is pending.
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*/
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*pending = 0;
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return 0;
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}
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@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart)
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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CLINT_BASE_GET();
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*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
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{ }
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@ -32,6 +32,18 @@ extern int riscv_send_ipi(int hart);
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*/
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extern int riscv_clear_ipi(int hart);
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/**
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* riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
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*
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* Platform code must provide this function.
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*
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* @hart: Hart ID of hart to be checked
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* @pending: Pointer to variable with result of the check,
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* 1 if IPI is pending, 0 otherwise
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* @return 0 if OK, -ve on error
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*/
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extern int riscv_get_ipi(int hart, int *pending);
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static int send_ipi_many(struct ipi_data *ipi)
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{
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ofnode node, cpus;
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