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ppc: Remove MPC8313ERDB boards

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These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-05-14 21:34:16 -04:00
parent af96210ae7
commit 7458f18e5c
13 changed files with 0 additions and 1898 deletions
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13
arch/powerpc/cpu/mpc83xx/Kconfig
View file

@ -16,18 +16,6 @@ config TARGET_CADDY2
bool "Support caddy2"
select ARCH_MPC8349
config TARGET_MPC8313ERDB_NOR
bool "Support MPC8313ERDB_NOR"
select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_MPC8313ERDB_NAND
bool "Support MPC8313ERDB_NAND"
select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
select ARCH_MPC8315
@ -291,7 +279,6 @@ config FSL_ELBC
bool
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"
source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"

25
board/freescale/mpc8313erdb/Kconfig
View file

@ -1,25 +0,0 @@
if TARGET_MPC8313ERDB_NOR
config SYS_BOARD
default "mpc8313erdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8313ERDB_NOR"
endif
if TARGET_MPC8313ERDB_NAND
config SYS_BOARD
default "mpc8313erdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8313ERDB_NAND"
endif

9
board/freescale/mpc8313erdb/MAINTAINERS
View file

@ -1,9 +0,0 @@
MPC8313ERDB BOARD
#M: -
S: Maintained
F: board/freescale/mpc8313erdb/
F: include/configs/MPC8313ERDB.h
F: configs/MPC8313ERDB_33_defconfig
F: configs/MPC8313ERDB_66_defconfig
F: configs/MPC8313ERDB_NAND_33_defconfig
F: configs/MPC8313ERDB_NAND_66_defconfig

6
board/freescale/mpc8313erdb/Makefile
View file

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := mpc8313erdb.o sdram.o

111
board/freescale/mpc8313erdb/README
View file

@ -1,111 +0,0 @@
Freescale MPC8313ERDB Board
-----------------------------------------
1. Board Switches and Jumpers
S3 is used to set CONFIG_SYS_RESET_SOURCE.
To boot the image at 0xFE000000 in NOR flash, use these DIP
switch settings for S3 S4:
+------+ +------+
| | | **** |
| **** | | |
+------+ ON +------+ ON
4321 4321
(where the '*' indicates the position of the tab of the switch.)
To boot the image at the beginning of NAND flash, use these
DIP switch settings for S3 S4:
+------+ +------+
| * | | *** |
| *** | | * |
+------+ ON +------+ ON
4321 4321
(where the '*' indicates the position of the tab of the switch.)
When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
2. Memory Map
The memory map looks like this:
0x0000_0000 0x07ff_ffff DDR 128M
0x8000_0000 0x8fff_ffff PCI MEM 256M
0x9000_0000 0x9fff_ffff PCI_MMIO 256M
0xe000_0000 0xe00f_ffff IMMR 1M
0xe200_0000 0xe20f_ffff PCI IO 16M
0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K
0xfa00_0000 0xfa00_7fff Board Status/ 32K
LED Control (CS3)
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
When booting from NAND, NAND flash is CS0 and NOR flash
is CS1.
3. Definitions
3.1 Explanation of NEW definitions in:
include/configs/MPC8313ERDB.h
CONFIG_MPC83xx MPC83xx family
CONFIG_MPC831x MPC831x specific
CONFIG_MPC8313ERDB MPC8313ERDB board specific
4. Compilation
Assuming you're using BASH (or similar) as your shell:
export CROSS_COMPILE=your-cross-compiler-prefix-
make distclean
make MPC8313ERDB_XXX_config
(where XXX is:
33 - 33 MHz oscillator, boot from NOR flash
66 - 66 MHz oscillator, boot from NOR flash
NAND_33 - 33 MHz oscillator, boot from NAND flash
NAND_66 - 66 MHz oscillator, boot from NAND flash)
make
5. Downloading and Flashing Images
5.1 Reflash U-Boot Image using U-Boot
NOR flash:
=>run tftpflash
You may want to try
=>tftpboot $loadaddr $uboot
first, to make sure that the TFTP load will succeed before it
goes ahead and wipes out your current firmware. And of course,
have an alternate means of programming the flash available
if the new U-Boot doesn't boot.
NAND flash:
=>tftpboot $loadaddr <filename>
=>nand erase 0 0x80000
=>nand write $loadaddr 0 0x80000
...where 0x80000 is the filesize rounded up to
the next 0x20000 increment.
5.2 Downloading and Booting Linux Kernel
Ensure that all networking-related environment variables are set
properly (including ipaddr, serverip, gatewayip (if needed),
netmask, ethaddr, eth1addr, rootpath (if using NFS root),
fdtfile, and bootfile).
Then, do one of the following, depending on whether you
want an NFS root or a ramdisk root:
=>run nfsboot
or
=>run ramboot
6 Notes
The console baudrate for MPC8313ERDB is 115200bps.

160
board/freescale/mpc8313erdb/mpc8313erdb.c
View file

@ -1,160 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
*
* Author: Scott Wood <scottwood@freescale.com>
*/
#include <common.h>
#include <clock_legacy.h>
#include <fdt_support.h>
#include <init.h>
#if defined(CONFIG_OF_LIBFDT)
#include <linux/libfdt.h>
#endif
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <ns16550.h>
#include <nand.h>
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
#include <asm/gpio.h>
#endif
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
#endif
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
mpc83xx_gpio_init_f();
#endif
return 0;
}
int board_early_init_r(void)
{
#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
mpc83xx_gpio_init_r();
#endif
return 0;
}
int checkboard(void)
{
puts("Board: Freescale MPC8313ERDB\n");
return 0;
}
#ifndef CONFIG_SPL_BUILD
static struct pci_region pci_regions[] = {
{
.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
.size = CONFIG_SYS_PCI1_MEM_SIZE,
.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
.size = CONFIG_SYS_PCI1_MMIO_SIZE,
.flags = PCI_REGION_MEM
},
{
.bus_start = CONFIG_SYS_PCI1_IO_BASE,
.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
.size = CONFIG_SYS_PCI1_IO_SIZE,
.flags = PCI_REGION_IO
}
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg);
}
/*
* Miscellaneous late-boot configurations
*
* If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
int rc = 0;
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
puts("Failure uploading VSC7385 microcode.\n");
rc = 1;
}
#endif
return rc;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
return 0;
}
#endif
#else /* CONFIG_SPL_BUILD */
void board_init_f(ulong bootflag)
{
board_early_init_f();
ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
dram_init();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif

129
board/freescale/mpc8313erdb/sdram.c
View file

@ -1,129 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
*
* Authors: Nick.Spence@freescale.com
* Wilson.Lo@freescale.com
* scottwood@freescale.com
*/
#include <common.h>
#include <init.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
static void resume_from_sleep(void)
{
u32 magic = *(u32 *)0;
typedef void (*func_t)(void);
func_t resume = *(func_t *)4;
if (magic == 0xf5153ae5)
resume();
gd->flags &= ~GD_FLG_SILENT;
puts("\nResume from sleep failed: bad magic word\n");
}
#endif
/* Fixed sdram init -- doesn't use serial presence detect.
*
* This is useful for faster booting in configs where the RAM is unlikely
* to be changed, or for things like NAND booting where space is tight.
*/
static long fixed_sdram(void)
{
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
#ifndef CONFIG_SYS_RAMBOOT
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
/*
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
__udelay(50000);
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[0].csbnds =
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
CSBNDS_EA);
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
else
#endif
im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
sync();
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
#endif
return msize;
}
int dram_init(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
/* LB refresh timer prescal, 266MHz/32 */
lbc->mrtpr = 0x20000000;
sync();
#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
resume_from_sleep();
#endif
/* return total bus SDRAM size(bytes) -- DDR */
gd->ram_size = msize;
return 0;
}

169
configs/MPC8313ERDB_33_defconfig
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@ -1,169 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8313ERDB_NOR=y
CONFIG_SYSTEM_PLL_FACTOR_5_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_RGMII=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2800000
CONFIG_LBLAW1_NAME="NAND"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_LBLAW2=y
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="VSC7385"
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xFA000000
CONFIG_LBLAW3_NAME="BCSR"
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_8_MBYTES=y
CONFIG_OR0_SCY_9=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_EHTR_1_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="NAND"
CONFIG_BR1_OR1_BASE=0xE2800000
CONFIG_BR1_ERRORCHECKING_BOTH=y
CONFIG_BR1_MACHINE_FCM=y
CONFIG_OR1_SCY_1=y
CONFIG_OR1_CSCT_8_CYCLE=y
CONFIG_OR1_CST_ONE_CLOCK=y
CONFIG_OR1_CHT_TWO_CLOCK=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="VSC7385"
CONFIG_BR2_OR2_BASE=0xF0000000
CONFIG_OR2_AM_128_KBYTES=y
CONFIG_OR2_SCY_15=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="BCSR"
CONFIG_BR3_OR3_BASE=0xFA000000
CONFIG_OR3_SCY_15=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_OR3_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_BOOTDELAY=6
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

168
configs/MPC8313ERDB_66_defconfig
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@ -1,168 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8313ERDB_NOR=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_RGMII=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2800000
CONFIG_LBLAW1_NAME="NAND"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_LBLAW2=y
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="VSC7385"
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xFA000000
CONFIG_LBLAW3_NAME="BCSR"
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_8_MBYTES=y
CONFIG_OR0_SCY_9=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_EHTR_1_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="NAND"
CONFIG_BR1_OR1_BASE=0xE2800000
CONFIG_BR1_ERRORCHECKING_BOTH=y
CONFIG_BR1_MACHINE_FCM=y
CONFIG_OR1_SCY_1=y
CONFIG_OR1_CSCT_8_CYCLE=y
CONFIG_OR1_CST_ONE_CLOCK=y
CONFIG_OR1_CHT_TWO_CLOCK=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="VSC7385"
CONFIG_BR2_OR2_BASE=0xF0000000
CONFIG_OR2_AM_128_KBYTES=y
CONFIG_OR2_SCY_15=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="BCSR"
CONFIG_BR3_OR3_BASE=0xFA000000
CONFIG_OR3_SCY_15=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_OR3_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_BOOTDELAY=6
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

178
configs/MPC8313ERDB_NAND_33_defconfig
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@ -1,178 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x80000
CONFIG_SPL_TEXT_BASE=0xFFF00000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8313ERDB_NAND=y
CONFIG_SYSTEM_PLL_FACTOR_5_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
CONFIG_TSEC1_MODE_RGMII=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_NAND_LBLAWBAR_PRELIM_1=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2800000
CONFIG_LBLAW1_NAME="NAND"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_LBLAW2=y
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="VSC7385"
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xFA000000
CONFIG_LBLAW3_NAME="BCSR"
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="NAND"
CONFIG_BR0_OR0_BASE=0xE2800000
CONFIG_BR0_ERRORCHECKING_BOTH=y
CONFIG_BR0_MACHINE_FCM=y
CONFIG_OR0_SCY_1=y
CONFIG_OR0_CSCT_8_CYCLE=y
CONFIG_OR0_CST_ONE_CLOCK=y
CONFIG_OR0_CHT_TWO_CLOCK=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="FLASH"
CONFIG_BR1_OR1_BASE=0xFE000000
CONFIG_BR1_PORTSIZE_16BIT=y
CONFIG_OR1_AM_8_MBYTES=y
CONFIG_OR1_SCY_9=y
CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_EHTR_1_CYCLE=y
CONFIG_OR1_EAD_EXTRA=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="VSC7385"
CONFIG_BR2_OR2_BASE=0xF0000000
CONFIG_OR2_AM_128_KBYTES=y
CONFIG_OR2_SCY_15=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="BCSR"
CONFIG_BR3_OR3_BASE=0xFA000000
CONFIG_OR3_SCY_15=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_OR3_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_BOOTDELAY=6
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FLASH is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

177
configs/MPC8313ERDB_NAND_66_defconfig
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@ -1,177 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00100000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x80000
CONFIG_SPL_TEXT_BASE=0xFFF00000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SYS_CLK_FREQ=66666667
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8313ERDB_NAND=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
CONFIG_TSEC1_MODE_RGMII=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="PCI1_MEM"
CONFIG_BAT1_BASE=0x80000000
CONFIG_BAT1_LENGTH_256_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
CONFIG_BAT2_BASE=0x90000000
CONFIG_BAT2_LENGTH_256_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_NAND_LBLAWBAR_PRELIM_1=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_16_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2800000
CONFIG_LBLAW1_NAME="NAND"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_LBLAW2=y
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="VSC7385"
CONFIG_LBLAW2_LENGTH_128_KBYTES=y
CONFIG_LBLAW3=y
CONFIG_LBLAW3_BASE=0xFA000000
CONFIG_LBLAW3_NAME="BCSR"
CONFIG_LBLAW3_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="NAND"
CONFIG_BR0_OR0_BASE=0xE2800000
CONFIG_BR0_ERRORCHECKING_BOTH=y
CONFIG_BR0_MACHINE_FCM=y
CONFIG_OR0_SCY_1=y
CONFIG_OR0_CSCT_8_CYCLE=y
CONFIG_OR0_CST_ONE_CLOCK=y
CONFIG_OR0_CHT_TWO_CLOCK=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="FLASH"
CONFIG_BR1_OR1_BASE=0xFE000000
CONFIG_BR1_PORTSIZE_16BIT=y
CONFIG_OR1_AM_8_MBYTES=y
CONFIG_OR1_SCY_9=y
CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_EHTR_1_CYCLE=y
CONFIG_OR1_EAD_EXTRA=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="VSC7385"
CONFIG_BR2_OR2_BASE=0xF0000000
CONFIG_OR2_AM_128_KBYTES=y
CONFIG_OR2_SCY_15=y
CONFIG_OR2_CSNT_EARLIER=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_ELBC_BR3_OR3=y
CONFIG_BR3_OR3_NAME="BCSR"
CONFIG_BR3_OR3_BASE=0xFA000000
CONFIG_OR3_SCY_15=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_OR3_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_BOOTDELAY=6
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_MISC_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FLASH is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

392
include/configs/MPC8313ERDB_NAND.h
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@ -1,392 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
*/
/*
* mpc8313epb board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/stringify.h>
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
#define CONFIG_SPL_PAD_TO 0x4000
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
#define CONFIG_PCI_INDIRECT_BRIDGE
/*
* On-board devices
*
* TSEC1 is VSC switch
* TSEC2 is SoC TSEC
*/
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
/* Early revs of this board will lock up hard when attempting
* to access the PMC registers, unless a JTAG debugger is
* connected, or some resistor modifications are made.
*/
#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
/*
* Device configurations
*/
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC1
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
/*
* DDR Setup
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/*
* Manually set up DDR parameters, as this board does not
* seem to have the SPD connected to I2C.
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
| (10 << TIMING_CFG1_REFREC_SHIFT) \
| (3 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3835a322 */
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (5 << TIMING_CFG2_CPO_SHIFT) \
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x129048c6 */ /* P9-45,may need tuning */
#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x05100500 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_DBW_32 \
| SDRAM_CFG_2T_EN)
/* 0x43088000 */
#else
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
/* set burst length to 8 for 32-bit data path */
#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
| (0x0632 << SDRAM_MODE_SD_SHIFT))
/* 0x44480632 */
#define CONFIG_SYS_DDR_MODE_2 0x8000C000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/*0x02000000*/
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
| DDRCDR_M_ODR)
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
!defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* drivers/mtd/nand/raw/nand.c */
#if defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE 0xE2800000
#endif
#define CONFIG_MTD_PARTITION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
/* Still needed for spl_minimal.c */
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
/* local bus write LED / read status buffer (BCSR) mapping */
#define CONFIG_SYS_BCSR_ADDR 0xFA000000
#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
/* map at 0xFA000000 on LCS3 */
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
/* VSC7385 Base address on LCS2 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
#endif
#define CONFIG_MPC83XX_GPIO 1
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/*
* TSEC
*/
#define CONFIG_GMII /* MII PHY management */
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define TSEC2_PHY_ADDR 4
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC2_PHYIDX 0
#endif
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC1"
/*
* Configure on-board RTC
*/
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Environment
*/
#define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
/* Enable Internal USB Phy and GPIO on LCD Connector */
#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
/*
* Environment Configuration
*/
#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME "mpc8313erdb"
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8313erdb.dtb"
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
"$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
"run setbootargs;" \
"run setipargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv rootdev /dev/ram;" \
"run setbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#endif /* __CONFIG_H */

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include/configs/MPC8313ERDB_NOR.h
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@ -1,361 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
*/
/*
* mpc8313epb board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
#include <linux/stringify.h>
#define CONFIG_PCI_INDIRECT_BRIDGE
/*
* On-board devices
*
* TSEC1 is VSC switch
* TSEC2 is SoC TSEC
*/
#define CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* Early revs of this board will lock up hard when attempting
* to access the PMC registers, unless a JTAG debugger is
* connected, or some resistor modifications are made.
*/
#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
/*
* Device configurations
*/
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC1
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
/*
* DDR Setup
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
/*
* Manually set up DDR parameters, as this board does not
* seem to have the SPD connected to I2C.
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| (5 << TIMING_CFG1_CASLAT_SHIFT) \
| (10 << TIMING_CFG1_REFREC_SHIFT) \
| (3 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3835a322 */
#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (5 << TIMING_CFG2_CPO_SHIFT) \
| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x129048c6 */ /* P9-45,may need tuning */
#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x05100500 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_DBW_32 \
| SDRAM_CFG_2T_EN)
/* 0x43088000 */
#else
#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_DBW_32)
/* 0x43080000 */
#endif
#define CONFIG_SYS_SDRAM_CFG2 0x00401000
/* set burst length to 8 for 32-bit data path */
#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
| (0x0632 << SDRAM_MODE_SD_SHIFT))
/* 0x44480632 */
#define CONFIG_SYS_DDR_MODE_2 0x8000C000
#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/*0x02000000*/
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
| DDRCDR_M_ODR)
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
!defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* drivers/mtd/nand/nand.c */
#define CONFIG_SYS_NAND_BASE 0xE2800000
#define CONFIG_MTD_PARTITION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
/* Still needed for spl_minimal.c */
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
/* local bus write LED / read status buffer (BCSR) mapping */
#define CONFIG_SYS_BCSR_ADDR 0xFA000000
#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
/* map at 0xFA000000 on LCS3 */
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
/* VSC7385 Base address on LCS2 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
#endif
#define CONFIG_MPC83XX_GPIO 1
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/*
* TSEC
*/
#define CONFIG_GMII /* MII PHY management */
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define TSEC2_PHY_ADDR 4
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC2_PHYIDX 0
#endif
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC1"
/*
* Configure on-board RTC
*/
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Environment
*/
#if !defined(CONFIG_SYS_RAMBOOT)
/* Address and size of Redundant Environment Sector */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */
#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
/* Enable Internal USB Phy and GPIO on LCD Connector */
#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
/*
* Environment Configuration
*/
#define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME "mpc8313erdb"
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8313erdb.dtb"
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize; " \
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
" +$filesize; " \
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
"$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
"run setbootargs;" \
"run setipargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv rootdev /dev/ram;" \
"run setbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#endif /* __CONFIG_H */