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board/km: add support for expu1 design based on nxp

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The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.

The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Aleksandar Gerasimovski 2021-06-08 14:16:28 +00:00 committed by Priyanka Jain
parent 0b036d4c1b
commit a7fd6fa1c2
9 changed files with 323 additions and 8 deletions
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18
arch/arm/Kconfig
View file

@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8
SELI8 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_PG_WCOM_EXPU1
bool "Support Hitachi-Powergrids EXPU1 service unit card"
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select VENDOR_KM
imply SCSI
help
Support for Hitachi-Powergrids EXPU1 service unit card.
EXPU1 is a QorIQ LS1021a based service unit card used
in XMC20 and FOX615 product families.
config TARGET_LS1021ATSN
bool "Support ls1021atsn"
select ARCH_LS1021A

1
arch/arm/dts/Makefile
View file

@ -411,6 +411,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \

130
arch/arm/dts/ls1021a-pg-wcom-expu1.dts Normal file
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@ -0,0 +1,130 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Hitachi ABB Power Grids EXPU1 board device tree source
*
* Copyright 2020 Hitachi ABB Power Grids
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include "ls1021a.dtsi"
/ {
model = "EXPU1 Service Unit for XMC and FOX";
aliases {
enet2-rgmii-debug-phy = &debug_phy;
};
chosen {
stdout-path = &uart0;
};
};
&enet0 {
status = "okay";
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet1 {
status = "okay";
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&enet2 {
phy-handle = <&debug_phy>;
phy-connection-type = "rgmii-id";
max-speed = <100>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&dspi1 {
bus-num = <0>;
status = "okay";
zl30343@0 {
compatible = "gen,spidev", "zarlink,zl30343";
reg = <0>;
spi-max-frequency = <8000000>;
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board */
ranges = <0x0 0x0 0x60000000 0x04000000>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x4000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "rcw";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "qe";
reg = <0x20000 0x20000>;
};
/* ZL30343 init data to be added here */
partition@40000 {
label = "envred";
reg = <0x40000 0x20000>;
};
partition@60000 {
label = "env";
reg = <0x60000 0x20000>;
};
partition@100000 {
label = "u-boot";
reg = <0x100000 0x100000>;
};
partition@200000 {
label = "ubi0";
reg = <0x200000 0x3E00000>;
};
};
};
&mdio0 {
debug_phy: ethernet-phy@11 {
reg = <0x11>;
};
tbi0: tbi-phy@0xb {
reg = <0xb>;
device_type = "tbi-phy";
};
};
&mdio1 {
tbi1: tbi-phy@0xd {
reg = <0xd>;
device_type = "tbi-phy";
};
};
&uart0 {
status = "okay";
};

7
board/keymile/Kconfig
View file

@ -64,6 +64,13 @@ config SYS_PAX_BASE
help
IFC Base Address for PAXx FPGA.
config SYS_CLIPS_BASE
hex "CLIPS IFC Base Address"
default 0x78000000
depends on ARCH_LS1021A
help
IFC Base Address for CLIPS FPGA.
config KM_CONSOLE_TTY
string "KM Console"
default "ttyS0"

20
board/keymile/pg-wcom-ls102xa/Kconfig
View file

@ -17,3 +17,23 @@ config BOARD_SPECIFIC_OPTIONS
imply FS_CRAMFS
endif
if TARGET_PG_WCOM_EXPU1
config SYS_BOARD
default "pg-wcom-ls102xa"
config SYS_VENDOR
default "keymile"
config SYS_SOC
default "ls102xa"
config SYS_CONFIG_NAME
default "pg-wcom-expu1"
config BOARD_SPECIFIC_OPTIONS
def_bool y
imply FS_CRAMFS
endif

3
board/keymile/pg-wcom-ls102xa/MAINTAINERS
View file

@ -6,5 +6,8 @@ S: Maintained
F: board/keymile/pg-wcom-ls102xa/
F: include/configs/km/pg-wcom-ls102xa.h
F: include/configs/pg-wcom-seli8.h
F: include/configs/pg-wcom-expu1.h
F: configs/pg_wcom_seli8_defconfig
F: configs/pg_wcom_expu1_defconfig
F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts
F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts

29
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View file

@ -70,16 +70,29 @@ int board_early_init_f(void)
/* QRIO Configuration */
qrio_uprstreq(UPREQ_CORE_RST);
if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8)
qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_LIU_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(KM_PAXK_RST, true);
#endif
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
}
#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1)
qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(WCOM_TMG_RST, true);
qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_PHY_RST, false, false);
qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_wdmask(WCOM_QSFP_RST, true);
qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST);
qrio_prst(WCOM_CLIPS_RST, false, false);
#endif
qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(KM_DBG_ETH_RST, false, false);
i2c_deblock_gpio_cfg();

70
configs/pg_wcom_expu1_defconfig Normal file
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@ -0,0 +1,70 @@
CONFIG_ARM=y
CONFIG_TARGET_PG_WCOM_EXPU1=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_COMMON_ETH_INIT=y
CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-expu1"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
CONFIG_MISC_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_FSL_DDR3=y
# CONFIG_MMC is not set
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y

53
include/configs/pg-wcom-expu1.h Normal file
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@ -0,0 +1,53 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Hitachi ABB Power Grids
*/
#ifndef __CONFIG_PG_WCOM_EXPU1_H
#define __CONFIG_PG_WCOM_EXPU1_H
#define WCOM_EXPU1
#define CONFIG_HOSTNAME "EXPU1"
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
/* CLIPS FPGA Definitions */
#define CONFIG_SYS_CSPR3_EXT (0x00)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_40)
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
FTIM0_GPCM_TEADC(0x7) | \
FTIM0_GPCM_TEAHC(0x2))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x12))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x12))
#define CONFIG_SYS_CS3_FTIM3 0x04000000
/* PRST */
#define WCOM_CLIPS_RST 0
#define WCOM_QSFP_RST 1
#define WCOM_PHY_RST 2
#define WCOM_TMG_RST 3
#define KM_DBG_ETH_RST 15
/* QRIO GPIOs used for deblocking */
#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
#define KM_I2C_DEBLOCK_SCL 20
#define KM_I2C_DEBLOCK_SDA 21
/* ZL30343 on SPI */
#define WCOM_ZL30343_CFG_ADDR 0xe8070000
#define WCOM_ZL30343_SPI_BUS 0
#define WCOM_ZL30343_CS 0
#include "km/pg-wcom-ls102xa.h"
#endif /* __CONFIG_PG_WCOM_EXPU1_H */