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m68k: Remove M5485 boards

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These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them.  As this is all of the CONFIG_M548x platforms as well,
remove that code.

Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-05-14 21:34:09 -04:00
parent a3c6f97cb1
commit eb83d10b42
25 changed files with 1 additions and 891 deletions
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9
arch/m68k/Kconfig
View file

@ -141,10 +141,6 @@ config M547x
bool
select MCF547x_8x
config M548x
bool
select MCF547x_8x
choice
prompt "Target select"
optional
@ -221,10 +217,6 @@ config TARGET_M5475EVB
bool "Support M5475EVB"
select M547x
config TARGET_M5485EVB
bool "Support M5485EVB"
select M548x
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
@ -253,7 +245,6 @@ source "board/freescale/m54418twr/Kconfig"
source "board/freescale/m54451evb/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
source "board/freescale/m548xevb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"

25
arch/m68k/dts/M5485AFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485AFE";
compatible = "fsl,M5485AFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485BFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485BFE";
compatible = "fsl,M5485BFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485CFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485CFE";
compatible = "fsl,M5485CFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485DFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485DFE";
compatible = "fsl,M5485DFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485EFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485EFE";
compatible = "fsl,M5485EFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485FFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485FFE";
compatible = "fsl,M5485FFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485GFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485GFE";
compatible = "fsl,M5485GFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

25
arch/m68k/dts/M5485HFE.dts
View file

@ -1,25 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf54xx.dtsi"
/ {
model = "Freescale M5485HFE";
compatible = "fsl,M5485HFE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec0 {
status = "okay";
};
&fec1 {
status = "okay";
mii-base = <0>;
};

8
arch/m68k/dts/Makefile
View file

@ -39,14 +39,6 @@ dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
M5475EFE.dtb \
M5475FFE.dtb \
M5475GFE.dtb
dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
M5485BFE.dtb \
M5485CFE.dtb \
M5485DFE.dtb \
M5485EFE.dtb \
M5485FFE.dtb \
M5485GFE.dtb \
M5485HFE.dtb
targets += $(dtb-y)

2
arch/m68k/include/asm/coldfire/intctrl.h
View file

@ -11,7 +11,7 @@
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
defined(CONFIG_M547x) || defined(CONFIG_M548x)
defined(CONFIG_M547x)
# define CONFIG_SYS_CF_INTC_REG1
#endif

47
arch/m68k/include/asm/immap.h
View file

@ -412,51 +412,4 @@
#endif
#endif /* CONFIG_M547x */
#ifdef CONFIG_M548x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6
#define FEC0_TX_PRIORITY 7
#define FEC0_RX_INIT 16
#define FEC0_TX_INIT 17
#define FEC1_RX_TASK 2
#define FEC1_TX_TASK 3
#define FEC1_RX_PRIORITY 6
#define FEC1_TX_PRIORITY 7
#define FEC1_RX_INIT 30
#define FEC1_TX_INIT 31
#endif
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
/* Timer */
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (0x1E)
#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
#endif
#endif /* CONFIG_M548x */
#endif /* __IMMAP_H */

15
board/freescale/m548xevb/Kconfig
View file

@ -1,15 +0,0 @@
if TARGET_M5485EVB
config SYS_CPU
default "mcf547x_8x"
config SYS_BOARD
default "m548xevb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "M5485EVB"
endif

13
board/freescale/m548xevb/MAINTAINERS
View file

@ -1,13 +0,0 @@
M548XEVB BOARD
M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
S: Maintained
F: board/freescale/m548xevb/
F: include/configs/M5485EVB.h
F: configs/M5485AFE_defconfig
F: configs/M5485BFE_defconfig
F: configs/M5485CFE_defconfig
F: configs/M5485DFE_defconfig
F: configs/M5485EFE_defconfig
F: configs/M5485FFE_defconfig
F: configs/M5485GFE_defconfig
F: configs/M5485HFE_defconfig

6
board/freescale/m548xevb/Makefile
View file

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = m548xevb.o

108
board/freescale/m548xevb/m548xevb.c
View file

@ -1,108 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
#include <config.h>
#include <common.h>
#include <init.h>
#include <pci.h>
#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: ");
puts("Freescale FireEngine 5485 EVB\n");
return 0;
};
int dram_init(void)
{
siu_t *siu = (siu_t *) (MMAP_SIU);
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
}
i--;
out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (temp == (1 << i))
break;
}
i--;
dramsize += temp;
out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
gd->ram_size = dramsize;
return 0;
};
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf("DRAM test not implemented!\n");
return (0);
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI devices, report devices found.
*/
static struct pci_controller hose;
extern void pci_mcf547x_8x_init(struct pci_controller *hose);
void pci_init_board(void)
{
pci_mcf547x_8x_init(&hose);
}
#endif /* CONFIG_PCI */

32
configs/M5485AFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485AFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485BFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485BFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485CFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485CFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485DFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485DFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485EFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485EFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485FFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485FFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485GFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485GFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

32
configs/M5485HFE_defconfig
View file

@ -1,32 +0,0 @@
CONFIG_M68K=y
CONFIG_SYS_TEXT_BASE=0xFF800000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="M5485HFE"
CONFIG_TARGET_M5485EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
CONFIG_BOOTDELAY=1
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFF840000
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_FSLDMAFEC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PHY=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

228
include/configs/M5485EVB.h
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@ -1,228 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Freescale MCF5485 FireEngine board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5485EVB_H
#define _M5485EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CONFIG_SLTTMR
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
# define CONFIG_SYS_DMA_USE_INTSRAM 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 32
# define CONFIG_SYS_TX_ETH_BUFFER 48
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif
#ifdef CONFIG_CMD_USB
# define CONFIG_USB_OHCI_NEW
/*# define CONFIG_PCI_OHCI*/
# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 80000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI_IO_BUS 0x71000000
#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
#endif
#define CONFIG_UDP_CHECKSUM
#define CONFIG_HOSTNAME "M548xEVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off bank 1;" \
"era ff800000 ff83ffff;" \
"cp.b ${loadaddr} ff800000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ 0x8000
/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_CFG1 0x73711630
#define CONFIG_SYS_SDRAM_CFG2 0x46770000
#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
#endif
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
#ifdef CONFIG_SYS_NOR1SZ
# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
#endif
#endif
/* Configuration for environment
* Environment is not embedded in u-boot. First time runing may have env
* crc error warning if there is no correct environment on the flash.
*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - NOR Flash
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL 0x00101980
#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL 0x00101D80
#endif
#endif /* _M5485EVB_H */