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imx: ventana: enable dm support for PCI and FEC ethernet

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Enable driver model support for FEC ethernet which allows us to remove
the iomux and board_eth_init function. Replace the toggling of the ethernet
phy reset with dt configuration.

Enable driver model support for PCI which allows us to remove the
eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for
PCI devices on init such as the e1000 that is present on the GW552x.

Convert board_pci_fixup to use dm callback and remove pcidisable env
variable which is not supported for DM_PCI and thus leave PCI always
enabled during init.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Tim Harvey 2021-05-03 11:21:27 -07:00 • committed by Stefano Babic
parent d9a7f1a913
commit cd18f1e6e6
17 changed files with 61 additions and 94 deletions
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2
arch/arm/dts/imx6qdl-gw51xx.dtsi
View file

@ -129,6 +129,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

2
arch/arm/dts/imx6qdl-gw52xx.dtsi
View file

@ -195,6 +195,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw53xx.dtsi
View file

@ -188,6 +188,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};
@ -597,6 +599,7 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};

3
arch/arm/dts/imx6qdl-gw54xx.dtsi
View file

@ -225,6 +225,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};
@ -675,6 +677,7 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};

2
arch/arm/dts/imx6qdl-gw560x.dtsi
View file

@ -279,6 +279,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw5903.dtsi
View file

@ -223,6 +223,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw5904.dtsi
View file

@ -200,6 +200,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
fixed-link {

2
arch/arm/dts/imx6qdl-gw5907.dtsi
View file

@ -131,6 +131,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

3
arch/arm/dts/imx6qdl-gw5910.dtsi
View file

@ -146,6 +146,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

4
arch/arm/dts/imx6qdl-gw5912.dtsi
View file

@ -141,6 +141,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};
@ -426,6 +429,7 @@
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
>;
};

3
arch/arm/dts/imx6qdl-gw5913.dtsi
View file

@ -121,6 +121,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
status = "okay";
};

1
board/gateworks/gw_ventana/common.h
View file

@ -11,7 +11,6 @@
#include "ventana_eeprom.h"
/* GPIO's common to all baseboards */
#define GP_PHY_RST IMX_GPIO_NR(1, 30)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)

99
board/gateworks/gw_ventana/gw_ventana.c
View file

@ -31,7 +31,6 @@
#include <linux/ctype.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
#include <pci.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
@ -54,42 +53,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct ventana_board_info ventana_info;
static int board_type;
/* ENET */
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
static void setup_iomux_enet(int gpio)
{
SETUP_IOMUX_PADS(enet_pads);
/* toggle PHY_RST# */
gpio_request(gpio, "phy_rst#");
gpio_direction_output(gpio, 0);
mdelay(10);
gpio_set_value(gpio, 1);
mdelay(100);
}
#ifdef CONFIG_USB_EHCI_MX6
/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
int board_ehci_hcd_init(int port)
@ -195,40 +158,7 @@ int mv88e61xx_hw_reset(struct phy_device *phydev)
}
#endif // CONFIG_MV88E61XX_SWITCH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_FEC_MXC
struct ventana_board_info *info = &ventana_info;
if (test_bit(EECONFIG_ETH0, info->config)) {
setup_iomux_enet(GP_PHY_RST);
cpu_eth_init(bis);
}
#endif
#ifdef CONFIG_E1000
e1000_initialize(bis);
#endif
#ifdef CONFIG_CI_UDC
/* For otg ethernet*/
usb_eth_initialize(bis);
#endif
/* default to the first detected enet dev */
if (!env_get("ethprime")) {
struct eth_device *dev = eth_get_dev_by_index(0);
if (dev) {
env_set("ethprime", dev->name);
printf("set ethprime to %s\n", env_get("ethprime"));
}
}
return 0;
}
#if defined(CONFIG_VIDEO_IPUV3)
static void enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
@ -427,7 +357,6 @@ int power_init_board(void)
return 0;
}
#if defined(CONFIG_CMD_PCI)
int imx6_pcie_toggle_reset(void)
{
if (board_type < GW_UNKNOWN) {
@ -448,6 +377,7 @@ int imx6_pcie_toggle_reset(void)
#define MAX_PCI_DEVS 32
struct pci_dev {
pci_dev_t devfn;
struct udevice *dev;
unsigned short vendor;
unsigned short device;
unsigned short class;
@ -458,18 +388,21 @@ struct pci_dev pci_devs[MAX_PCI_DEVS];
int pci_devno;
int pci_bridgeno;
void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
unsigned short vendor, unsigned short device,
unsigned short class)
void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
{
int i;
u32 dw;
struct pci_child_plat *pdata = dev_get_parent_plat(udev);
struct pci_dev *pdev = &pci_devs[pci_devno++];
unsigned short vendor = pdata->vendor;
unsigned short device = pdata->device;
unsigned int class = pdata->class;
pci_dev_t dev = dm_pci_get_bdf(udev);
int i;
debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
/* store array of devs for later use in device-tree fixup */
pdev->dev = udev;
pdev->devfn = dev;
pdev->vendor = vendor;
pdev->device = device;
@ -496,19 +429,19 @@ void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
if (vendor == PCI_VENDOR_ID_PLX &&
(device & 0xfff0) == 0x8600 &&
PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
ulong val;
debug("configuring PLX 860X downstream PERST#\n");
pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
dw |= 0xaaa8; /* GPIO1-7 outputs */
pci_hose_write_config_dword(hose, dev, 0x62c, dw);
pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
val |= 0xaaa8; /* GPIO1-7 outputs */
pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
pci_hose_read_config_dword(hose, dev, 0x644, &dw);
dw |= 0xfe; /* GPIO1-7 output high */
pci_hose_write_config_dword(hose, dev, 0x644, dw);
pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
val |= 0xfe; /* GPIO1-7 output high */
pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
mdelay(100);
}
}
#endif /* CONFIG_CMD_PCI */
#ifdef CONFIG_SERIAL_TAG
/*

5
configs/gwventana_emmc_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FIT_IMAGE_TINY=y
@ -85,9 +86,13 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y

5
configs/gwventana_gw5904_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FIT_IMAGE_TINY=y
@ -89,9 +90,13 @@ CONFIG_MV88E61XX_SWITCH=y
CONFIG_MV88E61XX_CPU_PORT=5
CONFIG_MV88E61XX_PHY_PORTS=0xf
CONFIG_MV88E61XX_FIXED_PORTS=0x0
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y

5
configs/gwventana_nand_defconfig
View file

@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FIT_IMAGE_TINY=y
@ -91,9 +92,13 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y

10
include/configs/gw_ventana.h
View file

@ -65,8 +65,6 @@
* PCI express
*/
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCI_FIXUP_DEV
#define CONFIG_PCIE_IMX
#endif
@ -82,13 +80,6 @@
/* Various command support */
/* Ethernet support */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_ARP_TIMEOUT 200UL
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
@ -129,7 +120,6 @@
#define CONFIG_SERVERIP 192.168.1.146
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"pcidisable=1\0" \
"splashpos=m,m\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \