mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
parent
cd64b0a6d9
commit
be1d758969
2 changed files with 82 additions and 1 deletions
|
@ -3,6 +3,7 @@
|
|||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright (C) 2015, Freescale Semiconductor
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
@ -98,3 +99,83 @@
|
|||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "fsl-ls1043-post.dtsi"
|
||||
|
||||
&fman0 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&qsgmii_phy1>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&qsgmii_phy2>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii-txid";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii-txid";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&qsgmii_phy3>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&qsgmii_phy4>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@f0000 { /* 10GEC1 */
|
||||
phy-handle = <&aqr105_phy>;
|
||||
phy-connection-type = "xgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
qsgmii_phy1: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
qsgmii_phy2: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
qsgmii_phy3: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
qsgmii_phy4: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
aqr105_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
interrupts = <0 132 4>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
interrupts = <1 9 0xf08>;
|
||||
};
|
||||
|
||||
soc {
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
Loading…
Add table
Reference in a new issue