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arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node

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This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for
zc1751-xm017-dc3 board.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Piyush Mehta 2021-06-21 10:11:27 +05:30 • committed by Michal Simek
parent 53b2af18ca
commit 436978b1d8
1 changed files with 26 additions and 0 deletions
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26
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
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@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
@ -37,6 +38,18 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_si5338_3: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
&fpd_dma_chan1 {
@ -166,6 +179,13 @@
};
};
&psgtr {
status = "okay";
/* usb3, sata */
clocks = <&clock_si5338_2>, <&clock_si5338_3>;
clock-names = "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -181,6 +201,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
};
&sdhci1 { /* emmc with some settings */
@ -205,6 +227,8 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
@ -217,5 +241,7 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
maximum-speed = "super-speed";
};