mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
arm: dts: rockchip: Add dts for rk3568 evb
Add dts for rk3568 evb, sync from the linux kernel upstream list [0]. [0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969 Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Joseph Chen
Kever Yang
parent
a4a9ce1660
commit
636ffbd25c
6 changed files with 4032 additions and 0 deletions
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@ -146,6 +146,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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rk3399-rockpro64.dtb \
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rk3399pro-rock-pi-n10.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3568-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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rv1108-elgin-r1.dtb \
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rv1108-evb.dtb
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23
arch/arm/dts/rk3568-evb-u-boot.dtsi
Normal file
23
arch/arm/dts/rk3568-evb-u-boot.dtsi
Normal file
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#include "rk3568-u-boot.dtsi"
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/ {
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chosen {
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stdout-path = &uart2;
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u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
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};
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};
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&sdmmc0 {
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status = "okay";
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};
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&uart2 {
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clock-frequency = <24000000>;
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u-boot,dm-spl;
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status = "okay";
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};
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79
arch/arm/dts/rk3568-evb.dts
Normal file
79
arch/arm/dts/rk3568-evb.dts
Normal file
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3568.dtsi"
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/ {
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model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
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compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
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chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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dc_12v: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc3v3_sys: vcc3v3-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc3v3_lcd0_n: vcc3v3-lcd0-n {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd0_n";
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc3v3_lcd1_n: vcc3v3-lcd1-n {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd1_n";
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&sdhci {
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bus-width = <8>;
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max-frequency = <200000000>;
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non-removable;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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3111
arch/arm/dts/rk3568-pinctrl.dtsi
Normal file
3111
arch/arm/dts/rk3568-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load diff
37
arch/arm/dts/rk3568-u-boot.dtsi
Normal file
37
arch/arm/dts/rk3568-u-boot.dtsi
Normal file
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@ -0,0 +1,37 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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/ {
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aliases {
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mmc0 = &sdhci;
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mmc1 = &sdmmc0;
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};
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dmc: dmc {
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compatible = "rockchip,rk3568-dmc";
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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};
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&cru {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pmucru {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&grf {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pmugrf {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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779
arch/arm/dts/rk3568.dtsi
Normal file
779
arch/arm/dts/rk3568.dtsi
Normal file
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@ -0,0 +1,779 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rk3568-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3568";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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serial8 = &uart8;
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serial9 = &uart9;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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clocks = <&scmi_clk 0>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000 900000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000 900000 1150000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <900000 900000 1150000>;
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opp-suspend;
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <900000 900000 1150000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <900000 900000 1150000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <975000 975000 1150000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1050000 1050000 1150000>;
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};
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opp-1992000000 {
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opp-hz = /bits/ 64 <1992000000>;
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opp-microvolt = <1150000 1150000 1150000>;
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};
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x82000010>;
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shmem = <&scmi_shmem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
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arm,no-tick-in-suspend;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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xin32k: xin32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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pinctrl-0 = <&clk32k_out0>;
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pinctrl-names = "default";
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#clock-cells = <0>;
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};
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sram@10f000 {
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compatible = "mmio-sram";
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reg = <0x0 0x0010f000 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x0010f000 0x100>;
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scmi_shmem: sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x100>;
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};
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};
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gic: interrupt-controller@fd400000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
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<0x0 0xfd460000 0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mbi-alias = <0x0 0xfd100000>;
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mbi-ranges = <296 24>;
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msi-controller;
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};
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pmugrf: syscon@fdc20000 {
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compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfdc20000 0x0 0x10000>;
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};
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grf: syscon@fdc60000 {
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compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
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reg = <0x0 0xfdc60000 0x0 0x10000>;
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};
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pmucru: clock-controller@fdd00000 {
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compatible = "rockchip,rk3568-pmucru";
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reg = <0x0 0xfdd00000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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cru: clock-controller@fdd20000 {
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compatible = "rockchip,rk3568-cru";
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reg = <0x0 0xfdd20000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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i2c0: i2c@fdd40000 {
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compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xfdd40000 0x0 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
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clock-names = "i2c", "pclk";
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pinctrl-0 = <&i2c0_xfer>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart0: serial@fdd50000 {
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compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
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reg = <0x0 0xfdd50000 0x0 0x100>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac0 0>, <&dmac0 1>;
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pinctrl-0 = <&uart0_xfer>;
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pinctrl-names = "default";
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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pwm0: pwm@fdd70000 {
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compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xfdd70000 0x0 0x10>;
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clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-0 = <&pwm0m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm1: pwm@fdd70010 {
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compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xfdd70010 0x0 0x10>;
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clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-0 = <&pwm1m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm2: pwm@fdd70020 {
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compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xfdd70020 0x0 0x10>;
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clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
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pinctrl-0 = <&pwm2m0_pins>;
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pinctrl-names = "active";
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm3: pwm@fdd70030 {
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compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
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reg = <0x0 0xfdd70030 0x0 0x10>;
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clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: mmc@fe000000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe000000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
||||
<&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
resets = <&cru SRST_SDMMC2>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc0: mmc@fe2b0000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
||||
<&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
resets = <&cru SRST_SDMMC0>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: mmc@fe2c0000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
||||
<&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
resets = <&cru SRST_SDMMC1>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: mmc@fe310000 {
|
||||
compatible = "rockchip,rk3568-dwcmshc";
|
||||
reg = <0x0 0xfe310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
|
||||
assigned-clock-rates = <200000000>, <24000000>;
|
||||
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
||||
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
||||
<&cru TCLK_EMMC>;
|
||||
clock-names = "core", "bus", "axi", "block", "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac0: dmac@fe530000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfe530000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_BUS>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac1: dmac@fe550000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfe550000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_BUS>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
i2c1: i2c@fe5a0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@fe5b0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c2m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@fe5c0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c3m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@fe5d0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c4m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@fe5e0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c5m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: watchdog@fe600000 {
|
||||
compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
|
||||
reg = <0x0 0xfe600000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
||||
clock-names = "tclk", "pclk";
|
||||
};
|
||||
|
||||
uart1: serial@fe650000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe650000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 2>, <&dmac0 3>;
|
||||
pinctrl-0 = <&uart1m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@fe660000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe660000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 4>, <&dmac0 5>;
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@fe670000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe670000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 6>, <&dmac0 7>;
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@fe680000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe680000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 8>, <&dmac0 9>;
|
||||
pinctrl-0 = <&uart4m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@fe690000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe690000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 10>, <&dmac0 11>;
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@fe6a0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6a0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 12>, <&dmac0 13>;
|
||||
pinctrl-0 = <&uart6m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@fe6b0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6b0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 14>, <&dmac0 15>;
|
||||
pinctrl-0 = <&uart7m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@fe6c0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6c0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 16>, <&dmac0 17>;
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart9: serial@fe6d0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6d0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 18>, <&dmac0 19>;
|
||||
pinctrl-0 = <&uart9m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@fe6e0000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0000 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm4_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm5: pwm@fe6e0010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0010 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm5_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm6: pwm@fe6e0020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0020 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm6_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm7: pwm@fe6e0030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0030 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm7_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm8: pwm@fe6f0000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0000 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm8m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm9: pwm@fe6f0010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0010 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm9m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm10: pwm@fe6f0020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0020 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm10m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm11: pwm@fe6f0030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0030 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm11m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm12: pwm@fe700000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700000 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm12m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm13: pwm@fe700010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700010 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm13m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm14: pwm@fe700020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700020 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm14m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm15: pwm@fe700030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700030 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm15m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,pmu = <&pmugrf>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@fdd60000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfdd60000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@fe740000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe740000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@fe750000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe750000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@fe760000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe760000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@fe770000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe770000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "rk3568-pinctrl.dtsi"
|
||||
Loading…
Reference in a new issue