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Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

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This commit is contained in:
Tom Rini 2021-07-06 12:22:39 -04:00
commit b5f9d2f3aa
31 changed files with 3167 additions and 6 deletions
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4
arch/riscv/Kconfig
View file

@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
endchoice
config SYS_ICACHE_OFF
@ -60,6 +63,7 @@ source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below

3
arch/riscv/cpu/fu740/Kconfig
View file

@ -35,3 +35,6 @@ config SIFIVE_FU740
imply SIFIVE_OTP
imply DM_PWM
imply PWM_SIFIVE
imply DM_I2C
imply SYS_I2C_OCORES
imply SPL_I2C_SUPPORT

3
arch/riscv/dts/Makefile
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@ -3,8 +3,9 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb hifive-unmatched-a00-rev1.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
targets += $(dtb-y)

4
arch/riscv/dts/fu740-c000-u-boot.dtsi
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@ -95,6 +95,10 @@
u-boot,dm-spl;
};
&i2c0 {
u-boot,dm-spl;
};
&eth0 {
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125125000>;

1489
arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi Normal file
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File diff suppressed because it is too large Load diff

7
arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 SiFive, Inc
*/
#include "hifive-unmatched-a00-u-boot.dtsi"
#include "fu740-hifive-unmatched-a00-ddr-rev1.dtsi"

4
arch/riscv/dts/hifive-unmatched-a00-rev1.dts Normal file
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@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright (c) 2021 SiFive, Inc */
#include "hifive-unmatched-a00.dts"

153
arch/riscv/dts/openpiton-riscv64.dts Normal file
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@ -0,0 +1,153 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
/*
* This dts is for a dual core instance of OpenPiton+Ariane built
* to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
* are automatically generated by the OpenPiton build system and
* this configuration may not be what you need if your configuration
* is different from the below.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "openpiton,riscv64";
chosen {
stdout-path = "uart0:115200";
};
aliases {
console = &uart0;
serial0 = &uart0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <520835>;
CPU0: cpu@0 {
clocks = <&clk0>;
u-boot,dm-spl;
device_type = "cpu";
reg = <0>;
compatible = "openhwgroup,cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU1: cpu@1 {
clocks = <&clk0>;
device_type = "cpu";
reg = <1>;
compatible = "openhwgroup,cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
clocks {
clk0: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <66667000>;
};
};
memory@80000000 {
u-boot,dm-spl;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "openpiton,chipset", "simple-bus";
ranges;
uart0: uart@fff0c2c000 {
compatible = "ns16550", "openpiton,ns16550";
reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <0>;
// regs are spaced on 8 bit boundary
};
eth: ethernet@fff0d00000 {
compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
device_type = "network";
reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
interrupt-parent = <&PLIC0>;
interrupts = <2>;
phy-handle = <&phy0>;
xlnx,duplex = <0x1>;
xlnx,include-global-buffers = <0x1>;
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,rx-ping-pong = <0x1>;
xlnx,s-axi-id-width = <0x1>;
xlnx,tx-ping-pong = <0x1>;
xlnx,use-internal = <0x0>;
axi_ethernetlite_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
compatible = "ethernet-phy-id001C.C915";
device_type = "ethernet-phy";
reg = <1>;
};
};
};
sdhci_0: sdhci@f000000000 {
u-boot,dm-spl;
compatible = "openpiton,piton-mmc", "openpiton,mmc";
reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
};
clint@fff1020000 {
compatible = "sifive,clint0", "openpiton,clint";
interrupts-extended = < &CPU0_intc 3
&CPU0_intc 7
&CPU1_intc 3
&CPU1_intc 7 >;
reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
clocks = <&clk0>;
};
PLIC0: plic@fff1100000 {
u-boot,dm-spl;
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0", "openpiton,plic";
interrupt-controller;
interrupts-extended = < &CPU0_intc 11
&CPU0_intc 9
&CPU1_intc 11
&CPU1_intc 9 >;
reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
riscv,max-priority = <7>;
riscv,ndev = <2>;
};
};
};

15
arch/riscv/include/asm/arch-fu740/eeprom.h Normal file
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@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2021 SiFive, Inc.
*
* Zong Li <zong.li@sifve.com>
*/
#ifndef _ASM_RISCV_EEPROM_H
#define _ASM_RISCV_EEPROM_H
#define PCB_REVISION_REV3 0x3
u8 get_pcb_revision_from_eeprom(void);
#endif /* _ASM_RISCV_EEPROM_H */

40
board/openpiton/riscv64/Kconfig Normal file
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@ -0,0 +1,40 @@
if TARGET_OPENPITON_RISCV64
config SYS_BOARD
default "riscv64"
config SYS_VENDOR
default "openpiton"
config SYS_CPU
default "generic"
config SYS_CONFIG_NAME
default "openpiton-riscv64"
config SYS_TEXT_BASE
default 0x81000000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x81000000 if RISCV_SMODE
config SPL_TEXT_BASE
default 0x82000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_EARLY_INIT_R
select SUPPORT_SPL
imply CPU_RISCV
imply RISCV_TIMER
imply SPL_SIFIVE_CLINT
imply CMD_CPU
imply SPL_CPU_SUPPORT
imply SPL_SMP
imply SPL_MMC
imply SMP
imply SPL_RISCV_MMODE
endif

8
board/openpiton/riscv64/MAINTAINERS Normal file
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@ -0,0 +1,8 @@
Openpiton BOARD
M: Tianrui Wei<tianrui-wei@outlook.com>
S: Maintained
F: board/openpiton/riscv64/
F: include/configs/openpiton-riscv64.h
F: configs/openpiton_riscv64_defconfig
F: configs/openpiton_riscv64_spl_defconfig
F: drivers/mmc/piton_mmc.c

5
board/openpiton/riscv64/Makefile Normal file
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@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 Tianrui Wei
# Tianrui Wei <tianrui-wei@outlook.com>
obj-y += openpiton-riscv64.o

33
board/openpiton/riscv64/openpiton-riscv64.c Normal file
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@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 SiFive, Inc
* Copyright (c) 2021 Tianrui Wei
*
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
* Tianrui Wei <tianrui-wei@outlook.com>
*/
#include <common.h>
#include <init.h>
#include <configs/openpiton-riscv64.h>
#include <dm.h>
#include <spl.h>
#ifdef CONFIG_SPL
void board_boot_order(u32 *spl_boot_list)
{
u8 i;
u32 boot_devices[] = {
BOOT_DEVICE_MMC1,
};
for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
spl_boot_list[i] = boot_devices[i];
}
#endif
int board_init(void)
{
return 0;
}

1
board/sifive/unmatched/Kconfig
View file

@ -47,5 +47,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply PHY_MSCC
imply SYSRESET
imply SYSRESET_GPIO
imply CMD_I2C
endif

1
board/sifive/unmatched/Makefile
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@ -3,6 +3,7 @@
# Copyright (c) 2020-2021 SiFive, Inc
obj-y += unmatched.o
obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o

574
board/sifive/unmatched/hifive-platform-i2c-eeprom.c Normal file
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@ -0,0 +1,574 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 SiFive, Inc.
*
* Based on board/freescale/common/sys_eeprom.c:
* Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
* York Sun (yorksun@freescale.com)
* Haiying Wang (haiying.wang@freescale.com)
* Timur Tabi (timur@freescale.com)
*/
#include <common.h>
#include <command.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include <u-boot/crc.h>
#ifndef CONFIG_SYS_EEPROM_BUS_NUM
#error Requires CONFIG_SYS_EEPROM_BUS_NUM to be defined
#endif
#define FORMAT_VERSION 0x1
/* Options for the manuf_test_status field */
#define SIFIVE_MANUF_TEST_STATUS_UNKNOWN 0
#define SIFIVE_MANUF_TEST_STATUS_PASS 1
#define SIFIVE_MANUF_TEST_STATUS_FAIL 2
/*
* BYTES_PER_EEPROM_PAGE: the AT24C02 datasheet says that data can
* only be written in page mode, which means 8 bytes at a time
*/
#define BYTES_PER_EEPROM_PAGE 8
/*
* EEPROM_WRITE_DELAY_MS: the AT24C02 datasheet says it takes up to
* 5ms to complete a given write
*/
#define EEPROM_WRITE_DELAY_MS 5000
/*
* MAGIC_NUMBER_BYTES: number of bytes used by the magic number
*/
#define MAGIC_NUMBER_BYTES 4
/*
* SERIAL_NUMBER_BYTES: number of bytes used by the board serial
* number
*/
#define SERIAL_NUMBER_BYTES 16
/*
* MAC_ADDR_BYTES: number of bytes used by the Ethernet MAC address
*/
#define MAC_ADDR_BYTES 6
/*
* MAC_ADDR_STRLEN: length of mac address string
*/
#define MAC_ADDR_STRLEN 17
/*
* SiFive OUI. Registration Date is 2018-02-15
*/
#define SIFIVE_OUI_PREFIX "70:B3:D5:92:F"
/**
* static eeprom: EEPROM layout for the SiFive platform I2C format
*/
static struct __attribute__ ((__packed__)) sifive_eeprom {
u8 magic[MAGIC_NUMBER_BYTES];
u8 format_ver;
u16 product_id;
u8 pcb_revision;
u8 bom_revision;
u8 bom_variant;
u8 serial[SERIAL_NUMBER_BYTES];
u8 manuf_test_status;
u8 mac_addr[MAC_ADDR_BYTES];
u32 crc;
} e;
struct sifive_product {
u16 id;
const char *name;
};
/* Set to 1 if we've read EEPROM into memory */
static int has_been_read;
/* Magic number at the first four bytes of EEPROM */
static const unsigned char magic[MAGIC_NUMBER_BYTES] = { 0xf1, 0x5e, 0x50, 0x45 };
/* Does the magic number match that of a SiFive EEPROM? */
static inline int is_match_magic(void)
{
return (memcmp(&e.magic, &magic, MAGIC_NUMBER_BYTES) == 0);
}
/* Calculate the current CRC */
static inline u32 calculate_crc32(void)
{
return crc32(0, (void *)&e, sizeof(struct sifive_eeprom) - sizeof(e.crc));
}
/* This function should be called after each update to the EEPROM structure */
static inline void update_crc(void)
{
e.crc = calculate_crc32();
}
static struct sifive_product sifive_products[] = {
{ 0, "Unknown"},
{ 2, "HiFive Unmatched" },
};
/**
* dump_raw_eeprom - display the raw contents of the EEPROM
*/
static void dump_raw_eeprom(void)
{
unsigned int i;
printf("EEPROM dump: (0x%lx bytes)\n", sizeof(e));
for (i = 0; i < sizeof(e); i++) {
if ((i % 16) == 0)
printf("%02X: ", i);
printf("%02X ", ((u8 *)&e)[i]);
if (((i % 16) == 15) || (i == sizeof(e) - 1))
printf("\n");
}
}
/**
* show_eeprom - display the contents of the EEPROM
*/
static void show_eeprom(void)
{
unsigned int i;
u32 crc;
const char *product_name = "Unknown";
char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 };
if (!is_match_magic()) {
printf("Not a SiFive HiFive EEPROM data format - magic bytes don't match\n");
dump_raw_eeprom();
return;
};
snprintf(board_serial, sizeof(board_serial), "%s", e.serial);
for (i = 0; i < ARRAY_SIZE(sifive_products); i++) {
if (sifive_products[i].id == e.product_id) {
product_name = sifive_products[i].name;
break;
}
};
printf("SiFive PCB EEPROM format v%u\n", e.format_ver);
printf("Product ID: %04hx (%s)\n", e.product_id, product_name);
printf("PCB revision: %x\n", e.pcb_revision);
printf("BOM revision: %c\n", e.bom_revision);
printf("BOM variant: %x\n", e.bom_variant);
printf("Serial number: %s\n", board_serial);
printf("Ethernet MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
e.mac_addr[0], e.mac_addr[1], e.mac_addr[2],
e.mac_addr[3], e.mac_addr[4], e.mac_addr[5]);
crc = calculate_crc32();
if (crc == e.crc) {
printf("CRC: %08x\n", e.crc);
} else {
printf("CRC: %08x (should be %08x)\n", e.crc, crc);
dump_raw_eeprom();
}
}
/**
* read_eeprom() - read the EEPROM into memory, if it hasn't been read already
*/
static int read_eeprom(void)
{
int ret;
struct udevice *dev;
if (has_been_read)
return 0;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
1,
&dev);
if (!ret)
dm_i2c_read(dev, 0, (void *)&e,
sizeof(struct sifive_eeprom));
show_eeprom();
has_been_read = (ret == 0) ? 1 : 0;
return ret;
}
/**
* prog_eeprom() - write the EEPROM from memory
*/
static int prog_eeprom(void)
{
int ret = 0;
unsigned int i;
void *p;
if (!is_match_magic()) {
printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
return 0;
}
for (i = 0, p = &e; i < sizeof(e);
i += BYTES_PER_EEPROM_PAGE, p += BYTES_PER_EEPROM_PAGE) {
struct udevice *dev;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
if (!ret)
ret = dm_i2c_write(dev, i, p,
min((int)(sizeof(e) - i),
BYTES_PER_EEPROM_PAGE));
if (ret)
break;
udelay(EEPROM_WRITE_DELAY_MS);
}
if (!ret) {
/* Verify the write by reading back the EEPROM and comparing */
struct sifive_eeprom e2;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
if (!ret)
ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
if (ret) {
printf("Programming failed.\n");
has_been_read = 0;
return -1;
}
printf("Programming passed.\n");
return 0;
}
/**
* set_mac_address() - stores a MAC address into the local EEPROM copy
*
* This function takes a pointer to MAC address string
* (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number),
* stores it in the MAC address field of the EEPROM local copy, and
* updates the local copy of the CRC.
*/
static void set_mac_address(char *string)
{
unsigned int i;
if (strncasecmp(SIFIVE_OUI_PREFIX, string, 13)) {
printf("The MAC address doesn't match SiFive OUI %s\n",
SIFIVE_OUI_PREFIX);
return;
}
for (i = 0; *string && (i < MAC_ADDR_BYTES); i++) {
e.mac_addr[i] = simple_strtoul(string, &string, 16);
if (*string == ':')
string++;
}
update_crc();
}
/**
* set_manuf_test_status() - stores a test status byte into the in-memory copy
*
* Takes a pointer to a manufacturing test status string ("unknown",
* "pass", "fail") and stores the corresponding numeric ID to the
* manuf_test_status field of the EEPROM local copy, and updates the
* CRC of the local copy.
*/
static void set_manuf_test_status(char *string)
{
if (!strcasecmp(string, "unknown")) {
e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_UNKNOWN;
} else if (!strcasecmp(string, "pass")) {
e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_PASS;
} else if (!strcasecmp(string, "fail")) {
e.manuf_test_status = SIFIVE_MANUF_TEST_STATUS_FAIL;
} else {
printf("Usage: mac manuf_test_status (unknown|pass|fail)\n");
return;
}
update_crc();
}
/**
* set_pcb_revision() - stores a SiFive PCB revision into the local EEPROM copy
*
* Takes a pointer to a string representing the numeric PCB revision in
* decimal ("0" - "255"), stores it in the pcb_revision field of the
* EEPROM local copy, and updates the CRC of the local copy.
*/
static void set_pcb_revision(char *string)
{
unsigned long p;
p = simple_strtoul(string, &string, 10);
if (p > U8_MAX) {
printf("%s must not be greater than %d\n", "PCB revision",
U8_MAX);
return;
}
e.pcb_revision = p;
update_crc();
}
/**
* set_bom_revision() - stores a SiFive BOM revision into the local EEPROM copy
*
* Takes a pointer to a uppercase ASCII character representing the BOM
* revision ("A" - "Z"), stores it in the bom_revision field of the
* EEPROM local copy, and updates the CRC of the local copy.
*/
static void set_bom_revision(char *string)
{
if (string[0] < 'A' || string[0] > 'Z') {
printf("BOM revision must be an uppercase letter between A and Z\n");
return;
}
e.bom_revision = string[0];
update_crc();
}
/**
* set_bom_variant() - stores a SiFive BOM variant into the local EEPROM copy
*
* Takes a pointer to a string representing the numeric BOM variant in
* decimal ("0" - "255"), stores it in the bom_variant field of the
* EEPROM local copy, and updates the CRC of the local copy.
*/
static void set_bom_variant(char *string)
{
unsigned long p;
p = simple_strtoul(string, &string, 10);
if (p > U8_MAX) {
printf("%s must not be greater than %d\n", "BOM variant",
U8_MAX);
return;
}
e.bom_variant = p;
update_crc();
}
/**
* set_product_id() - stores a SiFive product ID into the local EEPROM copy
*
* Takes a pointer to a string representing the numeric product ID in
* decimal ("0" - "65535"), stores it in the product ID field of the
* EEPROM local copy, and updates the CRC of the local copy.
*/
static void set_product_id(char *string)
{
unsigned long p;
p = simple_strtoul(string, &string, 10);
if (p > U16_MAX) {
printf("%s must not be greater than %d\n", "Product ID",
U16_MAX);
return;
}
e.product_id = p;
update_crc();
}
/**
* set_serial_number() - set the PCB serial number in the in-memory copy
*
* Set the board serial number in the in-memory EEPROM copy from the supplied
* string argument, and update the CRC.
*/
static void set_serial_number(char *string)
{
if (strlen(string) > SERIAL_NUMBER_BYTES) {
printf("Serial number must not be greater than 16 bytes\n");
return;
}
memset(e.serial, 0, sizeof(e.serial));
strncpy((char *)e.serial, string, sizeof(e.serial));
update_crc();
}
/**
* init_local_copy() - initialize the in-memory EEPROM copy
*
* Initialize the in-memory EEPROM copy with the magic number. Must
* be done when preparing to initialize a blank EEPROM, or overwrite
* one with a corrupted magic number.
*/
static void init_local_copy(void)
{
memset(&e, 0, sizeof(e));
memcpy(e.magic, magic, sizeof(e.magic));
e.format_ver = FORMAT_VERSION;
update_crc();
}
int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
char *cmd;
if (argc == 1) {
show_eeprom();
return 0;
}
if (argc > 3)
return cmd_usage(cmdtp);
cmd = argv[1];
/* Commands with no argument */
if (!strcmp(cmd, "read_eeprom")) {
read_eeprom();
return 0;
} else if (!strcmp(cmd, "initialize")) {
init_local_copy();
return 0;
} else if (!strcmp(cmd, "write_eeprom")) {
prog_eeprom();
return 0;
}
if (argc != 3)
return cmd_usage(cmdtp);
if (!is_match_magic()) {
printf("Please read the EEPROM ('read_eeprom') and/or initialize the EEPROM ('initialize') first.\n");
return 0;
}
if (!strcmp(cmd, "serial_number")) {
set_serial_number(argv[2]);
return 0;
} else if (!strcmp(cmd, "manuf_test_status")) {
set_manuf_test_status(argv[2]);
return 0;
} else if (!strcmp(cmd, "mac_address")) {
set_mac_address(argv[2]);
return 0;
} else if (!strcmp(cmd, "pcb_revision")) {
set_pcb_revision(argv[2]);
return 0;
} else if (!strcmp(cmd, "bom_variant")) {
set_bom_variant(argv[2]);
return 0;
} else if (!strcmp(cmd, "bom_revision")) {
set_bom_revision(argv[2]);
return 0;
} else if (!strcmp(cmd, "product_id")) {
set_product_id(argv[2]);
return 0;
}
return cmd_usage(cmdtp);
}
/**
* mac_read_from_eeprom() - read the MAC address from EEPROM
*
* This function reads the MAC address from EEPROM and sets the
* appropriate environment variables for each one read.
*
* The environment variables are only set if they haven't been set already.
* This ensures that any user-saved variables are never overwritten.
*
* This function must be called after relocation.
*/
int mac_read_from_eeprom(void)
{
u32 crc;
char board_serial[SERIAL_NUMBER_BYTES + 1] = { 0 };
puts("EEPROM: ");
if (read_eeprom()) {
printf("Read failed.\n");
return 0;
}
if (!is_match_magic()) {
printf("Invalid ID (%02x %02x %02x %02x)\n",
e.magic[0], e.magic[1], e.magic[2], e.magic[3]);
dump_raw_eeprom();
return 0;
}
crc = calculate_crc32();
if (crc != e.crc) {
printf("CRC mismatch (%08x != %08x)\n", crc, e.crc);
dump_raw_eeprom();
return 0;
}
eth_env_set_enetaddr("ethaddr", e.mac_addr);
if (!env_get("serial#")) {
snprintf(board_serial, sizeof(board_serial), "%s", e.serial);
env_set("serial#", board_serial);
}
return 0;
}
/**
* get_pcb_revision_from_eeprom - get the PCB revision
*
* Read the EEPROM to determine the board revision.
*
* This function is called before relocation, so we need to read a private
* copy of the EEPROM into a local variable on the stack.
*/
u8 get_pcb_revision_from_eeprom(void)
{
struct __attribute__ ((__packed__)) board_eeprom {
u8 magic[MAGIC_NUMBER_BYTES];
u8 format_ver;
u16 product_id;
u8 pcb_revision;
} be;
int ret;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
1,
&dev);
if (!ret)
dm_i2c_read(dev, 0, (void *)&be,
sizeof(struct board_eeprom));
return be.pcb_revision;
}

28
board/sifive/unmatched/spl.c
View file

@ -10,11 +10,14 @@
#include <spl.h>
#include <misc.h>
#include <log.h>
#include <fdtdec.h>
#include <dm/root.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/eeprom.h>
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
@ -26,6 +29,16 @@ int spl_board_init_f(void)
{
int ret;
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
int rescan;
ret = fdtdec_resetup(&rescan);
if (!ret && rescan) {
dm_uninit();
dm_init_and_scan(true);
}
#endif
ret = spl_soc_init();
if (ret) {
debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
@ -79,7 +92,18 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* boot using first FIT config */
return 0;
/*
* Apply different DDR params on different board revision.
* Use PCB revision which is byte 0x7 in I2C platform EEPROM
* to distinguish that.
*/
if (get_pcb_revision_from_eeprom() == PCB_REVISION_REV3 &&
!strcmp(name, "hifive-unmatched-a00"))
return 0;
else if (get_pcb_revision_from_eeprom() != PCB_REVISION_REV3 &&
!strcmp(name, "hifive-unmatched-a00-rev1"))
return 0;
return -1;
}
#endif

76
configs/openpiton_riscv64_defconfig Normal file
View file

@ -0,0 +1,76 @@
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
CONFIG_OF_BOARD_FIXUP=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_DATE is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_EMBED=y
# CONFIG_NET is not set
CONFIG_CPU=y
CONFIG_MMC=y
# CONFIG_MMC_WRITE is not set
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_PITON=y
CONFIG_RAM=y
# CONFIG_RAM_SIFIVE is not set
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_FS_SQUASHFS=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MD5=y
CONFIG_GETOPT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set

87
configs/openpiton_riscv64_spl_defconfig Normal file
View file

@ -0,0 +1,87 @@
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_PAYLOAD=""
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_NR_CPUS=32
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_BANNER_PRINT is not set
CONFIG_SPL_CPU=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_RTC_SUPPORT=y
CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_DATE is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
# CONFIG_NET is not set
CONFIG_CPU=y
CONFIG_MMC=y
# CONFIG_MMC_WRITE is not set
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_PITON=y
CONFIG_RAM=y
# CONFIG_RAM_SIFIVE is not set
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_FS_SQUASHFS=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MD5=y
CONFIG_GETOPT=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set

1
configs/sifive_unleashed_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unleashed-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_MISC_INIT_R=y

5
configs/sifive_unmatched_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
@ -40,3 +41,7 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SPL_OF_LIST="hifive-unmatched-a00 hifive-unmatched-a00-rev1"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000

1
doc/board/index.rst
View file

@ -19,6 +19,7 @@ Board-specific doc
intel/index
kontron/index
microchip/index
openpiton/index
rockchip/index
sifive/index
sipeed/index

9
doc/board/openpiton/index.rst Normal file
View file

@ -0,0 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
OpenPiton
=========
.. toctree::
:maxdepth: 2
riscv64

376
doc/board/openpiton/riscv64.rst Normal file
View file

@ -0,0 +1,376 @@
.. SPDX-License-Identifier: GPL-2.0+
Openpiton RISC-V SoC
====================
OpenPiton RISC-V SoC
--------------------
OpenPiton is an open source, manycore processor and research platform. It is a
tiled manycore framework scalable from one to 1/2 billion cores. It supports a
number of ISAs including RISC-V with its P-Mesh cache coherence protocol and
networks on chip. It is highly configurable in both core and uncore components.
OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes
running full-stack Debian linux.
RISC-V Standard Bootflow
-------------------------
Currently, OpenPiton implements RISC-V standard bootflow in the following steps
mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition
---------------------
If you'd like to build OpenPiton, please go to OpenPiton github repo
(at https://github.com/PrincetonUniversity/openpiton) to build from the latest
changes
Building Images
---------------------------
SPL
---
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
export ARCH=riscv
3. make openpiton_riscv64_spl_defconfig
4. make
U-Boot
------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
export ARCH=riscv
3. make openpiton_riscv64_defconfig
4. make
opensbi
-------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
export ARCH=riscv
3. Go to OpenSBI directory
4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
Using fw_payload.bin with linux
-------------------------------
Put the generated fw_payload.bin into the /boot directory on the root filesystem,
plug in the SD card, then flash the bitstream. Linux will boot automatically.
Booting
-------
Once you plugin the sdcard and power up, you should see the U-Boot prompt.
Sample Dual-core Debian boot log from OpenPiton
-----------------------------------------------
.. code-block:: none
Trying to boot from MMC1
OpenSBI v0.9-5-gd06cb61
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : OPENPITON RISC-V
Platform Features : timer,mfdeleg
Platform HART Count : 3
Firmware Base : 0x80000000
Firmware Size : 104 KB
Runtime SBI Version : 0.2
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*,1*,2*
Domain0 Region00 : 0x0000000080000000-0x000000008001ffff ()
Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x0000000082200000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsu
Boot HART Features : scounteren,mcounteren
Boot HART PMP Count : 0
Boot HART PMP Granularity : 0
Boot HART PMP Address Bits: 0
Boot HART MHPM Count : 0
Boot HART MHPM Count : 0
Boot HART MIDELEG : 0x0000000000000222
Boot HART MEDELEG : 0x000000000000b109
U-Boot 2021.01+ (Jun 12 2021 - 10:31:34 +0800)
DRAM: 1 GiB
MMC: sdhci@f000000000: 0 (eMMC)
In: uart@fff0c2c000
Out: uart@fff0c2c000
Err: uart@fff0c2c000
Hit any key to stop autoboot: 0
6492992 bytes read in 5310 ms (1.2 MiB/s)
## Flattened Device Tree blob at 86000000
Booting using the fdt blob at 0x86000000
Loading Device Tree to 00000000bfffa000, end 00000000bffff007 ... OK
Starting kernel ...
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
[ 0.000000] Linux version 5.6.0-rc4-gb9d34f7e294d-dirty
[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
[ 0.000000] printk: bootconsole [sbi0] enabled
[ 0.000000] Zone ranges:
[ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff]
[ 0.000000] Normal empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff]
[ 0.000000] On node 0 totalpages: 261632
[ 0.000000] DMA32 zone: 4088 pages used for memmap
[ 0.000000] DMA32 zone: 0 pages reserved
[ 0.000000] DMA32 zone: 261632 pages, LIFO batch:63
[ 0.000000] software IO TLB: mapped [mem 0xbaffa000-0xbeffa000] (64MB)
[ 0.000000] SBI specification v0.2 detected
[ 0.000000] SBI implementation ID=0x1 Version=0x9
[ 0.000000] SBI v0.2 TIME extension detected
[ 0.000000] SBI v0.2 IPI extension detected
[ 0.000000] SBI v0.2 RFENCE extension detected
[ 0.000000] SBI v0.2 HSM extension detected
[ 0.000000] elf_hwcap is 0x112d
[ 0.000000] percpu: Embedded 16 pages/cpu s25368 r8192 d31976 u65536
[ 0.000000] pcpu-alloc: s25368 r8192 d31976 u65536 alloc=16*4096
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 257544
[ 0.000000] Kernel command line: earlycon=sbi root=/dev/piton_sd1
[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.000000] Sorting __ex_table...
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 956252K/1046528K available (4357K kernel code, 286K rwdata, 1200K rodata, 168K init, 311K bss, 90276K re)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
[ 0.000000] plic: mapped 2 interrupts with 1 handlers for 2 contexts.
[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1ec037a6a, max_idle_ns: 7052723236599 ns
[ 0.000138] sched_clock: 64 bits at 520kHz, resolution 1919ns, wraps every 4398046510738ns
[ 0.009429] printk: console [hvc0] enabled
[ 0.009429] printk: console [hvc0] enabled
[ 0.017850] printk: bootconsole [sbi0] disabled
[ 0.017850] printk: bootconsole [sbi0] disabled
[ 0.028029] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.04 BogoMIPS (lpj=5208)
[ 0.038753] pid_max: default: 32768 minimum: 301
[ 0.050248] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
[ 0.058661] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
[ 0.069359] *** VALIDATE tmpfs ***
[ 0.089093] *** VALIDATE proc ***
[ 0.101135] *** VALIDATE cgroup ***
[ 0.105019] *** VALIDATE cgroup2 ***
[ 0.144310] rcu: Hierarchical SRCU implementation.
[ 0.162836] smp: Bringing up secondary CPUs ...
[ 0.167736] smp: Brought up 1 node, 1 CPU
[ 0.185982] devtmpfs: initialized
[ 0.216237] random: get_random_u32 called from bucket_table_alloc.isra.25+0x4e/0x15c with crng_init=0
[ 0.236026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.246916] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
[ 0.266994] NET: Registered protocol family 16
[ 0.763362] clocksource: Switched to clocksource riscv_clocksource
[ 0.770122] *** VALIDATE bpf ***
[ 0.782837] *** VALIDATE ramfs ***
[ 0.829997] NET: Registered protocol family 2
[ 0.853577] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
[ 0.864085] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.875373] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear)
[ 0.887958] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.902149] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
[ 0.909904] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
[ 0.924809] NET: Registered protocol family 1
[ 0.948605] RPC: Registered named UNIX socket transport module.
[ 0.956003] RPC: Registered udp transport module.
[ 0.961565] RPC: Registered tcp transport module.
[ 0.966432] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.987180] Initialise system trusted keyrings
[ 0.998953] workingset: timestamp_bits=46 max_order=18 bucket_order=0
[ 1.323977] *** VALIDATE nfs ***
[ 1.328520] *** VALIDATE nfs4 ***
[ 1.334422] NFS: Registering the id_resolver key type
[ 1.340148] Key type id_resolver registered
[ 1.345280] Key type id_legacy registered
[ 1.349820] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 1.357610] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[ 1.866909] Key type asymmetric registered
[ 1.872460] Asymmetric key parser 'x509' registered
[ 1.878750] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
[ 1.887480] io scheduler mq-deadline registered
[ 1.892864] io scheduler kyber registered
[ 3.905595] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.954332] fff0c2c000.uart: ttyS0 at MMIO 0xfff0c2c000 (irq = 1, base_baud = 4166687) is a 16550
[ 4.254794] loop: module loaded
[ 4.258269] piton_sd:v1.0 Apr 26, 2019
[ 4.258269]
[ 4.265170] gpt partition table header:
[ 4.265283] signature: 5452415020494645
[ 4.269258] revision: 10000
[ 4.273746] size: 5c
[ 4.276659] crc_header: 26b42404
[ 4.278911] reserved: 0
[ 4.282730] current lba: 1
[ 4.285311] backup lda: 3b723ff
[ 4.288093] partition entries lba: 2
[ 4.291835] number partition entries: 80
[ 4.295529] size partition entries: 80
[ 9.473253] piton_sd: piton_sd1
[ 10.099676] libphy: Fixed MDIO Bus: probed
[ 10.148782] NET: Registered protocol family 10
[ 10.183418] Segment Routing with IPv6
[ 10.189384] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 10.214449] NET: Registered protocol family 17
[ 10.227413] Key type dns_resolver registered
[ 10.240561] Loading compiled-in X.509 certificates
[ 10.465264] EXT4-fs (piton_sd1): mounted filesystem with ordered data mode. Opts: (null)
[ 10.475922] VFS: Mounted root (ext4 filesystem) readonly on device 254:1.
[ 10.551865] devtmpfs: mounted
[ 10.562744] Freeing unused kernel memory: 168K
[ 10.567450] This architecture does not have kernel memory protection.
[ 10.574688] Run /sbin/init as init process
[ 10.578916] with arguments:
[ 10.582489] /sbin/init
[ 10.585312] with environment:
[ 10.588518] HOME=/
[ 10.591459] TERM=linux
[ 18.154373] systemd[1]: System time before build time, advancing clock.
[ 18.565415] systemd[1]: systemd 238 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIB)
[ 18.596359] systemd[1]: Detected architecture riscv64.
Welcome to Debian GNU/Linux buster/sid!
[ 18.797150] systemd[1]: Set hostname to <openpiton>.
[ 31.609244] random: systemd: uninitialized urandom read (16 bytes read)
[ 31.630366] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
[ OK ] Listening on /dev/initctl Compatibility Named Pipe.
[ 31.674820] random: systemd: uninitialized urandom read (16 bytes read)
[ 31.806800] systemd[1]: Created slice system-serial\x2dgetty.slice.
[ OK ] Created slice system-serial\x2dgetty.slice.
[ 31.839855] random: systemd: uninitialized urandom read (16 bytes read)
[ 31.850670] systemd[1]: Reached target Slices.
[ OK ] Reached target Slices.
[ 32.128005] systemd[1]: Reached target Swap.
[ OK ] Reached target Swap.
[ 32.180337] systemd[1]: Listening on Journal Socket.
[ OK ] Listening on Journal Socket.
[ 32.416448] systemd[1]: Mounting Kernel Debug File System...
Mounting Kernel Debug File System...
[ 32.937934] systemd[1]: Starting Remount Root and Kernel File Systems...
Starting Remount Root and Kernel File Systems...
[ 33.117472] urandom_read: 4 callbacks suppressed
[ 33.117645] random: systemd: uninitialized urandom read (16 bytes read)
[ 33.214868] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[ OK ] Started Forward Password Requests to Wall Directory Watch.
[ 33.366745] random: systemd: uninitialized urandom read (16 bytes read)
[ 33.453262] systemd[1]: Listening on Journal Socket (/dev/log).
[ OK ] Listening on Journal Socket (/dev/log).
[ 33.627020] random: systemd: uninitialized urandom read (16 bytes read)
[ 34.029973] systemd[1]: Starting Load Kernel Modules...
Starting Load Kernel Modules...
[ OK ] Created slice system-getty.slice.
[ OK ] Started Dispatch Password Requests to Console Directory Watch.
[ OK ] Reached target Local Encrypted Volumes.
[ OK ] Reached target Paths.
[ OK ] Reached target Remote File Systems.
[ OK ] Listening on udev Kernel Socket.
[ OK ] Listening on udev Control Socket.
[ OK ] Reached target Sockets.
Starting udev Coldplug all Devices...
Starting Journal Service...
[ 37.108761] systemd[1]: Starting Create Static Device Nodes in /dev...
Starting Create Static Device Nodes in /dev...
[ 37.941929] systemd[1]: Mounted Kernel Debug File System.
[ OK ] Mounted Kernel Debug File System.
[ 38.463855] systemd[1]: Started Remount Root and Kernel File Systems.
[ OK ] Started Remount Root and Kernel File Systems.
[ 39.614728] systemd[1]: Started Load Kernel Modules.
[ OK ] Started Load Kernel Modules.
[ 40.794332] systemd[1]: Starting Apply Kernel Variables...
Starting Apply Kernel Variables...
[ 41.928338] systemd[1]: Starting Load/Save Random Seed...
Starting Load/Save Random Seed...
[ 43.494757] systemd[1]: Started Create Static Device Nodes in /dev.
[ OK ] Started Create Static Device Nodes in /dev.
[ 44.795372] systemd[1]: Starting udev Kernel Device Manager...
Starting udev Kernel Device Manager...
[ 45.043065] systemd[1]: Reached target Local File Systems (Pre).
[ OK ] Reached target Local File Systems (Pre).
[ 45.224716] systemd[1]: Reached target Local File Systems.
[ OK ] Reached target Local File Systems.
[ 46.036491] systemd[1]: Started Apply Kernel Variables.
[ OK ] Started Apply Kernel Variables.
[ 46.947879] systemd[1]: Started Load/Save Random Seed.
[ OK ] Started Load/Save Random Seed.
[ 47.910242] systemd[1]: Starting Raise network interfaces...
Starting Raise network interfaces...
[ 48.119915] systemd[1]: Started Journal Service.
[ OK ] Started Journal Service.
Starting Flush Journal to Persistent Storage...
[ OK ] Started udev Kernel Device Manager.
[ 55.369915] systemd-journald[88]: Received request to flush runtime journal from PID 1
[ OK ] Started Flush Journal to Persistent Storage.
Starting Create Volatile Files and Directories...
[ OK ] Started Raise network interfaces.
[ OK ] Reached target Network.
[FAILED] Failed to start Create Volatile Files and Directories.
See 'systemctl status systemd-tmpfiles-setup.service' for details.
Starting Update UTMP about System Boot/Shutdown...
[FAILED] Failed to start Network Time Synchronization.
See 'systemctl status systemd-timesyncd.service' for details.
[ OK ] Reached target System Time Synchronized.
[ OK ] Stopped Network Time Synchronization.
[ OK ] Started udev Coldplug all Devices.
[ OK ] Found device /dev/hvc0.
[ OK ] Reached target System Initialization.
[ OK ] Reached target Basic System.
[ OK ] Started Regular background program processing daemon.
[ OK ] Started Daily Cleanup of Temporary Directories.
Starting Permit User Sessions...
[ OK ] Started Daily apt download activities.
[ OK ] Started Daily apt upgrade and clean activities.
[ OK ] Reached target Timers.
[ OK ] Started Permit User Sessions.
[ OK ] Started Serial Getty on hvc0.
[ OK ] Reached target Login Prompts.
[ OK ] Reached target Multi-User System.
[ OK ] Reached target Graphical Interface.
Debian GNU/Linux buster/sid openpiton hvc0
openpiton login:

6
drivers/clk/sifive/fu740-prci.c
View file

@ -20,7 +20,7 @@
#include "sifive-prci.h"
#include <asm/io.h>
int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable)
int sifive_prci_fu740_pcieauxclk_enable(struct __prci_clock *pc, bool enable)
{
struct __prci_wrpll_data *pwd = pc->pwd;
struct __prci_data *pd = pc->pd;
@ -98,7 +98,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
};
static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
.enable_clk = sifive_prci_fu740_pciauxclk_enable,
.enable_clk = sifive_prci_fu740_pcieauxclk_enable,
};
/* List of clock controls provided by the PRCI */
@ -150,7 +150,7 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
[PRCI_CLK_PCIEAUX] {
.name = "pciaux",
.name = "pcieaux",
.parent_name = "",
.ops = &sifive_fu740_prci_pcieaux_clk_ops,
.pwd = &__prci_pcieaux_data,

9
drivers/mmc/Kconfig
View file

@ -727,6 +727,15 @@ config MMC_SUNXI_HAS_MODE_SWITCH
bool
depends on MMC_SUNXI
config MMC_PITON
bool "MMC support for OpenPiton SoC"
depends on DM_MMC && BLK
help
This selects support for the SD host controller on OpenPiton SoC.
Note that this SD controller directly exposes the contents of the
SD card as memory mapped, so there is no manual configuration
required
config GENERIC_ATMEL_MCI
bool "Atmel Multimedia Card Interface support"
depends on DM_MMC && BLK && ARCH_AT91

1
drivers/mmc/Makefile
View file

@ -72,6 +72,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MMC_PITON) += piton_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o

161
drivers/mmc/piton_mmc.c Normal file
View file

@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
* Portions Copyright 2011-2019 NVIDIA Corporation
* Portions Copyright 2021 Tianrui Wei
* This file is adapted from tegra_mmc.c
* Tianrui Wei <tianrui-wei@outlook.com>
*/
#include <asm/gpio.h>
#include <asm/io.h>
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/types.h>
#include <linux/sizes.h>
#include <log.h>
#include <mmc.h>
#define PITON_MMC_DUMMY_F_MAX 20000000
#define PITON_MMC_DUMMY_F_MIN 10000000
#define PITON_MMC_DUMMY_CAPACITY SZ_4G << 3
#define PITON_MMC_DUMMY_B_MAX SZ_4G
struct piton_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
};
struct piton_mmc_priv {
void __iomem *base_addr;
};
static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
if (!data)
return 0;
struct piton_mmc_priv *priv = dev_get_priv(dev);
u32 *buff, *start_addr, *write_src;
size_t byte_cnt, start_block;
buff = (u32 *)data->dest;
write_src = (u32 *)data->src;
start_block = cmd->cmdarg;
start_addr = priv->base_addr + start_block;
/* if there is a read */
for (byte_cnt = data->blocks * data->blocksize; byte_cnt;
byte_cnt -= sizeof(u32)) {
if (data->flags & MMC_DATA_READ) {
*buff++ = readl(start_addr++);
}
else if (data->flags & MMC_DATA_WRITE) {
writel(*write_src++,start_addr++);
}
}
return 0;
}
static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
{
struct piton_mmc_priv *priv = dev_get_priv(dev);
struct piton_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg;
struct mmc *mmc;
struct blk_desc *bdesc;
priv->base_addr = (void *)dev_read_addr(dev);
cfg = &plat->cfg;
cfg->name = "PITON MMC";
cfg->host_caps = MMC_MODE_8BIT;
cfg->f_max = PITON_MMC_DUMMY_F_MAX;
cfg->f_min = PITON_MMC_DUMMY_F_MIN;
cfg->voltages = MMC_VDD_21_22;
mmc = &plat->mmc;
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
mmc->capacity_user = PITON_MMC_DUMMY_CAPACITY;
mmc->capacity_user *= mmc->read_bl_len;
mmc->capacity_boot = 0;
mmc->capacity_rpmb = 0;
for (int i = 0; i < 4; i++)
mmc->capacity_gp[i] = 0;
mmc->capacity = PITON_MMC_DUMMY_CAPACITY;
mmc->has_init = 1;
bdesc = mmc_get_blk_desc(mmc);
bdesc->lun = 0;
bdesc->hwpart = 0;
bdesc->type = 0;
bdesc->blksz = mmc->read_bl_len;
bdesc->log2blksz = LOG2(bdesc->blksz);
bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
return 0;
}
static int piton_mmc_getcd(struct udevice *dev)
{
return 1;
}
static const struct dm_mmc_ops piton_mmc_ops = {
.send_cmd = piton_mmc_send_cmd,
.get_cd = piton_mmc_getcd,
};
static int piton_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct piton_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
cfg->name = dev->name;
upriv->mmc = &plat->mmc;
upriv->mmc->has_init = 1;
upriv->mmc->capacity = PITON_MMC_DUMMY_CAPACITY;
upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
return 0;
}
static int piton_mmc_bind(struct udevice *dev)
{
struct piton_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
cfg->name = dev->name;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->f_min = PITON_MMC_DUMMY_F_MIN;
cfg->f_max = PITON_MMC_DUMMY_F_MAX;
cfg->b_max = MMC_MAX_BLOCK_LEN;
return mmc_bind(dev, &plat->mmc, cfg);
}
static const struct udevice_id piton_mmc_ids[] = {
{.compatible = "openpiton,piton-mmc"},
{/* sentinel */}
};
U_BOOT_DRIVER(piton_mmc_drv) = {
.name = "piton_mmc",
.id = UCLASS_MMC,
.of_match = piton_mmc_ids,
.of_to_plat = piton_mmc_ofdata_to_platdata,
.bind = piton_mmc_bind,
.probe = piton_mmc_probe,
.ops = &piton_mmc_ops,
.plat_auto = sizeof(struct piton_mmc_plat),
.priv_auto = sizeof(struct piton_mmc_priv),
};

61
include/configs/openpiton-riscv64.h Normal file
View file

@ -0,0 +1,61 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
* Copyright (c) 2021 Tianrui Wei
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
* Tianrui Wei <tianrui-wei@outlook.com>
*/
#ifndef __OPENPITON_RISCV64_CONFIG_H
#define __OPENPITON_RISCV64_CONFIG_H
#include <linux/sizes.h>
/* Environment options */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M)
#define CONFIG_SYS_LOAD_ADDR 0x87000000
#define CONFIG_SYS_MALLOC_LEN SZ_256M
#define CONFIG_SYS_BOOTM_LEN SZ_256M
#ifdef CONFIG_SPL
#define CONFIG_SPL_MAX_SIZE 0x00100000
#define CONFIG_SPL_BSS_START_ADDR 0x82000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000
#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin"
#define CONFIG_SPL_GD_ADDR 0x85000000
#endif
/* -------------------------------------------------
* Environment
*/
//Disable persistent environment variable storage
#define CONFIG_ENV_IS_NOWHERE 1
/* ---------------------------------------------------------------------
* Board boot configuration
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_addr_r=0x86000000\0" \
"kernel_addr_r=0x80200000\0" \
"image=boot/Image\0" \
"mmcdev=0\0" \
"mmcpart=1\0"
#define CONFIG_USE_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"fdt addr ${fdtcontroladdr}; " \
"fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \
"load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \
"booti ${kernel_addr_r} - ${fdt_addr_r}; "
#endif/* __CONFIG_H */

1
include/configs/sifive-unleashed.h
View file

@ -75,6 +75,7 @@
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV \
BOOTENV_SF

7
include/configs/sifive-unmatched.h
View file

@ -73,6 +73,7 @@
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
#define CONFIG_PREBOOT \
@ -80,4 +81,10 @@
"fdt addr ${fdtcontroladdr};"
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1
#define CONFIG_ID_EEPROM
#endif /* __SIFIVE_UNMATCHED_H */