mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
- New SoC platform support: rk3568; - rockchip pcie Code compile issue fix; - Board fix for rk3399 Khadas Edge; - Add Rockchip NFC driver;
This commit is contained in:
commit
28afb71646
39 changed files with 10837 additions and 9 deletions
|
@ -146,6 +146,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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rk3399-rockpro64.dtb \
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rk3399pro-rock-pi-n10.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3568-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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rv1108-elgin-r1.dtb \
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rv1108-evb.dtb
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|
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23
arch/arm/dts/rk3568-evb-u-boot.dtsi
Normal file
23
arch/arm/dts/rk3568-evb-u-boot.dtsi
Normal file
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#include "rk3568-u-boot.dtsi"
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/ {
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chosen {
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stdout-path = &uart2;
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u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
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};
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};
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&sdmmc0 {
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status = "okay";
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};
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&uart2 {
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clock-frequency = <24000000>;
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u-boot,dm-spl;
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status = "okay";
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};
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79
arch/arm/dts/rk3568-evb.dts
Normal file
79
arch/arm/dts/rk3568-evb.dts
Normal file
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3568.dtsi"
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/ {
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model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
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compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
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chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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dc_12v: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc3v3_sys: vcc3v3-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc3v3_lcd0_n: vcc3v3-lcd0-n {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd0_n";
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc3v3_lcd1_n: vcc3v3-lcd1-n {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd1_n";
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&sdhci {
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bus-width = <8>;
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max-frequency = <200000000>;
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non-removable;
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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3111
arch/arm/dts/rk3568-pinctrl.dtsi
Normal file
3111
arch/arm/dts/rk3568-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load diff
37
arch/arm/dts/rk3568-u-boot.dtsi
Normal file
37
arch/arm/dts/rk3568-u-boot.dtsi
Normal file
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@ -0,0 +1,37 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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/ {
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aliases {
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mmc0 = &sdhci;
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mmc1 = &sdmmc0;
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};
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dmc: dmc {
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compatible = "rockchip,rk3568-dmc";
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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};
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&cru {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pmucru {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&grf {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pmugrf {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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779
arch/arm/dts/rk3568.dtsi
Normal file
779
arch/arm/dts/rk3568.dtsi
Normal file
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@ -0,0 +1,779 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rk3568-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3568";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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serial8 = &uart8;
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serial9 = &uart9;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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clocks = <&scmi_clk 0>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000 900000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000 900000 1150000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <900000 900000 1150000>;
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opp-suspend;
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <900000 900000 1150000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <900000 900000 1150000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <975000 975000 1150000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1050000 1050000 1150000>;
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};
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opp-1992000000 {
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opp-hz = /bits/ 64 <1992000000>;
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opp-microvolt = <1150000 1150000 1150000>;
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};
|
||||
};
|
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|
||||
firmware {
|
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scmi: scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x82000010>;
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shmem = <&scmi_shmem>;
|
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#address-cells = <1>;
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#size-cells = <0>;
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|
||||
scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
|
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};
|
||||
};
|
||||
|
||||
};
|
||||
|
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pmu {
|
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compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
xin24m: xin24m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
xin32k: xin32k {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-0 = <&clk32k_out0>;
|
||||
pinctrl-names = "default";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sram@10f000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0x0010f000 0x0 0x100>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x0010f000 0x100>;
|
||||
|
||||
scmi_shmem: sram@0 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@fd400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||||
<0x0 0xfd460000 0 0x80000>; /* GICR */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
mbi-alias = <0x0 0xfd100000>;
|
||||
mbi-ranges = <296 24>;
|
||||
msi-controller;
|
||||
};
|
||||
|
||||
pmugrf: syscon@fdc20000 {
|
||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
grf: syscon@fdc60000 {
|
||||
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc60000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pmucru: clock-controller@fdd00000 {
|
||||
compatible = "rockchip,rk3568-pmucru";
|
||||
reg = <0x0 0xfdd00000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@fdd20000 {
|
||||
compatible = "rockchip,rk3568-cru";
|
||||
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@fdd40000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfdd40000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@fdd50000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfdd50000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 0>, <&dmac0 1>;
|
||||
pinctrl-0 = <&uart0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@fdd70000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfdd70000 0x0 0x10>;
|
||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm0m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@fdd70010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfdd70010 0x0 0x10>;
|
||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm1m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@fdd70020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfdd70020 0x0 0x10>;
|
||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm2m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@fdd70030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfdd70030 0x0 0x10>;
|
||||
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: mmc@fe000000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe000000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
||||
<&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
resets = <&cru SRST_SDMMC2>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc0: mmc@fe2b0000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
||||
<&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
resets = <&cru SRST_SDMMC0>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: mmc@fe2c0000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
||||
<&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
resets = <&cru SRST_SDMMC1>;
|
||||
reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: mmc@fe310000 {
|
||||
compatible = "rockchip,rk3568-dwcmshc";
|
||||
reg = <0x0 0xfe310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
|
||||
assigned-clock-rates = <200000000>, <24000000>;
|
||||
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
||||
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
||||
<&cru TCLK_EMMC>;
|
||||
clock-names = "core", "bus", "axi", "block", "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac0: dmac@fe530000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfe530000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_BUS>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac1: dmac@fe550000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfe550000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,pl330-periph-burst;
|
||||
clocks = <&cru ACLK_BUS>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
i2c1: i2c@fe5a0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@fe5b0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c2m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@fe5c0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c3m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@fe5d0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c4m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@fe5e0000 {
|
||||
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
||||
clock-names = "i2c", "pclk";
|
||||
pinctrl-0 = <&i2c5m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: watchdog@fe600000 {
|
||||
compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
|
||||
reg = <0x0 0xfe600000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
||||
clock-names = "tclk", "pclk";
|
||||
};
|
||||
|
||||
uart1: serial@fe650000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe650000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 2>, <&dmac0 3>;
|
||||
pinctrl-0 = <&uart1m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@fe660000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe660000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 4>, <&dmac0 5>;
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@fe670000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe670000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 6>, <&dmac0 7>;
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@fe680000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe680000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 8>, <&dmac0 9>;
|
||||
pinctrl-0 = <&uart4m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@fe690000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe690000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 10>, <&dmac0 11>;
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@fe6a0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6a0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 12>, <&dmac0 13>;
|
||||
pinctrl-0 = <&uart6m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@fe6b0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6b0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 14>, <&dmac0 15>;
|
||||
pinctrl-0 = <&uart7m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@fe6c0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6c0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 16>, <&dmac0 17>;
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart9: serial@fe6d0000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe6d0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
dmas = <&dmac0 18>, <&dmac0 19>;
|
||||
pinctrl-0 = <&uart9m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@fe6e0000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0000 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm4_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm5: pwm@fe6e0010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0010 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm5_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm6: pwm@fe6e0020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0020 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm6_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm7: pwm@fe6e0030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6e0030 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm7_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm8: pwm@fe6f0000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0000 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm8m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm9: pwm@fe6f0010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0010 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm9m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm10: pwm@fe6f0020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0020 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm10m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm11: pwm@fe6f0030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe6f0030 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm11m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm12: pwm@fe700000 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700000 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm12m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm13: pwm@fe700010 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700010 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm13m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm14: pwm@fe700020 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700020 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm14m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm15: pwm@fe700030 {
|
||||
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
reg = <0x0 0xfe700030 0x0 0x10>;
|
||||
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
clock-names = "pwm", "pclk";
|
||||
pinctrl-0 = <&pwm15m0_pins>;
|
||||
pinctrl-names = "active";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,pmu = <&pmugrf>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio@fdd60000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfdd60000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@fe740000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe740000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@fe750000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe750000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@fe760000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe760000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@fe770000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe770000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "rk3568-pinctrl.dtsi"
|
344
arch/arm/dts/rockchip-pinconf.dtsi
Normal file
344
arch/arm/dts/rockchip-pinconf.dtsi
Normal file
|
@ -0,0 +1,344 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
|
||||
bias-disable;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
|
||||
bias-disable;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
|
||||
bias-disable;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
|
||||
bias-disable;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
|
||||
bias-disable;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
|
||||
bias-disable;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
|
||||
bias-disable;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
|
||||
bias-disable;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
|
||||
bias-disable;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
|
||||
bias-disable;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
|
||||
bias-disable;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
|
||||
bias-disable;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
|
||||
bias-disable;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
|
||||
bias-disable;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
|
||||
bias-pull-up;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
|
||||
bias-pull-up;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
|
||||
bias-pull-up;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
|
||||
bias-pull-up;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
|
||||
bias-pull-up;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
|
||||
bias-pull-up;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
|
||||
bias-pull-up;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
|
||||
bias-pull-up;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
|
||||
bias-pull-up;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
|
||||
bias-pull-up;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
|
||||
bias-pull-up;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
|
||||
bias-pull-down;
|
||||
drive-strength = <0>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
|
||||
bias-pull-down;
|
||||
drive-strength = <1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
|
||||
bias-pull-down;
|
||||
drive-strength = <3>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
|
||||
bias-pull-down;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
|
||||
bias-pull-down;
|
||||
drive-strength = <5>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
|
||||
bias-pull-down;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
|
||||
bias-pull-down;
|
||||
drive-strength = <7>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
|
||||
bias-pull-down;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
|
||||
bias-pull-down;
|
||||
drive-strength = <9>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
|
||||
bias-pull-down;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
|
||||
bias-pull-down;
|
||||
drive-strength = <11>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
|
||||
bias-pull-down;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
|
||||
bias-pull-down;
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
|
||||
bias-pull-down;
|
||||
drive-strength = <14>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
|
||||
bias-pull-down;
|
||||
drive-strength = <15>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_up_smt: pcfg-pull-up-smt {
|
||||
bias-pull-up;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_down_smt: pcfg-pull-down-smt {
|
||||
bias-pull-down;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
||||
bias-disable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
|
||||
bias-disable;
|
||||
drive-strength = <0>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
};
|
11
arch/arm/include/asm/arch-rk3568/boot0.h
Normal file
11
arch/arm/include/asm/arch-rk3568/boot0.h
Normal file
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_BOOT0_H__
|
||||
#define __ASM_ARCH_BOOT0_H__
|
||||
|
||||
#include <asm/arch-rockchip/boot0.h>
|
||||
|
||||
#endif
|
11
arch/arm/include/asm/arch-rk3568/gpio.h
Normal file
11
arch/arm/include/asm/arch-rk3568/gpio.h
Normal file
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H__
|
||||
#define __ASM_ARCH_GPIO_H__
|
||||
|
||||
#include <asm/arch-rockchip/gpio.h>
|
||||
|
||||
#endif
|
504
arch/arm/include/asm/arch-rockchip/cru_rk3568.h
Normal file
504
arch/arm/include/asm/arch-rockchip/cru_rk3568.h
Normal file
|
@ -0,0 +1,504 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_CRU_RK3568_H
|
||||
#define _ASM_ARCH_CRU_RK3568_H
|
||||
|
||||
#define MHz 1000000
|
||||
#define KHz 1000
|
||||
#define OSC_HZ (24 * MHz)
|
||||
|
||||
#define APLL_HZ (816 * MHz)
|
||||
#define GPLL_HZ (1188 * MHz)
|
||||
#define CPLL_HZ (1000 * MHz)
|
||||
#define PPLL_HZ (100 * MHz)
|
||||
|
||||
/* RK3568 pll id */
|
||||
enum rk3568_pll_id {
|
||||
APLL,
|
||||
DPLL,
|
||||
CPLL,
|
||||
GPLL,
|
||||
NPLL,
|
||||
VPLL,
|
||||
PPLL,
|
||||
HPLL,
|
||||
PLL_COUNT,
|
||||
};
|
||||
|
||||
struct rk3568_clk_info {
|
||||
unsigned long id;
|
||||
char *name;
|
||||
bool is_cru;
|
||||
};
|
||||
|
||||
/* Private data for the clock driver - used by rockchip_get_cru() */
|
||||
struct rk3568_pmuclk_priv {
|
||||
struct rk3568_pmucru *pmucru;
|
||||
ulong ppll_hz;
|
||||
ulong hpll_hz;
|
||||
};
|
||||
|
||||
struct rk3568_clk_priv {
|
||||
struct rk3568_cru *cru;
|
||||
struct rk3568_grf *grf;
|
||||
ulong ppll_hz;
|
||||
ulong hpll_hz;
|
||||
ulong gpll_hz;
|
||||
ulong cpll_hz;
|
||||
ulong npll_hz;
|
||||
ulong vpll_hz;
|
||||
ulong armclk_hz;
|
||||
ulong armclk_enter_hz;
|
||||
ulong armclk_init_hz;
|
||||
bool sync_kernel;
|
||||
bool set_armclk_rate;
|
||||
};
|
||||
|
||||
struct rk3568_pll {
|
||||
unsigned int con0;
|
||||
unsigned int con1;
|
||||
unsigned int con2;
|
||||
unsigned int con3;
|
||||
unsigned int con4;
|
||||
unsigned int reserved0[3];
|
||||
};
|
||||
|
||||
struct rk3568_pmucru {
|
||||
struct rk3568_pll pll[2];/* Address Offset: 0x0000 */
|
||||
unsigned int reserved0[16];/* Address Offset: 0x0040 */
|
||||
unsigned int mode_con00;/* Address Offset: 0x0080 */
|
||||
unsigned int reserved1[31];/* Address Offset: 0x0084 */
|
||||
unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
|
||||
unsigned int reserved2[22];/* Address Offset: 0x0128 */
|
||||
unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
|
||||
unsigned int reserved3[29];/* Address Offset: 0x018C */
|
||||
unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
|
||||
};
|
||||
|
||||
check_member(rk3568_pmucru, mode_con00, 0x80);
|
||||
check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
|
||||
|
||||
struct rk3568_cru {
|
||||
struct rk3568_pll pll[6];
|
||||
unsigned int mode_con00;/* Address Offset: 0x00C0 */
|
||||
unsigned int misc_con[3];/* Address Offset: 0x00C4 */
|
||||
unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
|
||||
unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
|
||||
unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
|
||||
unsigned int glb_rst_con;/* Address Offset: 0x00DC */
|
||||
unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
|
||||
unsigned int reserved0[7];/* Address Offset: 0x00E4 */
|
||||
unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
|
||||
unsigned int reserved1[43];/* Address Offset: 0x0254 */
|
||||
unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
|
||||
unsigned int reserved2[28]; /* Address Offset: 0x0390 */
|
||||
unsigned int softrst_con[30];/* Address Offset: 0x0400 */
|
||||
unsigned int reserved3[2];/* Address Offset: 0x0478 */
|
||||
unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
|
||||
unsigned int reserved4[32];/* Address Offset: 0x0500 */
|
||||
unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
|
||||
unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
|
||||
unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
|
||||
unsigned int emmc_con[2];/* Address Offset: 0x0598 */
|
||||
};
|
||||
|
||||
check_member(rk3568_cru, mode_con00, 0xc0);
|
||||
check_member(rk3568_cru, softrst_con[0], 0x400);
|
||||
|
||||
struct pll_rate_table {
|
||||
unsigned long rate;
|
||||
unsigned int fbdiv;
|
||||
unsigned int postdiv1;
|
||||
unsigned int refdiv;
|
||||
unsigned int postdiv2;
|
||||
unsigned int dsmpd;
|
||||
unsigned int frac;
|
||||
};
|
||||
|
||||
#define RK3568_PMU_MODE 0x80
|
||||
#define RK3568_PMU_PLL_CON(x) ((x) * 0x4)
|
||||
#define RK3568_PLL_CON(x) ((x) * 0x4)
|
||||
#define RK3568_MODE_CON 0xc0
|
||||
|
||||
enum {
|
||||
/* CRU_PMU_CLK_SEL0_CON */
|
||||
RTC32K_SEL_SHIFT = 6,
|
||||
RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
|
||||
RTC32K_SEL_PMUPVTM = 0,
|
||||
RTC32K_SEL_OSC1_32K,
|
||||
RTC32K_SEL_OSC0_DIV32K,
|
||||
|
||||
/* CRU_PMU_CLK_SEL1_CON */
|
||||
RTC32K_FRAC_NUMERATOR_SHIFT = 16,
|
||||
RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
|
||||
RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
|
||||
RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
|
||||
|
||||
/* CRU_PMU_CLK_SEL2_CON */
|
||||
PCLK_PDPMU_SEL_SHIFT = 15,
|
||||
PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT,
|
||||
PCLK_PDPMU_SEL_PPLL = 0,
|
||||
PCLK_PDPMU_SEL_GPLL,
|
||||
PCLK_PDPMU_DIV_SHIFT = 0,
|
||||
PCLK_PDPMU_DIV_MASK = 0x1f,
|
||||
|
||||
/* CRU_PMU_CLK_SEL3_CON */
|
||||
CLK_I2C0_DIV_SHIFT = 0,
|
||||
CLK_I2C0_DIV_MASK = 0x7f,
|
||||
|
||||
/* CRU_PMU_CLK_SEL6_CON */
|
||||
CLK_PWM0_SEL_SHIFT = 7,
|
||||
CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
|
||||
CLK_PWM0_SEL_XIN24M = 0,
|
||||
CLK_PWM0_SEL_PPLL,
|
||||
CLK_PWM0_DIV_SHIFT = 0,
|
||||
CLK_PWM0_DIV_MASK = 0x7f,
|
||||
|
||||
/* CRU_CLK_SEL0_CON */
|
||||
CLK_CORE_PRE_SEL_SHIFT = 7,
|
||||
CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT,
|
||||
CLK_CORE_PRE_SEL_SRC = 0,
|
||||
CLK_CORE_PRE_SEL_APLL,
|
||||
|
||||
/* CRU_CLK_SEL2_CON */
|
||||
SCLK_CORE_PRE_SEL_SHIFT = 15,
|
||||
SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT,
|
||||
SCLK_CORE_PRE_SEL_SRC = 0,
|
||||
SCLK_CORE_PRE_SEL_NPLL,
|
||||
SCLK_CORE_SRC_SEL_SHIFT = 8,
|
||||
SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT,
|
||||
SCLK_CORE_SRC_SEL_APLL = 0,
|
||||
SCLK_CORE_SRC_SEL_GPLL,
|
||||
SCLK_CORE_SRC_SEL_NPLL,
|
||||
SCLK_CORE_SRC_DIV_SHIFT = 0,
|
||||
SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL3_CON */
|
||||
GICCLK_CORE_DIV_SHIFT = 8,
|
||||
GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT,
|
||||
ATCLK_CORE_DIV_SHIFT = 0,
|
||||
ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL4_CON */
|
||||
PERIPHCLK_CORE_PRE_DIV_SHIFT = 8,
|
||||
PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT,
|
||||
PCLK_CORE_PRE_DIV_SHIFT = 0,
|
||||
PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL5_CON */
|
||||
ACLK_CORE_NIU2BUS_SEL_SHIFT = 14,
|
||||
ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT,
|
||||
ACLK_CORE_NDFT_DIV_SHIFT = 8,
|
||||
ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL10_CON */
|
||||
HCLK_PERIMID_SEL_SHIFT = 6,
|
||||
HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT,
|
||||
HCLK_PERIMID_SEL_150M = 0,
|
||||
HCLK_PERIMID_SEL_100M,
|
||||
HCLK_PERIMID_SEL_75M,
|
||||
HCLK_PERIMID_SEL_24M,
|
||||
ACLK_PERIMID_SEL_SHIFT = 4,
|
||||
ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT,
|
||||
ACLK_PERIMID_SEL_300M = 0,
|
||||
ACLK_PERIMID_SEL_200M,
|
||||
ACLK_PERIMID_SEL_100M,
|
||||
ACLK_PERIMID_SEL_24M,
|
||||
|
||||
/* CRU_CLK_SEL27_CON */
|
||||
CLK_CRYPTO_PKA_SEL_SHIFT = 6,
|
||||
CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT,
|
||||
CLK_CRYPTO_PKA_SEL_300M = 0,
|
||||
CLK_CRYPTO_PKA_SEL_200M,
|
||||
CLK_CRYPTO_PKA_SEL_100M,
|
||||
CLK_CRYPTO_CORE_SEL_SHIFT = 4,
|
||||
CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT,
|
||||
CLK_CRYPTO_CORE_SEL_200M = 0,
|
||||
CLK_CRYPTO_CORE_SEL_150M,
|
||||
CLK_CRYPTO_CORE_SEL_100M,
|
||||
HCLK_SECURE_FLASH_SEL_SHIFT = 2,
|
||||
HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT,
|
||||
HCLK_SECURE_FLASH_SEL_150M = 0,
|
||||
HCLK_SECURE_FLASH_SEL_100M,
|
||||
HCLK_SECURE_FLASH_SEL_75M,
|
||||
HCLK_SECURE_FLASH_SEL_24M,
|
||||
ACLK_SECURE_FLASH_SEL_SHIFT = 0,
|
||||
ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT,
|
||||
ACLK_SECURE_FLASH_SEL_200M = 0,
|
||||
ACLK_SECURE_FLASH_SEL_150M,
|
||||
ACLK_SECURE_FLASH_SEL_100M,
|
||||
ACLK_SECURE_FLASH_SEL_24M,
|
||||
|
||||
/* CRU_CLK_SEL28_CON */
|
||||
CCLK_EMMC_SEL_SHIFT = 12,
|
||||
CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT,
|
||||
CCLK_EMMC_SEL_24M = 0,
|
||||
CCLK_EMMC_SEL_200M,
|
||||
CCLK_EMMC_SEL_150M,
|
||||
CCLK_EMMC_SEL_100M,
|
||||
CCLK_EMMC_SEL_50M,
|
||||
CCLK_EMMC_SEL_375K,
|
||||
BCLK_EMMC_SEL_SHIFT = 8,
|
||||
BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT,
|
||||
BCLK_EMMC_SEL_200M = 0,
|
||||
BCLK_EMMC_SEL_150M,
|
||||
BCLK_EMMC_SEL_125M,
|
||||
SCLK_SFC_SEL_SHIFT = 4,
|
||||
SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT,
|
||||
SCLK_SFC_SEL_24M = 0,
|
||||
SCLK_SFC_SEL_50M,
|
||||
SCLK_SFC_SEL_75M,
|
||||
SCLK_SFC_SEL_100M,
|
||||
SCLK_SFC_SEL_125M,
|
||||
SCLK_SFC_SEL_150M,
|
||||
NCLK_NANDC_SEL_SHIFT = 0,
|
||||
NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT,
|
||||
NCLK_NANDC_SEL_200M = 0,
|
||||
NCLK_NANDC_SEL_150M,
|
||||
NCLK_NANDC_SEL_100M,
|
||||
NCLK_NANDC_SEL_24M,
|
||||
|
||||
/* CRU_CLK_SEL30_CON */
|
||||
CLK_SDMMC1_SEL_SHIFT = 12,
|
||||
CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT,
|
||||
CLK_SDMMC0_SEL_SHIFT = 8,
|
||||
CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT,
|
||||
CLK_SDMMC_SEL_24M = 0,
|
||||
CLK_SDMMC_SEL_400M,
|
||||
CLK_SDMMC_SEL_300M,
|
||||
CLK_SDMMC_SEL_100M,
|
||||
CLK_SDMMC_SEL_50M,
|
||||
CLK_SDMMC_SEL_750K,
|
||||
|
||||
/* CRU_CLK_SEL31_CON */
|
||||
CLK_MAC0_OUT_SEL_SHIFT = 14,
|
||||
CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT,
|
||||
CLK_MAC0_OUT_SEL_125M = 0,
|
||||
CLK_MAC0_OUT_SEL_50M,
|
||||
CLK_MAC0_OUT_SEL_25M,
|
||||
CLK_MAC0_OUT_SEL_24M,
|
||||
CLK_GMAC0_PTP_REF_SEL_SHIFT = 12,
|
||||
CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT,
|
||||
CLK_GMAC0_PTP_REF_SEL_62_5M = 0,
|
||||
CLK_GMAC0_PTP_REF_SEL_100M,
|
||||
CLK_GMAC0_PTP_REF_SEL_50M,
|
||||
CLK_GMAC0_PTP_REF_SEL_24M,
|
||||
CLK_MAC0_2TOP_SEL_SHIFT = 8,
|
||||
CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT,
|
||||
CLK_MAC0_2TOP_SEL_125M = 0,
|
||||
CLK_MAC0_2TOP_SEL_50M,
|
||||
CLK_MAC0_2TOP_SEL_25M,
|
||||
CLK_MAC0_2TOP_SEL_PPLL,
|
||||
RGMII0_CLK_SEL_SHIFT = 4,
|
||||
RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT,
|
||||
RGMII0_CLK_SEL_125M = 0,
|
||||
RGMII0_CLK_SEL_125M_1,
|
||||
RGMII0_CLK_SEL_2_5M,
|
||||
RGMII0_CLK_SEL_25M,
|
||||
RMII0_CLK_SEL_SHIFT = 3,
|
||||
RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT,
|
||||
RMII0_CLK_SEL_2_5M = 0,
|
||||
RMII0_CLK_SEL_25M,
|
||||
RMII0_EXTCLK_SEL_SHIFT = 2,
|
||||
RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT,
|
||||
RMII0_EXTCLK_SEL_MAC0_TOP = 0,
|
||||
RMII0_EXTCLK_SEL_IO,
|
||||
RMII0_MODE_SHIFT = 0,
|
||||
RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT,
|
||||
RMII0_MODE_SEL_RGMII = 0,
|
||||
RMII0_MODE_SEL_RMII,
|
||||
RMII0_MODE_SEL_GMII,
|
||||
|
||||
/* CRU_CLK_SEL32_CON */
|
||||
CLK_SDMMC2_SEL_SHIFT = 8,
|
||||
CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL38_CON */
|
||||
ACLK_VOP_PRE_SEL_SHIFT = 6,
|
||||
ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT,
|
||||
ACLK_VOP_PRE_SEL_CPLL = 0,
|
||||
ACLK_VOP_PRE_SEL_GPLL,
|
||||
ACLK_VOP_PRE_SEL_HPLL,
|
||||
ACLK_VOP_PRE_SEL_VPLL,
|
||||
ACLK_VOP_PRE_DIV_SHIFT = 0,
|
||||
ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL39_CON */
|
||||
DCLK0_VOP_SEL_SHIFT = 10,
|
||||
DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT,
|
||||
DCLK_VOP_SEL_HPLL = 0,
|
||||
DCLK_VOP_SEL_VPLL,
|
||||
DCLK_VOP_SEL_GPLL,
|
||||
DCLK_VOP_SEL_CPLL,
|
||||
DCLK0_VOP_DIV_SHIFT = 0,
|
||||
DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL40_CON */
|
||||
DCLK1_VOP_SEL_SHIFT = 10,
|
||||
DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT,
|
||||
DCLK1_VOP_DIV_SHIFT = 0,
|
||||
DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL41_CON */
|
||||
DCLK2_VOP_SEL_SHIFT = 10,
|
||||
DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT,
|
||||
DCLK2_VOP_DIV_SHIFT = 0,
|
||||
DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL43_CON */
|
||||
DCLK_EBC_SEL_SHIFT = 6,
|
||||
DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT,
|
||||
DCLK_EBC_SEL_GPLL_400M = 0,
|
||||
DCLK_EBC_SEL_CPLL_333M,
|
||||
DCLK_EBC_SEL_GPLL_200M,
|
||||
|
||||
/* CRU_CLK_SEL47_CON */
|
||||
ACLK_RKVDEC_SEL_SHIFT = 7,
|
||||
ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT,
|
||||
ACLK_RKVDEC_SEL_GPLL = 0,
|
||||
ACLK_RKVDEC_SEL_CPLL,
|
||||
ACLK_RKVDEC_DIV_SHIFT = 0,
|
||||
ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL49_CON */
|
||||
CLK_RKVDEC_CORE_SEL_SHIFT = 14,
|
||||
CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT,
|
||||
CLK_RKVDEC_CORE_SEL_GPLL = 0,
|
||||
CLK_RKVDEC_CORE_SEL_CPLL,
|
||||
CLK_RKVDEC_CORE_SEL_NPLL,
|
||||
CLK_RKVDEC_CORE_SEL_VPLL,
|
||||
CLK_RKVDEC_CORE_DIV_SHIFT = 8,
|
||||
CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL50_CON */
|
||||
PCLK_BUS_SEL_SHIFT = 4,
|
||||
PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT,
|
||||
PCLK_BUS_SEL_100M = 0,
|
||||
PCLK_BUS_SEL_75M,
|
||||
PCLK_BUS_SEL_50M,
|
||||
PCLK_BUS_SEL_24M,
|
||||
ACLK_BUS_SEL_SHIFT = 0,
|
||||
ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT,
|
||||
ACLK_BUS_SEL_200M = 0,
|
||||
ACLK_BUS_SEL_150M,
|
||||
ACLK_BUS_SEL_100M,
|
||||
ACLK_BUS_SEL_24M,
|
||||
|
||||
/* CRU_CLK_SEL51_CON */
|
||||
CLK_TSADC_DIV_SHIFT = 8,
|
||||
CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT,
|
||||
CLK_TSADC_TSEN_SEL_SHIFT = 4,
|
||||
CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT,
|
||||
CLK_TSADC_TSEN_SEL_24M = 0,
|
||||
CLK_TSADC_TSEN_SEL_100M,
|
||||
CLK_TSADC_TSEN_SEL_CPLL_100M,
|
||||
CLK_TSADC_TSEN_DIV_SHIFT = 0,
|
||||
CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL52_CON */
|
||||
CLK_UART_SEL_SHIFT = 12,
|
||||
CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
|
||||
CLK_UART_SEL_SRC = 0,
|
||||
CLK_UART_SEL_FRAC,
|
||||
CLK_UART_SEL_XIN24M,
|
||||
CLK_UART_SRC_SEL_SHIFT = 8,
|
||||
CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT,
|
||||
CLK_UART_SRC_SEL_GPLL = 0,
|
||||
CLK_UART_SRC_SEL_CPLL,
|
||||
CLK_UART_SRC_SEL_480M,
|
||||
CLK_UART_SRC_DIV_SHIFT = 0,
|
||||
CLK_UART_SRC_DIV_MASK = 0x3f << CLK_UART_SRC_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL53_CON */
|
||||
CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
|
||||
CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
|
||||
CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
|
||||
CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
|
||||
|
||||
/* CRU_CLK_SEL71_CON */
|
||||
CLK_I2C_SEL_SHIFT = 8,
|
||||
CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT,
|
||||
CLK_I2C_SEL_200M = 0,
|
||||
CLK_I2C_SEL_100M,
|
||||
CLK_I2C_SEL_24M,
|
||||
CLK_I2C_SEL_CPLL_100M,
|
||||
|
||||
/* CRU_CLK_SEL72_CON */
|
||||
CLK_PWM3_SEL_SHIFT = 12,
|
||||
CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT,
|
||||
CLK_PWM2_SEL_SHIFT = 10,
|
||||
CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
|
||||
CLK_PWM1_SEL_SHIFT = 8,
|
||||
CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
|
||||
CLK_PWM_SEL_100M = 0,
|
||||
CLK_PWM_SEL_24M,
|
||||
CLK_PWM_SEL_CPLL_100M,
|
||||
CLK_SPI3_SEL_SHIFT = 6,
|
||||
CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
|
||||
CLK_SPI2_SEL_SHIFT = 4,
|
||||
CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
|
||||
CLK_SPI1_SEL_SHIFT = 2,
|
||||
CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
|
||||
CLK_SPI0_SEL_SHIFT = 0,
|
||||
CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
|
||||
CLK_SPI_SEL_200M = 0,
|
||||
CLK_SPI_SEL_24M,
|
||||
CLK_SPI_SEL_CPLL_100M,
|
||||
|
||||
/* CRU_CLK_SEL73_CON */
|
||||
PCLK_TOP_SEL_SHIFT = 12,
|
||||
PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT,
|
||||
PCLK_TOP_SEL_100M = 0,
|
||||
PCLK_TOP_SEL_75M,
|
||||
PCLK_TOP_SEL_50M,
|
||||
PCLK_TOP_SEL_24M,
|
||||
HCLK_TOP_SEL_SHIFT = 8,
|
||||
HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT,
|
||||
HCLK_TOP_SEL_150M = 0,
|
||||
HCLK_TOP_SEL_100M,
|
||||
HCLK_TOP_SEL_75M,
|
||||
HCLK_TOP_SEL_24M,
|
||||
ACLK_TOP_LOW_SEL_SHIFT = 4,
|
||||
ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT,
|
||||
ACLK_TOP_LOW_SEL_400M = 0,
|
||||
ACLK_TOP_LOW_SEL_300M,
|
||||
ACLK_TOP_LOW_SEL_200M,
|
||||
ACLK_TOP_LOW_SEL_24M,
|
||||
ACLK_TOP_HIGH_SEL_SHIFT = 0,
|
||||
ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT,
|
||||
ACLK_TOP_HIGH_SEL_500M = 0,
|
||||
ACLK_TOP_HIGH_SEL_400M,
|
||||
ACLK_TOP_HIGH_SEL_300M,
|
||||
ACLK_TOP_HIGH_SEL_24M,
|
||||
|
||||
/* CRU_CLK_SEL78_CON */
|
||||
CPLL_500M_DIV_SHIFT = 8,
|
||||
CPLL_500M_DIV_MASK = 0x1f << CPLL_500M_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL79_CON */
|
||||
CPLL_250M_DIV_SHIFT = 8,
|
||||
CPLL_250M_DIV_MASK = 0x1f << CPLL_250M_DIV_SHIFT,
|
||||
CPLL_333M_DIV_SHIFT = 0,
|
||||
CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL80_CON */
|
||||
CPLL_62P5M_DIV_SHIFT = 8,
|
||||
CPLL_62P5M_DIV_MASK = 0x1f << CPLL_62P5M_DIV_SHIFT,
|
||||
CPLL_125M_DIV_SHIFT = 0,
|
||||
CPLL_125M_DIV_MASK = 0x1f << CPLL_125M_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL81_CON */
|
||||
CPLL_25M_DIV_SHIFT = 8,
|
||||
CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT,
|
||||
CPLL_50M_DIV_SHIFT = 0,
|
||||
CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,
|
||||
|
||||
/* CRU_CLK_SEL82_CON */
|
||||
CPLL_100M_DIV_SHIFT = 0,
|
||||
CPLL_100M_DIV_MASK = 0x1f << CPLL_100M_DIV_SHIFT,
|
||||
};
|
||||
#endif
|
369
arch/arm/include/asm/arch-rockchip/grf_rk3568.h
Normal file
369
arch/arm/include/asm/arch-rockchip/grf_rk3568.h
Normal file
|
@ -0,0 +1,369 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __SOC_ROCKCHIP_RK3568_GRF_H__
|
||||
#define __SOC_ROCKCHIP_RK3568_GRF_H__
|
||||
|
||||
struct rk3568_grf {
|
||||
unsigned int gpio1a_iomux_l;
|
||||
unsigned int gpio1a_iomux_h;
|
||||
unsigned int gpio1b_iomux_l;
|
||||
unsigned int gpio1b_iomux_h;
|
||||
unsigned int gpio1c_iomux_l;
|
||||
unsigned int gpio1c_iomux_h;
|
||||
unsigned int gpio1d_iomux_l;
|
||||
unsigned int gpio1d_iomux_h;
|
||||
unsigned int gpio2a_iomux_l;
|
||||
unsigned int gpio2a_iomux_h;
|
||||
unsigned int gpio2b_iomux_l;
|
||||
unsigned int gpio2b_iomux_h;
|
||||
unsigned int gpio2c_iomux_l;
|
||||
unsigned int gpio2c_iomux_h;
|
||||
unsigned int gpio2d_iomux_l;
|
||||
unsigned int gpio2d_iomux_h;
|
||||
unsigned int gpio3a_iomux_l;
|
||||
unsigned int gpio3a_iomux_h;
|
||||
unsigned int gpio3b_iomux_l;
|
||||
unsigned int gpio3b_iomux_h;
|
||||
unsigned int gpio3c_iomux_l;
|
||||
unsigned int gpio3c_iomux_h;
|
||||
unsigned int gpio3d_iomux_l;
|
||||
unsigned int gpio3d_iomux_h;
|
||||
unsigned int gpio4a_iomux_l;
|
||||
unsigned int gpio4a_iomux_h;
|
||||
unsigned int gpio4b_iomux_l;
|
||||
unsigned int gpio4b_iomux_h;
|
||||
unsigned int gpio4c_iomux_l;
|
||||
unsigned int gpio4c_iomux_h;
|
||||
unsigned int gpio4d_iomux_l;
|
||||
unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1];
|
||||
unsigned int gpio1a_p;
|
||||
unsigned int gpio1b_p;
|
||||
unsigned int gpio1c_p;
|
||||
unsigned int gpio1d_p;
|
||||
unsigned int gpio2a_p;
|
||||
unsigned int gpio2b_p;
|
||||
unsigned int gpio2c_p;
|
||||
unsigned int gpio2d_p;
|
||||
unsigned int gpio3a_p;
|
||||
unsigned int gpio3b_p;
|
||||
unsigned int gpio3c_p;
|
||||
unsigned int gpio3d_p;
|
||||
unsigned int gpio4a_p;
|
||||
unsigned int gpio4b_p;
|
||||
unsigned int gpio4c_p;
|
||||
unsigned int gpio4d_p;
|
||||
unsigned int gpio1a_ie;
|
||||
unsigned int gpio1b_ie;
|
||||
unsigned int gpio1c_ie;
|
||||
unsigned int gpio1d_ie;
|
||||
unsigned int gpio2a_ie;
|
||||
unsigned int gpio2b_ie;
|
||||
unsigned int gpio2c_ie;
|
||||
unsigned int gpio2d_ie;
|
||||
unsigned int gpio3a_ie;
|
||||
unsigned int gpio3b_ie;
|
||||
unsigned int gpio3c_ie;
|
||||
unsigned int gpio3d_ie;
|
||||
unsigned int gpio4a_ie;
|
||||
unsigned int gpio4b_ie;
|
||||
unsigned int gpio4c_ie;
|
||||
unsigned int gpio4d_ie;
|
||||
unsigned int gpio1a_opd;
|
||||
unsigned int gpio1b_opd;
|
||||
unsigned int gpio1c_opd;
|
||||
unsigned int gpio1d_opd;
|
||||
unsigned int gpio2a_opd;
|
||||
unsigned int gpio2b_opd;
|
||||
unsigned int gpio2c_opd;
|
||||
unsigned int gpio2d_opd;
|
||||
unsigned int gpio3a_opd;
|
||||
unsigned int gpio3b_opd;
|
||||
unsigned int gpio3c_opd;
|
||||
unsigned int gpio3d_opd;
|
||||
unsigned int gpio4a_opd;
|
||||
unsigned int gpio4b_opd;
|
||||
unsigned int gpio4c_opd;
|
||||
unsigned int gpio4d_opd;
|
||||
unsigned int gpio1a_sus;
|
||||
unsigned int gpio1b_sus;
|
||||
unsigned int gpio1c_sus;
|
||||
unsigned int gpio1d_sus;
|
||||
unsigned int gpio2a_sus;
|
||||
unsigned int gpio2b_sus;
|
||||
unsigned int gpio2c_sus;
|
||||
unsigned int gpio2d_sus;
|
||||
unsigned int gpio3a_sus;
|
||||
unsigned int gpio3b_sus;
|
||||
unsigned int gpio3c_sus;
|
||||
unsigned int gpio3d_sus;
|
||||
unsigned int gpio4a_sus;
|
||||
unsigned int gpio4b_sus;
|
||||
unsigned int gpio4c_sus;
|
||||
unsigned int gpio4d_sus;
|
||||
unsigned int gpio1a_sl;
|
||||
unsigned int gpio1b_sl;
|
||||
unsigned int gpio1c_sl;
|
||||
unsigned int gpio1d_sl;
|
||||
unsigned int gpio2a_sl;
|
||||
unsigned int gpio2b_sl;
|
||||
unsigned int gpio2c_sl;
|
||||
unsigned int gpio2d_sl;
|
||||
unsigned int gpio3a_sl;
|
||||
unsigned int gpio3b_sl;
|
||||
unsigned int gpio3c_sl;
|
||||
unsigned int gpio3d_sl;
|
||||
unsigned int gpio4a_sl;
|
||||
unsigned int gpio4b_sl;
|
||||
unsigned int gpio4c_sl;
|
||||
unsigned int gpio4d_sl;
|
||||
unsigned int reserved1[(0x0200 - 0x01bc) / 4 - 1];
|
||||
unsigned int gpio1a_ds_0;
|
||||
unsigned int gpio1a_ds_1;
|
||||
unsigned int gpio1a_ds_2;
|
||||
unsigned int gpio1a_ds_3;
|
||||
unsigned int gpio1b_ds_0;
|
||||
unsigned int gpio1b_ds_1;
|
||||
unsigned int gpio1b_ds_2;
|
||||
unsigned int gpio1b_ds_3;
|
||||
unsigned int gpio1c_ds_0;
|
||||
unsigned int gpio1c_ds_1;
|
||||
unsigned int gpio1c_ds_2;
|
||||
unsigned int gpio1c_ds_3;
|
||||
unsigned int gpio1d_ds_0;
|
||||
unsigned int gpio1d_ds_1;
|
||||
unsigned int gpio1d_ds_2;
|
||||
unsigned int gpio1d_ds_3;
|
||||
unsigned int gpio2a_ds_0;
|
||||
unsigned int gpio2a_ds_1;
|
||||
unsigned int gpio2a_ds_2;
|
||||
unsigned int gpio2a_ds_3;
|
||||
unsigned int gpio2b_ds_0;
|
||||
unsigned int gpio2b_ds_1;
|
||||
unsigned int gpio2b_ds_2;
|
||||
unsigned int gpio2b_ds_3;
|
||||
unsigned int gpio2c_ds_0;
|
||||
unsigned int gpio2c_ds_1;
|
||||
unsigned int gpio2c_ds_2;
|
||||
unsigned int gpio2c_ds_3;
|
||||
unsigned int gpio2d_ds_0;
|
||||
unsigned int gpio2d_ds_1;
|
||||
unsigned int gpio2d_ds_2;
|
||||
unsigned int gpio2d_ds_3;
|
||||
unsigned int gpio3a_ds_0;
|
||||
unsigned int gpio3a_ds_1;
|
||||
unsigned int gpio3a_ds_2;
|
||||
unsigned int gpio3a_ds_3;
|
||||
unsigned int gpio3b_ds_0;
|
||||
unsigned int gpio3b_ds_1;
|
||||
unsigned int gpio3b_ds_2;
|
||||
unsigned int gpio3b_ds_3;
|
||||
unsigned int gpio3c_ds_0;
|
||||
unsigned int gpio3c_ds_1;
|
||||
unsigned int gpio3c_ds_2;
|
||||
unsigned int gpio3c_ds_3;
|
||||
unsigned int gpio3d_ds_0;
|
||||
unsigned int gpio3d_ds_1;
|
||||
unsigned int gpio3d_ds_2;
|
||||
unsigned int gpio3d_ds_3;
|
||||
unsigned int gpio4a_ds_0;
|
||||
unsigned int gpio4a_ds_1;
|
||||
unsigned int gpio4a_ds_2;
|
||||
unsigned int gpio4a_ds_3;
|
||||
unsigned int gpio4b_ds_0;
|
||||
unsigned int gpio4b_ds_1;
|
||||
unsigned int gpio4b_ds_2;
|
||||
unsigned int gpio4b_ds_3;
|
||||
unsigned int gpio4c_ds_0;
|
||||
unsigned int gpio4c_ds_1;
|
||||
unsigned int gpio4c_ds_2;
|
||||
unsigned int gpio4c_ds_3;
|
||||
unsigned int gpio4d_ds_0;
|
||||
unsigned int gpio4d_ds_1;
|
||||
unsigned int gpio4d_ds_2;
|
||||
unsigned int gpio4d_ds_3;
|
||||
unsigned int iofunc_sel0;
|
||||
unsigned int iofunc_sel1;
|
||||
unsigned int iofunc_sel2;
|
||||
unsigned int iofunc_sel3;
|
||||
unsigned int iofunc_sel4;
|
||||
unsigned int iofunc_sel5;
|
||||
unsigned int reserved2[(0x0340 - 0x0314) / 4 - 1];
|
||||
unsigned int vi_con0;
|
||||
unsigned int vi_con1;
|
||||
unsigned int vi_status0;
|
||||
unsigned int reserved3[(0x0360 - 0x0348) / 4 - 1];
|
||||
unsigned int vo_con0;
|
||||
unsigned int vo_con1;
|
||||
unsigned int vo_con2;
|
||||
unsigned int vo_con3;
|
||||
unsigned int reserved4[(0x0380 - 0x036c) / 4 - 1];
|
||||
unsigned int mac0_con0;
|
||||
unsigned int mac0_con1;
|
||||
unsigned int mac1_con0;
|
||||
unsigned int mac1_con1;
|
||||
unsigned int reserved5[(0x03a0 - 0x038c) / 4 - 1];
|
||||
unsigned int biu_con0;
|
||||
unsigned int biu_con1;
|
||||
unsigned int biu_con2;
|
||||
unsigned int reserved6[(0x03c0 - 0x03a8) / 4 - 1];
|
||||
unsigned int gic_con0;
|
||||
unsigned int gic_con1;
|
||||
unsigned int gic_con2;
|
||||
unsigned int reserved7[(0x03f0 - 0x03c8) / 4 - 1];
|
||||
unsigned int gpu_con0;
|
||||
unsigned int gpu_con1;
|
||||
unsigned int reserved8[(0x0400 - 0x03f4) / 4 - 1];
|
||||
unsigned int cpu_con0;
|
||||
unsigned int reserved9[(0x0420 - 0x0400) / 4 - 1];
|
||||
unsigned int cpu_status0;
|
||||
unsigned int reserved10[(0x0500 - 0x0420) / 4 - 1];
|
||||
unsigned int soc_con0;
|
||||
unsigned int soc_con1;
|
||||
unsigned int soc_con2;
|
||||
unsigned int soc_con3;
|
||||
unsigned int reserved11[(0x0514 - 0x050c) / 4 - 1];
|
||||
unsigned int soc_con5;
|
||||
unsigned int soc_con6;
|
||||
unsigned int reserved12[(0x0580 - 0x0518) / 4 - 1];
|
||||
unsigned int soc_status0;
|
||||
unsigned int reserved13[(0x05c0 - 0x0580) / 4 - 1];
|
||||
unsigned int ram_con;
|
||||
unsigned int core_ram_con;
|
||||
unsigned int reserved14[(0x0600 - 0x05c4) / 4 - 1];
|
||||
unsigned int tsadc_con;
|
||||
unsigned int reserved15[(0x0610 - 0x0600) / 4 - 1];
|
||||
unsigned int saradc_con;
|
||||
unsigned int reserved16[(0x0700 - 0x0610) / 4 - 1];
|
||||
unsigned int gpupvtpll_con0;
|
||||
unsigned int gpupvtpll_con1;
|
||||
unsigned int gpupvtpll_con2;
|
||||
unsigned int gpupvtpll_con3;
|
||||
unsigned int reserved17[(0x0740 - 0x070c) / 4 - 1];
|
||||
unsigned int npupvtpll_con0;
|
||||
unsigned int npupvtpll_con1;
|
||||
unsigned int npupvtpll_con2;
|
||||
unsigned int npupvtpll_con3;
|
||||
unsigned int reserved18[(0x0800 - 0x074c) / 4 - 1];
|
||||
unsigned int chip_id;
|
||||
unsigned int reserved19[(0x0840 - 0x0800) / 4 - 1];
|
||||
unsigned int gpio1c5_ds;
|
||||
unsigned int gpio2a2_ds;
|
||||
unsigned int gpio2b0_ds;
|
||||
unsigned int gpio3a0_ds;
|
||||
unsigned int gpio3a6_ds;
|
||||
unsigned int gpio4a0_ds;
|
||||
unsigned int reserved20[(0x0900 - 0x0854) / 4 - 1];
|
||||
unsigned int dmac0_con0;
|
||||
unsigned int dmac0_con1;
|
||||
unsigned int dmac0_con2;
|
||||
unsigned int dmac0_con3;
|
||||
unsigned int dmac0_con4;
|
||||
unsigned int dmac0_con5;
|
||||
unsigned int dmac0_con6;
|
||||
unsigned int dmac0_con7;
|
||||
unsigned int dmac0_con8;
|
||||
unsigned int dmac0_con9;
|
||||
unsigned int reserved21[(0x0940 - 0x0924) / 4 - 1];
|
||||
unsigned int dmac1_con0;
|
||||
unsigned int dmac1_con1;
|
||||
unsigned int dmac1_con2;
|
||||
unsigned int dmac1_con3;
|
||||
unsigned int dmac1_con4;
|
||||
unsigned int dmac1_con5;
|
||||
unsigned int dmac1_con6;
|
||||
unsigned int dmac1_con7;
|
||||
unsigned int dmac1_con8;
|
||||
unsigned int dmac1_con9;
|
||||
};
|
||||
|
||||
check_member(rk3568_grf, dmac1_con9, 0x0964);
|
||||
|
||||
struct rk3568_pmugrf {
|
||||
unsigned int pmu_gpio0a_iomux_l;
|
||||
unsigned int pmu_gpio0a_iomux_h;
|
||||
unsigned int pmu_gpio0b_iomux_l;
|
||||
unsigned int pmu_gpio0b_iomux_h;
|
||||
unsigned int pmu_gpio0c_iomux_l;
|
||||
unsigned int pmu_gpio0c_iomux_h;
|
||||
unsigned int pmu_gpio0d_iomux_l;
|
||||
unsigned int reserved0[(0x0020 - 0x0018) / 4 - 1];
|
||||
unsigned int pmu_gpio0a_p;
|
||||
unsigned int pmu_gpio0b_p;
|
||||
unsigned int pmu_gpio0c_p;
|
||||
unsigned int pmu_gpio0d_p;
|
||||
unsigned int pmu_gpio0a_ie;
|
||||
unsigned int pmu_gpio0b_ie;
|
||||
unsigned int pmu_gpio0c_ie;
|
||||
unsigned int pmu_gpio0d_ie;
|
||||
unsigned int pmu_gpio0a_opd;
|
||||
unsigned int pmu_gpio0b_opd;
|
||||
unsigned int pmu_gpio0c_opd;
|
||||
unsigned int pmu_gpio0d_opd;
|
||||
unsigned int pmu_gpio0a_sus;
|
||||
unsigned int pmu_gpio0b_sus;
|
||||
unsigned int pmu_gpio0c_sus;
|
||||
unsigned int pmu_gpio0d_sus;
|
||||
unsigned int pmu_gpio0a_sl;
|
||||
unsigned int pmu_gpio0b_sl;
|
||||
unsigned int pmu_gpio0c_sl;
|
||||
unsigned int pmu_gpio0d_sl;
|
||||
unsigned int pmu_gpio0a_ds_0;
|
||||
unsigned int pmu_gpio0a_ds_1;
|
||||
unsigned int pmu_gpio0a_ds_2;
|
||||
unsigned int pmu_gpio0a_ds_3;
|
||||
unsigned int pmu_gpio0b_ds_0;
|
||||
unsigned int pmu_gpio0b_ds_1;
|
||||
unsigned int pmu_gpio0b_ds_2;
|
||||
unsigned int pmu_gpio0b_ds_3;
|
||||
unsigned int pmu_gpio0c_ds_0;
|
||||
unsigned int pmu_gpio0c_ds_1;
|
||||
unsigned int pmu_gpio0c_ds_2;
|
||||
unsigned int pmu_gpio0c_ds_3;
|
||||
unsigned int pmu_gpio0d_ds_0;
|
||||
unsigned int pmu_gpio0d_ds_1;
|
||||
unsigned int pmu_gpio0d_ds_2;
|
||||
unsigned int pmu_gpio0d_ds_3;
|
||||
unsigned int reserved1[(0x0100 - 0x00ac) / 4 - 1];
|
||||
unsigned int pmu_soc_con0;
|
||||
unsigned int pmu_soc_con1;
|
||||
unsigned int pmu_soc_con2;
|
||||
unsigned int pmu_soc_con3;
|
||||
unsigned int pmu_soc_con4;
|
||||
unsigned int pmu_soc_con5;
|
||||
unsigned int reserved2[(0x0124 - 0x0114) / 4 - 1];
|
||||
unsigned int pmu_io_vsel0;
|
||||
unsigned int pmu_io_vsel1;
|
||||
unsigned int pmu_io_vsel2;
|
||||
unsigned int reserved3[(0x0180 - 0x012c) / 4 - 1];
|
||||
unsigned int pmu_dll_con0;
|
||||
unsigned int reserved4[(0x0200 - 0x0180) / 4 - 1];
|
||||
unsigned int pmu_os_reg0;
|
||||
unsigned int pmu_os_reg1;
|
||||
unsigned int pmu_os_reg2;
|
||||
unsigned int pmu_os_reg3;
|
||||
unsigned int pmu_os_reg4;
|
||||
unsigned int pmu_os_reg5;
|
||||
unsigned int pmu_os_reg6;
|
||||
unsigned int pmu_os_reg7;
|
||||
unsigned int pmu_os_reg8;
|
||||
unsigned int pmu_os_reg9;
|
||||
unsigned int pmu_os_reg10;
|
||||
unsigned int pmu_os_reg11;
|
||||
unsigned int pmu_reset_function_status;
|
||||
unsigned int pmu_reset_function_clr;
|
||||
unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
|
||||
unsigned int pmu_sig_detect_con;
|
||||
unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
|
||||
unsigned int pmu_sig_detect_status;
|
||||
unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
|
||||
unsigned int pmu_sig_detect_status_clear;
|
||||
unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
|
||||
unsigned int pmu_sdmmc_det_counter;
|
||||
};
|
||||
|
||||
check_member(rk3568_pmugrf, pmu_sdmmc_det_counter, 0x03b0);
|
||||
|
||||
#endif
|
|
@ -257,6 +257,23 @@ config ROCKCHIP_RK3399
|
|||
and video codec support. Peripherals include Gigabit Ethernet,
|
||||
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
||||
|
||||
config ROCKCHIP_RK3568
|
||||
bool "Support Rockchip RK3568"
|
||||
select ARM64
|
||||
select CLK
|
||||
select PINCTRL
|
||||
select RAM
|
||||
select REGMAP
|
||||
select SYSCON
|
||||
select BOARD_LATE_INIT
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
help
|
||||
The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
|
||||
including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
|
||||
two video interfaces supporting HDMI and eDP, several DDR3 options
|
||||
and video codec support. Peripherals include Gigabit Ethernet,
|
||||
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
||||
|
||||
config ROCKCHIP_RV1108
|
||||
bool "Support Rockchip RV1108"
|
||||
select CPU_V7A
|
||||
|
@ -386,5 +403,6 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
|
|||
source "arch/arm/mach-rockchip/rk3328/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3368/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3399/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rk3568/Kconfig"
|
||||
source "arch/arm/mach-rockchip/rv1108/Kconfig"
|
||||
endif
|
||||
|
|
|
@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
|
|||
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
|
||||
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
|
||||
|
||||
# Clear out SPL objects, in case this is a TPL build
|
||||
|
|
20
arch/arm/mach-rockchip/rk3568/Kconfig
Normal file
20
arch/arm/mach-rockchip/rk3568/Kconfig
Normal file
|
@ -0,0 +1,20 @@
|
|||
if ROCKCHIP_RK3568
|
||||
|
||||
config TARGET_EVB_RK3568
|
||||
bool "RK3568 evaluation board"
|
||||
select BOARD_LATE_INIT
|
||||
help
|
||||
RK3568 EVB is a evaluation board for Rockchp RK3568.
|
||||
|
||||
config ROCKCHIP_BOOT_MODE_REG
|
||||
default 0xfdc20200
|
||||
|
||||
config SYS_SOC
|
||||
default "rk3568"
|
||||
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x2000
|
||||
|
||||
source "board/rockchip/evb_rk3568/Kconfig"
|
||||
|
||||
endif
|
9
arch/arm/mach-rockchip/rk3568/Makefile
Normal file
9
arch/arm/mach-rockchip/rk3568/Makefile
Normal file
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += clk_rk3568.o
|
||||
obj-y += rk3568.o
|
||||
obj-y += syscon_rk3568.o
|
53
arch/arm/mach-rockchip/rk3568/clk_rk3568.c
Normal file
53
arch/arm/mach-rockchip/rk3568/clk_rk3568.c
Normal file
|
@ -0,0 +1,53 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <asm/arch-rockchip/cru_rk3568.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
int rockchip_get_clk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(rockchip_rk3568_cru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_cru(void)
|
||||
{
|
||||
struct rk3568_clk_priv *priv;
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = rockchip_get_clk(&dev);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
priv = dev_get_priv(dev);
|
||||
|
||||
return priv->cru;
|
||||
}
|
||||
|
||||
static int rockchip_get_pmucruclk(struct udevice **devp)
|
||||
{
|
||||
return uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(rockchip_rk3568_pmucru), devp);
|
||||
}
|
||||
|
||||
void *rockchip_get_pmucru(void)
|
||||
{
|
||||
struct rk3568_pmuclk_priv *priv;
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = rockchip_get_pmucruclk(&dev);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
priv = dev_get_priv(dev);
|
||||
|
||||
return priv->pmucru;
|
||||
}
|
85
arch/arm/mach-rockchip/rk3568/rk3568.c
Normal file
85
arch/arm/mach-rockchip/rk3568/rk3568.c
Normal file
|
@ -0,0 +1,85 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/armv8/mmu.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch-rockchip/grf_rk3568.h>
|
||||
#include <asm/arch-rockchip/hardware.h>
|
||||
#include <dt-bindings/clock/rk3568-cru.h>
|
||||
|
||||
#define PMUGRF_BASE 0xfdc20000
|
||||
#define GRF_BASE 0xfdc60000
|
||||
|
||||
/* PMU_GRF_GPIO0D_IOMUX_L */
|
||||
enum {
|
||||
GPIO0D1_SHIFT = 4,
|
||||
GPIO0D1_MASK = GENMASK(6, 4),
|
||||
GPIO0D1_GPIO = 0,
|
||||
GPIO0D1_UART2_TXM0,
|
||||
|
||||
GPIO0D0_SHIFT = 0,
|
||||
GPIO0D0_MASK = GENMASK(2, 0),
|
||||
GPIO0D0_GPIO = 0,
|
||||
GPIO0D0_UART2_RXM0,
|
||||
};
|
||||
|
||||
/* GRF_IOFUNC_SEL3 */
|
||||
enum {
|
||||
UART2_IO_SEL_SHIFT = 10,
|
||||
UART2_IO_SEL_MASK = GENMASK(11, 10),
|
||||
UART2_IO_SEL_M0 = 0,
|
||||
};
|
||||
|
||||
static struct mm_region rk3568_mem_map[] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0xf0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xf0000000UL,
|
||||
.phys = 0xf0000000UL,
|
||||
.size = 0x10000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
.virt = 0x300000000,
|
||||
.phys = 0x300000000,
|
||||
.size = 0x0c0c00000,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = rk3568_mem_map;
|
||||
|
||||
void board_debug_uart_init(void)
|
||||
{
|
||||
static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
|
||||
static struct rk3568_grf * const grf = (void *)GRF_BASE;
|
||||
|
||||
/* UART2 M0 */
|
||||
rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
|
||||
UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
|
||||
|
||||
/* Switch iomux */
|
||||
rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
|
||||
GPIO0D1_MASK | GPIO0D0_MASK,
|
||||
GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
|
||||
GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
24
arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
Normal file
24
arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
Normal file
|
@ -0,0 +1,24 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
|
||||
static const struct udevice_id rk3568_syscon_ids[] = {
|
||||
{ .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF },
|
||||
{ .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(syscon_rk3568) = {
|
||||
.name = "rk3568_syscon",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = rk3568_syscon_ids,
|
||||
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.bind = dm_scan_fdt_dev,
|
||||
#endif
|
||||
};
|
15
board/rockchip/evb_rk3568/Kconfig
Normal file
15
board/rockchip/evb_rk3568/Kconfig
Normal file
|
@ -0,0 +1,15 @@
|
|||
if TARGET_EVB_RK3568
|
||||
|
||||
config SYS_BOARD
|
||||
default "evb_rk3568"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "rockchip"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "evb_rk3568"
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
|
||||
endif
|
6
board/rockchip/evb_rk3568/MAINTAINERS
Normal file
6
board/rockchip/evb_rk3568/MAINTAINERS
Normal file
|
@ -0,0 +1,6 @@
|
|||
EVB-RK3568
|
||||
M: Joseph Chen <chenjh@rock-chips.com>
|
||||
S: Maintained
|
||||
F: board/rockchip/evb_rk3568
|
||||
F: include/configs/evb_rk3568.h
|
||||
F: configs/evb-rk3568_defconfig
|
7
board/rockchip/evb_rk3568/Makefile
Normal file
7
board/rockchip/evb_rk3568/Makefile
Normal file
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += evb_rk3568.o
|
4
board/rockchip/evb_rk3568/evb_rk3568.c
Normal file
4
board/rockchip/evb_rk3568/evb_rk3568.c
Normal file
|
@ -0,0 +1,4 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
35
configs/evb-rk3568_defconfig
Normal file
35
configs/evb-rk3568_defconfig
Normal file
|
@ -0,0 +1,35 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_TARGET_EVB_RK3568=y
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_ERRNO_STR=y
|
|
@ -50,6 +50,8 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
|
|
|
@ -49,6 +49,8 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
|
|
|
@ -50,6 +50,8 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
|
|
|
@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
|
|||
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
|
||||
|
|
2959
drivers/clk/rockchip/clk_rk3568.c
Normal file
2959
drivers/clk/rockchip/clk_rk3568.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -333,6 +333,22 @@ config CORTINA_NAND
|
|||
The controller supports a maximum 8k page size and supports
|
||||
a maximum 40-bit error correction per sector of 1024 bytes.
|
||||
|
||||
config ROCKCHIP_NAND
|
||||
bool "Support for NAND controller on Rockchip SoCs"
|
||||
depends on ARCH_ROCKCHIP
|
||||
select SYS_NAND_SELF_INIT
|
||||
select DM_MTD
|
||||
imply CMD_NAND
|
||||
help
|
||||
Enables support for NAND Flash chips on Rockchip SoCs platform.
|
||||
This controller is found on Rockchip SoCs.
|
||||
There are four different versions of NAND FLASH Controllers,
|
||||
including:
|
||||
NFC v600: RK2928, RK3066, RK3188
|
||||
NFC v622: RK3036, RK3128
|
||||
NFC v800: RK3308, RV1108
|
||||
NFC v900: PX30, RK3326
|
||||
|
||||
comment "Generic NAND options"
|
||||
|
||||
config SYS_NAND_BLOCK_SIZE
|
||||
|
|
|
@ -70,6 +70,7 @@ obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
|
|||
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
|
||||
obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
|
||||
obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
|
||||
obj-$(CONFIG_ROCKCHIP_NAND) += rockchip_nfc.o
|
||||
|
||||
else # minimal SPL drivers
|
||||
|
||||
|
|
1253
drivers/mtd/nand/raw/rockchip_nfc.c
Normal file
1253
drivers/mtd/nand/raw/rockchip_nfc.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -61,13 +61,13 @@ struct rk_pcie {
|
|||
#define PCIE_CLIENT_DBF_EN 0xffff0003
|
||||
|
||||
/* Parameters for the waiting for #perst signal */
|
||||
#define PERST_WAIT_MS 1000
|
||||
#define MACRO_US 1000
|
||||
|
||||
static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
|
||||
{
|
||||
if ((uintptr_t)addr & (size - 1)) {
|
||||
*val = 0;
|
||||
return PCIBIOS_UNSUPPORTED;
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (size == 4) {
|
||||
|
@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
|
|||
static int rk_pcie_write(void __iomem *addr, int size, u32 val)
|
||||
{
|
||||
if ((uintptr_t)addr & (size - 1))
|
||||
return PCIBIOS_UNSUPPORTED;
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (size == 4)
|
||||
writel(val, addr);
|
||||
|
@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
|
|||
*/
|
||||
static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
dw_pcie_dbi_write_enable(&pci->dw, true);
|
||||
|
||||
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
|
||||
|
@ -251,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
|
|||
* some wired devices need much more, such as 600ms.
|
||||
* Add a enough delay to cover all cases.
|
||||
*/
|
||||
msleep(PERST_WAIT_MS);
|
||||
udelay(MACRO_US * 1000);
|
||||
dm_gpio_set_value(&priv->rst_gpio, 1);
|
||||
}
|
||||
|
||||
|
@ -273,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
|
|||
dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
|
||||
rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
|
||||
rk_pcie_debug_dump(priv);
|
||||
msleep(1000);
|
||||
udelay(MACRO_US * 1000);
|
||||
}
|
||||
|
||||
dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
|
||||
/* Link maybe in Gen switch recovery but we need to wait more 1s */
|
||||
msleep(1000);
|
||||
udelay(MACRO_US * 1000);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
@ -298,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
|
|||
}
|
||||
}
|
||||
|
||||
msleep(1000);
|
||||
udelay(MACRO_US * 1000);
|
||||
|
||||
ret = generic_phy_init(&priv->phy);
|
||||
if (ret) {
|
||||
|
|
|
@ -12,4 +12,5 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
|
|||
obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
|
||||
|
|
56
drivers/ram/rockchip/sdram_rk3568.c
Normal file
56
drivers/ram/rockchip/sdram_rk3568.c
Normal file
|
@ -0,0 +1,56 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <ram.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <asm/arch-rockchip/grf_rk3568.h>
|
||||
#include <asm/arch-rockchip/sdram.h>
|
||||
|
||||
struct dram_info {
|
||||
struct ram_info info;
|
||||
struct rk3568_pmugrf *pmugrf;
|
||||
};
|
||||
|
||||
static int rk3568_dmc_probe(struct udevice *dev)
|
||||
{
|
||||
struct dram_info *priv = dev_get_priv(dev);
|
||||
|
||||
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
|
||||
priv->info.base = CONFIG_SYS_SDRAM_BASE;
|
||||
priv->info.size =
|
||||
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3568_dmc_get_info(struct udevice *dev, struct ram_info *info)
|
||||
{
|
||||
struct dram_info *priv = dev_get_priv(dev);
|
||||
|
||||
*info = priv->info;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ram_ops rk3568_dmc_ops = {
|
||||
.get_info = rk3568_dmc_get_info,
|
||||
};
|
||||
|
||||
static const struct udevice_id rk3568_dmc_ids[] = {
|
||||
{ .compatible = "rockchip,rk3568-dmc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(dmc_rk3568) = {
|
||||
.name = "rockchip_rk3568_dmc",
|
||||
.id = UCLASS_RAM,
|
||||
.of_match = rk3568_dmc_ids,
|
||||
.ops = &rk3568_dmc_ops,
|
||||
.probe = rk3568_dmc_probe,
|
||||
.priv_auto = sizeof(struct dram_info),
|
||||
};
|
|
@ -15,4 +15,7 @@
|
|||
|
||||
#define SDRAM_BANK_SIZE (2UL << 30)
|
||||
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
|
||||
#endif
|
||||
|
|
17
include/configs/evb_rk3568.h
Normal file
17
include/configs/evb_rk3568.h
Normal file
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __EVB_RK3568_H
|
||||
#define __EVB_RK3568_H
|
||||
|
||||
#include <configs/rk3568_common.h>
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
|
||||
#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
|
||||
#endif
|
|
@ -51,6 +51,7 @@
|
|||
"script_size_f=0x2000\0" \
|
||||
"pxefile_addr_r=0x00600000\0" \
|
||||
"fdt_addr_r=0x01f00000\0" \
|
||||
"fdtoverlay_addr_r=0x02000000\0" \
|
||||
"kernel_addr_r=0x02080000\0" \
|
||||
"ramdisk_addr_r=0x06000000\0" \
|
||||
"kernel_comp_addr_r=0x08000000\0" \
|
||||
|
|
43
include/configs/rk3568_common.h
Normal file
43
include/configs/rk3568_common.h
Normal file
|
@ -0,0 +1,43 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_RK3568_COMMON_H
|
||||
#define __CONFIG_RK3568_COMMON_H
|
||||
|
||||
#include "rockchip-common.h"
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
#define COUNTER_FREQUENCY 24000000
|
||||
#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020
|
||||
|
||||
#define CONFIG_IRAM_BASE 0xfdcc0000
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00c00800
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0
|
||||
#define SDRAM_MAX_SIZE 0xf0000000
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x00c00000\0" \
|
||||
"pxefile_addr_r=0x00e00000\0" \
|
||||
"fdt_addr_r=0x0a100000\0" \
|
||||
"kernel_addr_r=0x02080000\0" \
|
||||
"ramdisk_addr_r=0x0a200000\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
ENV_MEM_LAYOUT_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
BOOTENV
|
||||
#endif
|
||||
|
||||
#endif
|
925
include/dt-bindings/clock/rk3568-cru.h
Normal file
925
include/dt-bindings/clock/rk3568-cru.h
Normal file
|
@ -0,0 +1,925 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
|
||||
|
||||
/* pmucru-clocks indices */
|
||||
|
||||
/* pmucru plls */
|
||||
#define PLL_PPLL 1
|
||||
#define PLL_HPLL 2
|
||||
|
||||
/* pmucru clocks */
|
||||
#define XIN_OSC0_DIV 4
|
||||
#define CLK_RTC_32K 5
|
||||
#define CLK_PMU 6
|
||||
#define CLK_I2C0 7
|
||||
#define CLK_RTC32K_FRAC 8
|
||||
#define CLK_UART0_DIV 9
|
||||
#define CLK_UART0_FRAC 10
|
||||
#define SCLK_UART0 11
|
||||
#define DBCLK_GPIO0 12
|
||||
#define CLK_PWM0 13
|
||||
#define CLK_CAPTURE_PWM0_NDFT 14
|
||||
#define CLK_PMUPVTM 15
|
||||
#define CLK_CORE_PMUPVTM 16
|
||||
#define CLK_REF24M 17
|
||||
#define XIN_OSC0_USBPHY0_G 18
|
||||
#define CLK_USBPHY0_REF 19
|
||||
#define XIN_OSC0_USBPHY1_G 20
|
||||
#define CLK_USBPHY1_REF 21
|
||||
#define XIN_OSC0_MIPIDSIPHY0_G 22
|
||||
#define CLK_MIPIDSIPHY0_REF 23
|
||||
#define XIN_OSC0_MIPIDSIPHY1_G 24
|
||||
#define CLK_MIPIDSIPHY1_REF 25
|
||||
#define CLK_WIFI_DIV 26
|
||||
#define CLK_WIFI_OSC0 27
|
||||
#define CLK_WIFI 28
|
||||
#define CLK_PCIEPHY0_DIV 29
|
||||
#define CLK_PCIEPHY0_OSC0 30
|
||||
#define CLK_PCIEPHY0_REF 31
|
||||
#define CLK_PCIEPHY1_DIV 32
|
||||
#define CLK_PCIEPHY1_OSC0 33
|
||||
#define CLK_PCIEPHY1_REF 34
|
||||
#define CLK_PCIEPHY2_DIV 35
|
||||
#define CLK_PCIEPHY2_OSC0 36
|
||||
#define CLK_PCIEPHY2_REF 37
|
||||
#define CLK_PCIE30PHY_REF_M 38
|
||||
#define CLK_PCIE30PHY_REF_N 39
|
||||
#define CLK_HDMI_REF 40
|
||||
#define XIN_OSC0_EDPPHY_G 41
|
||||
#define PCLK_PDPMU 42
|
||||
#define PCLK_PMU 43
|
||||
#define PCLK_UART0 44
|
||||
#define PCLK_I2C0 45
|
||||
#define PCLK_GPIO0 46
|
||||
#define PCLK_PMUPVTM 47
|
||||
#define PCLK_PWM0 48
|
||||
#define CLK_PDPMU 49
|
||||
#define SCLK_32K_IOE 50
|
||||
|
||||
#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
/* cru plls */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define PLL_VPLL 5
|
||||
#define PLL_NPLL 6
|
||||
|
||||
/* cru clocks */
|
||||
#define CPLL_333M 9
|
||||
#define ARMCLK 10
|
||||
#define USB480M 11
|
||||
#define ACLK_CORE_NIU2BUS 18
|
||||
#define CLK_CORE_PVTM 19
|
||||
#define CLK_CORE_PVTM_CORE 20
|
||||
#define CLK_CORE_PVTPLL 21
|
||||
#define CLK_GPU_SRC 22
|
||||
#define CLK_GPU_PRE_NDFT 23
|
||||
#define CLK_GPU_PRE_MUX 24
|
||||
#define ACLK_GPU_PRE 25
|
||||
#define PCLK_GPU_PRE 26
|
||||
#define CLK_GPU 27
|
||||
#define CLK_GPU_NP5 28
|
||||
#define PCLK_GPU_PVTM 29
|
||||
#define CLK_GPU_PVTM 30
|
||||
#define CLK_GPU_PVTM_CORE 31
|
||||
#define CLK_GPU_PVTPLL 32
|
||||
#define CLK_NPU_SRC 33
|
||||
#define CLK_NPU_PRE_NDFT 34
|
||||
#define CLK_NPU 35
|
||||
#define CLK_NPU_NP5 36
|
||||
#define HCLK_NPU_PRE 37
|
||||
#define PCLK_NPU_PRE 38
|
||||
#define ACLK_NPU_PRE 39
|
||||
#define ACLK_NPU 40
|
||||
#define HCLK_NPU 41
|
||||
#define PCLK_NPU_PVTM 42
|
||||
#define CLK_NPU_PVTM 43
|
||||
#define CLK_NPU_PVTM_CORE 44
|
||||
#define CLK_NPU_PVTPLL 45
|
||||
#define CLK_DDRPHY1X_SRC 46
|
||||
#define CLK_DDRPHY1X_HWFFC_SRC 47
|
||||
#define CLK_DDR1X 48
|
||||
#define CLK_MSCH 49
|
||||
#define CLK24_DDRMON 50
|
||||
#define ACLK_GIC_AUDIO 51
|
||||
#define HCLK_GIC_AUDIO 52
|
||||
#define HCLK_SDMMC_BUFFER 53
|
||||
#define DCLK_SDMMC_BUFFER 54
|
||||
#define ACLK_GIC600 55
|
||||
#define ACLK_SPINLOCK 56
|
||||
#define HCLK_I2S0_8CH 57
|
||||
#define HCLK_I2S1_8CH 58
|
||||
#define HCLK_I2S2_2CH 59
|
||||
#define HCLK_I2S3_2CH 60
|
||||
#define CLK_I2S0_8CH_TX_SRC 61
|
||||
#define CLK_I2S0_8CH_TX_FRAC 62
|
||||
#define MCLK_I2S0_8CH_TX 63
|
||||
#define I2S0_MCLKOUT_TX 64
|
||||
#define CLK_I2S0_8CH_RX_SRC 65
|
||||
#define CLK_I2S0_8CH_RX_FRAC 66
|
||||
#define MCLK_I2S0_8CH_RX 67
|
||||
#define I2S0_MCLKOUT_RX 68
|
||||
#define CLK_I2S1_8CH_TX_SRC 69
|
||||
#define CLK_I2S1_8CH_TX_FRAC 70
|
||||
#define MCLK_I2S1_8CH_TX 71
|
||||
#define I2S1_MCLKOUT_TX 72
|
||||
#define CLK_I2S1_8CH_RX_SRC 73
|
||||
#define CLK_I2S1_8CH_RX_FRAC 74
|
||||
#define MCLK_I2S1_8CH_RX 75
|
||||
#define I2S1_MCLKOUT_RX 76
|
||||
#define CLK_I2S2_2CH_SRC 77
|
||||
#define CLK_I2S2_2CH_FRAC 78
|
||||
#define MCLK_I2S2_2CH 79
|
||||
#define I2S2_MCLKOUT 80
|
||||
#define CLK_I2S3_2CH_TX_SRC 81
|
||||
#define CLK_I2S3_2CH_TX_FRAC 82
|
||||
#define MCLK_I2S3_2CH_TX 83
|
||||
#define I2S3_MCLKOUT_TX 84
|
||||
#define CLK_I2S3_2CH_RX_SRC 85
|
||||
#define CLK_I2S3_2CH_RX_FRAC 86
|
||||
#define MCLK_I2S3_2CH_RX 87
|
||||
#define I2S3_MCLKOUT_RX 88
|
||||
#define HCLK_PDM 89
|
||||
#define MCLK_PDM 90
|
||||
#define HCLK_VAD 91
|
||||
#define HCLK_SPDIF_8CH 92
|
||||
#define MCLK_SPDIF_8CH_SRC 93
|
||||
#define MCLK_SPDIF_8CH_FRAC 94
|
||||
#define MCLK_SPDIF_8CH 95
|
||||
#define HCLK_AUDPWM 96
|
||||
#define SCLK_AUDPWM_SRC 97
|
||||
#define SCLK_AUDPWM_FRAC 98
|
||||
#define SCLK_AUDPWM 99
|
||||
#define HCLK_ACDCDIG 100
|
||||
#define CLK_ACDCDIG_I2C 101
|
||||
#define CLK_ACDCDIG_DAC 102
|
||||
#define CLK_ACDCDIG_ADC 103
|
||||
#define ACLK_SECURE_FLASH 104
|
||||
#define HCLK_SECURE_FLASH 105
|
||||
#define ACLK_CRYPTO_NS 106
|
||||
#define HCLK_CRYPTO_NS 107
|
||||
#define CLK_CRYPTO_NS_CORE 108
|
||||
#define CLK_CRYPTO_NS_PKA 109
|
||||
#define CLK_CRYPTO_NS_RNG 110
|
||||
#define HCLK_TRNG_NS 111
|
||||
#define CLK_TRNG_NS 112
|
||||
#define PCLK_OTPC_NS 113
|
||||
#define CLK_OTPC_NS_SBPI 114
|
||||
#define CLK_OTPC_NS_USR 115
|
||||
#define HCLK_NANDC 116
|
||||
#define NCLK_NANDC 117
|
||||
#define HCLK_SFC 118
|
||||
#define HCLK_SFC_XIP 119
|
||||
#define SCLK_SFC 120
|
||||
#define ACLK_EMMC 121
|
||||
#define HCLK_EMMC 122
|
||||
#define BCLK_EMMC 123
|
||||
#define CCLK_EMMC 124
|
||||
#define TCLK_EMMC 125
|
||||
#define ACLK_PIPE 126
|
||||
#define PCLK_PIPE 127
|
||||
#define PCLK_PIPE_GRF 128
|
||||
#define ACLK_PCIE20_MST 129
|
||||
#define ACLK_PCIE20_SLV 130
|
||||
#define ACLK_PCIE20_DBI 131
|
||||
#define PCLK_PCIE20 132
|
||||
#define CLK_PCIE20_AUX_NDFT 133
|
||||
#define CLK_PCIE20_AUX_DFT 134
|
||||
#define CLK_PCIE20_PIPE_DFT 135
|
||||
#define ACLK_PCIE30X1_MST 136
|
||||
#define ACLK_PCIE30X1_SLV 137
|
||||
#define ACLK_PCIE30X1_DBI 138
|
||||
#define PCLK_PCIE30X1 139
|
||||
#define CLK_PCIE30X1_AUX_NDFT 140
|
||||
#define CLK_PCIE30X1_AUX_DFT 141
|
||||
#define CLK_PCIE30X1_PIPE_DFT 142
|
||||
#define ACLK_PCIE30X2_MST 143
|
||||
#define ACLK_PCIE30X2_SLV 144
|
||||
#define ACLK_PCIE30X2_DBI 145
|
||||
#define PCLK_PCIE30X2 146
|
||||
#define CLK_PCIE30X2_AUX_NDFT 147
|
||||
#define CLK_PCIE30X2_AUX_DFT 148
|
||||
#define CLK_PCIE30X2_PIPE_DFT 149
|
||||
#define ACLK_SATA0 150
|
||||
#define CLK_SATA0_PMALIVE 151
|
||||
#define CLK_SATA0_RXOOB 152
|
||||
#define CLK_SATA0_PIPE_NDFT 153
|
||||
#define CLK_SATA0_PIPE_DFT 154
|
||||
#define ACLK_SATA1 155
|
||||
#define CLK_SATA1_PMALIVE 156
|
||||
#define CLK_SATA1_RXOOB 157
|
||||
#define CLK_SATA1_PIPE_NDFT 158
|
||||
#define CLK_SATA1_PIPE_DFT 159
|
||||
#define ACLK_SATA2 160
|
||||
#define CLK_SATA2_PMALIVE 161
|
||||
#define CLK_SATA2_RXOOB 162
|
||||
#define CLK_SATA2_PIPE_NDFT 163
|
||||
#define CLK_SATA2_PIPE_DFT 164
|
||||
#define ACLK_USB3OTG0 165
|
||||
#define CLK_USB3OTG0_REF 166
|
||||
#define CLK_USB3OTG0_SUSPEND 167
|
||||
#define ACLK_USB3OTG1 168
|
||||
#define CLK_USB3OTG1_REF 169
|
||||
#define CLK_USB3OTG1_SUSPEND 170
|
||||
#define CLK_XPCS_EEE 171
|
||||
#define PCLK_XPCS 172
|
||||
#define ACLK_PHP 173
|
||||
#define HCLK_PHP 174
|
||||
#define PCLK_PHP 175
|
||||
#define HCLK_SDMMC0 176
|
||||
#define CLK_SDMMC0 177
|
||||
#define HCLK_SDMMC1 178
|
||||
#define CLK_SDMMC1 179
|
||||
#define ACLK_GMAC0 180
|
||||
#define PCLK_GMAC0 181
|
||||
#define CLK_MAC0_2TOP 182
|
||||
#define CLK_MAC0_OUT 183
|
||||
#define CLK_MAC0_REFOUT 184
|
||||
#define CLK_GMAC0_PTP_REF 185
|
||||
#define ACLK_USB 186
|
||||
#define HCLK_USB 187
|
||||
#define PCLK_USB 188
|
||||
#define HCLK_USB2HOST0 189
|
||||
#define HCLK_USB2HOST0_ARB 190
|
||||
#define HCLK_USB2HOST1 191
|
||||
#define HCLK_USB2HOST1_ARB 192
|
||||
#define HCLK_SDMMC2 193
|
||||
#define CLK_SDMMC2 194
|
||||
#define ACLK_GMAC1 195
|
||||
#define PCLK_GMAC1 196
|
||||
#define CLK_MAC1_2TOP 197
|
||||
#define CLK_MAC1_OUT 198
|
||||
#define CLK_MAC1_REFOUT 199
|
||||
#define CLK_GMAC1_PTP_REF 200
|
||||
#define ACLK_PERIMID 201
|
||||
#define HCLK_PERIMID 202
|
||||
#define ACLK_VI 203
|
||||
#define HCLK_VI 204
|
||||
#define PCLK_VI 205
|
||||
#define ACLK_VICAP 206
|
||||
#define HCLK_VICAP 207
|
||||
#define DCLK_VICAP 208
|
||||
#define ICLK_VICAP_G 209
|
||||
#define ACLK_ISP 210
|
||||
#define HCLK_ISP 211
|
||||
#define CLK_ISP 212
|
||||
#define PCLK_CSI2HOST1 213
|
||||
#define CLK_CIF_OUT 214
|
||||
#define CLK_CAM0_OUT 215
|
||||
#define CLK_CAM1_OUT 216
|
||||
#define ACLK_VO 217
|
||||
#define HCLK_VO 218
|
||||
#define PCLK_VO 219
|
||||
#define ACLK_VOP_PRE 220
|
||||
#define ACLK_VOP 221
|
||||
#define HCLK_VOP 222
|
||||
#define DCLK_VOP0 223
|
||||
#define DCLK_VOP1 224
|
||||
#define DCLK_VOP2 225
|
||||
#define CLK_VOP_PWM 226
|
||||
#define ACLK_HDCP 227
|
||||
#define HCLK_HDCP 228
|
||||
#define PCLK_HDCP 229
|
||||
#define PCLK_HDMI_HOST 230
|
||||
#define CLK_HDMI_SFR 231
|
||||
#define PCLK_DSITX_0 232
|
||||
#define PCLK_DSITX_1 233
|
||||
#define PCLK_EDP_CTRL 234
|
||||
#define CLK_EDP_200M 235
|
||||
#define ACLK_VPU_PRE 236
|
||||
#define HCLK_VPU_PRE 237
|
||||
#define ACLK_VPU 238
|
||||
#define HCLK_VPU 239
|
||||
#define ACLK_RGA_PRE 240
|
||||
#define HCLK_RGA_PRE 241
|
||||
#define PCLK_RGA_PRE 242
|
||||
#define ACLK_RGA 243
|
||||
#define HCLK_RGA 244
|
||||
#define CLK_RGA_CORE 245
|
||||
#define ACLK_IEP 246
|
||||
#define HCLK_IEP 247
|
||||
#define CLK_IEP_CORE 248
|
||||
#define HCLK_EBC 249
|
||||
#define DCLK_EBC 250
|
||||
#define ACLK_JDEC 251
|
||||
#define HCLK_JDEC 252
|
||||
#define ACLK_JENC 253
|
||||
#define HCLK_JENC 254
|
||||
#define PCLK_EINK 255
|
||||
#define HCLK_EINK 256
|
||||
#define ACLK_RKVENC_PRE 257
|
||||
#define HCLK_RKVENC_PRE 258
|
||||
#define ACLK_RKVENC 259
|
||||
#define HCLK_RKVENC 260
|
||||
#define CLK_RKVENC_CORE 261
|
||||
#define ACLK_RKVDEC_PRE 262
|
||||
#define HCLK_RKVDEC_PRE 263
|
||||
#define ACLK_RKVDEC 264
|
||||
#define HCLK_RKVDEC 265
|
||||
#define CLK_RKVDEC_CA 266
|
||||
#define CLK_RKVDEC_CORE 267
|
||||
#define CLK_RKVDEC_HEVC_CA 268
|
||||
#define ACLK_BUS 269
|
||||
#define PCLK_BUS 270
|
||||
#define PCLK_TSADC 271
|
||||
#define CLK_TSADC_TSEN 272
|
||||
#define CLK_TSADC 273
|
||||
#define PCLK_SARADC 274
|
||||
#define CLK_SARADC 275
|
||||
#define PCLK_SCR 276
|
||||
#define PCLK_WDT_NS 277
|
||||
#define TCLK_WDT_NS 278
|
||||
#define ACLK_DMAC0 279
|
||||
#define ACLK_DMAC1 280
|
||||
#define ACLK_MCU 281
|
||||
#define PCLK_INTMUX 282
|
||||
#define PCLK_MAILBOX 283
|
||||
#define PCLK_UART1 284
|
||||
#define CLK_UART1_SRC 285
|
||||
#define CLK_UART1_FRAC 286
|
||||
#define SCLK_UART1 287
|
||||
#define PCLK_UART2 288
|
||||
#define CLK_UART2_SRC 289
|
||||
#define CLK_UART2_FRAC 290
|
||||
#define SCLK_UART2 291
|
||||
#define PCLK_UART3 292
|
||||
#define CLK_UART3_SRC 293
|
||||
#define CLK_UART3_FRAC 294
|
||||
#define SCLK_UART3 295
|
||||
#define PCLK_UART4 296
|
||||
#define CLK_UART4_SRC 297
|
||||
#define CLK_UART4_FRAC 298
|
||||
#define SCLK_UART4 299
|
||||
#define PCLK_UART5 300
|
||||
#define CLK_UART5_SRC 301
|
||||
#define CLK_UART5_FRAC 302
|
||||
#define SCLK_UART5 303
|
||||
#define PCLK_UART6 304
|
||||
#define CLK_UART6_SRC 305
|
||||
#define CLK_UART6_FRAC 306
|
||||
#define SCLK_UART6 307
|
||||
#define PCLK_UART7 308
|
||||
#define CLK_UART7_SRC 309
|
||||
#define CLK_UART7_FRAC 310
|
||||
#define SCLK_UART7 311
|
||||
#define PCLK_UART8 312
|
||||
#define CLK_UART8_SRC 313
|
||||
#define CLK_UART8_FRAC 314
|
||||
#define SCLK_UART8 315
|
||||
#define PCLK_UART9 316
|
||||
#define CLK_UART9_SRC 317
|
||||
#define CLK_UART9_FRAC 318
|
||||
#define SCLK_UART9 319
|
||||
#define PCLK_CAN0 320
|
||||
#define CLK_CAN0 321
|
||||
#define PCLK_CAN1 322
|
||||
#define CLK_CAN1 323
|
||||
#define PCLK_CAN2 324
|
||||
#define CLK_CAN2 325
|
||||
#define CLK_I2C 326
|
||||
#define PCLK_I2C1 327
|
||||
#define CLK_I2C1 328
|
||||
#define PCLK_I2C2 329
|
||||
#define CLK_I2C2 330
|
||||
#define PCLK_I2C3 331
|
||||
#define CLK_I2C3 332
|
||||
#define PCLK_I2C4 333
|
||||
#define CLK_I2C4 334
|
||||
#define PCLK_I2C5 335
|
||||
#define CLK_I2C5 336
|
||||
#define PCLK_SPI0 337
|
||||
#define CLK_SPI0 338
|
||||
#define PCLK_SPI1 339
|
||||
#define CLK_SPI1 340
|
||||
#define PCLK_SPI2 341
|
||||
#define CLK_SPI2 342
|
||||
#define PCLK_SPI3 343
|
||||
#define CLK_SPI3 344
|
||||
#define PCLK_PWM1 345
|
||||
#define CLK_PWM1 346
|
||||
#define CLK_PWM1_CAPTURE 347
|
||||
#define PCLK_PWM2 348
|
||||
#define CLK_PWM2 349
|
||||
#define CLK_PWM2_CAPTURE 350
|
||||
#define PCLK_PWM3 351
|
||||
#define CLK_PWM3 352
|
||||
#define CLK_PWM3_CAPTURE 353
|
||||
#define DBCLK_GPIO 354
|
||||
#define PCLK_GPIO1 355
|
||||
#define DBCLK_GPIO1 356
|
||||
#define PCLK_GPIO2 357
|
||||
#define DBCLK_GPIO2 358
|
||||
#define PCLK_GPIO3 359
|
||||
#define DBCLK_GPIO3 360
|
||||
#define PCLK_GPIO4 361
|
||||
#define DBCLK_GPIO4 362
|
||||
#define OCC_SCAN_CLK_GPIO 363
|
||||
#define PCLK_TIMER 364
|
||||
#define CLK_TIMER0 365
|
||||
#define CLK_TIMER1 366
|
||||
#define CLK_TIMER2 367
|
||||
#define CLK_TIMER3 368
|
||||
#define CLK_TIMER4 369
|
||||
#define CLK_TIMER5 370
|
||||
#define ACLK_TOP_HIGH 371
|
||||
#define ACLK_TOP_LOW 372
|
||||
#define HCLK_TOP 373
|
||||
#define PCLK_TOP 374
|
||||
#define PCLK_PCIE30PHY 375
|
||||
#define CLK_OPTC_ARB 376
|
||||
#define PCLK_MIPICSIPHY 377
|
||||
#define PCLK_MIPIDSIPHY0 378
|
||||
#define PCLK_MIPIDSIPHY1 379
|
||||
#define PCLK_PIPEPHY0 380
|
||||
#define PCLK_PIPEPHY1 381
|
||||
#define PCLK_PIPEPHY2 382
|
||||
#define PCLK_CPU_BOOST 383
|
||||
#define CLK_CPU_BOOST 384
|
||||
#define PCLK_OTPPHY 385
|
||||
#define SCLK_GMAC0 386
|
||||
#define SCLK_GMAC0_RGMII_SPEED 387
|
||||
#define SCLK_GMAC0_RMII_SPEED 388
|
||||
#define SCLK_GMAC0_RX_TX 389
|
||||
#define SCLK_GMAC1 390
|
||||
#define SCLK_GMAC1_RGMII_SPEED 391
|
||||
#define SCLK_GMAC1_RMII_SPEED 392
|
||||
#define SCLK_GMAC1_RX_TX 393
|
||||
#define SCLK_SDMMC0_DRV 394
|
||||
#define SCLK_SDMMC0_SAMPLE 395
|
||||
#define SCLK_SDMMC1_DRV 396
|
||||
#define SCLK_SDMMC1_SAMPLE 397
|
||||
#define SCLK_SDMMC2_DRV 398
|
||||
#define SCLK_SDMMC2_SAMPLE 399
|
||||
#define SCLK_EMMC_DRV 400
|
||||
#define SCLK_EMMC_SAMPLE 401
|
||||
#define PCLK_EDPPHY_GRF 402
|
||||
#define CLK_HDMI_CEC 403
|
||||
#define CLK_I2S0_8CH_TX 404
|
||||
#define CLK_I2S0_8CH_RX 405
|
||||
#define CLK_I2S1_8CH_TX 406
|
||||
#define CLK_I2S1_8CH_RX 407
|
||||
#define CLK_I2S2_2CH 408
|
||||
#define CLK_I2S3_2CH_TX 409
|
||||
#define CLK_I2S3_2CH_RX 410
|
||||
#define CPLL_500M 411
|
||||
#define CPLL_250M 412
|
||||
#define CPLL_125M 413
|
||||
#define CPLL_62P5M 414
|
||||
#define CPLL_50M 415
|
||||
#define CPLL_25M 416
|
||||
#define CPLL_100M 417
|
||||
|
||||
#define PCLK_CORE_PVTM 450
|
||||
|
||||
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
|
||||
|
||||
/* pmu soft-reset indices */
|
||||
/* pmucru_softrst_con0 */
|
||||
#define SRST_P_PDPMU_NIU 0
|
||||
#define SRST_P_PMUCRU 1
|
||||
#define SRST_P_PMUGRF 2
|
||||
#define SRST_P_I2C0 3
|
||||
#define SRST_I2C0 4
|
||||
#define SRST_P_UART0 5
|
||||
#define SRST_S_UART0 6
|
||||
#define SRST_P_PWM0 7
|
||||
#define SRST_PWM0 8
|
||||
#define SRST_P_GPIO0 9
|
||||
#define SRST_GPIO0 10
|
||||
#define SRST_P_PMUPVTM 11
|
||||
#define SRST_PMUPVTM 12
|
||||
|
||||
/* soft-reset indices */
|
||||
|
||||
/* cru_softrst_con0 */
|
||||
#define SRST_NCORERESET0 0
|
||||
#define SRST_NCORERESET1 1
|
||||
#define SRST_NCORERESET2 2
|
||||
#define SRST_NCORERESET3 3
|
||||
#define SRST_NCPUPORESET0 4
|
||||
#define SRST_NCPUPORESET1 5
|
||||
#define SRST_NCPUPORESET2 6
|
||||
#define SRST_NCPUPORESET3 7
|
||||
#define SRST_NSRESET 8
|
||||
#define SRST_NSPORESET 9
|
||||
#define SRST_NATRESET 10
|
||||
#define SRST_NGICRESET 11
|
||||
#define SRST_NPRESET 12
|
||||
#define SRST_NPERIPHRESET 13
|
||||
|
||||
/* cru_softrst_con1 */
|
||||
#define SRST_A_CORE_NIU2DDR 16
|
||||
#define SRST_A_CORE_NIU2BUS 17
|
||||
#define SRST_P_DBG_NIU 18
|
||||
#define SRST_P_DBG 19
|
||||
#define SRST_P_DBG_DAPLITE 20
|
||||
#define SRST_DAP 21
|
||||
#define SRST_A_ADB400_CORE2GIC 22
|
||||
#define SRST_A_ADB400_GIC2CORE 23
|
||||
#define SRST_P_CORE_GRF 24
|
||||
#define SRST_P_CORE_PVTM 25
|
||||
#define SRST_CORE_PVTM 26
|
||||
#define SRST_CORE_PVTPLL 27
|
||||
|
||||
/* cru_softrst_con2 */
|
||||
#define SRST_GPU 32
|
||||
#define SRST_A_GPU_NIU 33
|
||||
#define SRST_P_GPU_NIU 34
|
||||
#define SRST_P_GPU_PVTM 35
|
||||
#define SRST_GPU_PVTM 36
|
||||
#define SRST_GPU_PVTPLL 37
|
||||
#define SRST_A_NPU_NIU 40
|
||||
#define SRST_H_NPU_NIU 41
|
||||
#define SRST_P_NPU_NIU 42
|
||||
#define SRST_A_NPU 43
|
||||
#define SRST_H_NPU 44
|
||||
#define SRST_P_NPU_PVTM 45
|
||||
#define SRST_NPU_PVTM 46
|
||||
#define SRST_NPU_PVTPLL 47
|
||||
|
||||
/* cru_softrst_con3 */
|
||||
#define SRST_A_MSCH 51
|
||||
#define SRST_HWFFC_CTRL 52
|
||||
#define SRST_DDR_ALWAYSON 53
|
||||
#define SRST_A_DDRSPLIT 54
|
||||
#define SRST_DDRDFI_CTL 55
|
||||
#define SRST_A_DMA2DDR 57
|
||||
|
||||
/* cru_softrst_con4 */
|
||||
#define SRST_A_PERIMID_NIU 64
|
||||
#define SRST_H_PERIMID_NIU 65
|
||||
#define SRST_A_GIC_AUDIO_NIU 66
|
||||
#define SRST_H_GIC_AUDIO_NIU 67
|
||||
#define SRST_A_GIC600 68
|
||||
#define SRST_A_GIC600_DEBUG 69
|
||||
#define SRST_A_GICADB_CORE2GIC 70
|
||||
#define SRST_A_GICADB_GIC2CORE 71
|
||||
#define SRST_A_SPINLOCK 72
|
||||
#define SRST_H_SDMMC_BUFFER 73
|
||||
#define SRST_D_SDMMC_BUFFER 74
|
||||
#define SRST_H_I2S0_8CH 75
|
||||
#define SRST_H_I2S1_8CH 76
|
||||
#define SRST_H_I2S2_2CH 77
|
||||
#define SRST_H_I2S3_2CH 78
|
||||
|
||||
/* cru_softrst_con5 */
|
||||
#define SRST_M_I2S0_8CH_TX 80
|
||||
#define SRST_M_I2S0_8CH_RX 81
|
||||
#define SRST_M_I2S1_8CH_TX 82
|
||||
#define SRST_M_I2S1_8CH_RX 83
|
||||
#define SRST_M_I2S2_2CH 84
|
||||
#define SRST_M_I2S3_2CH_TX 85
|
||||
#define SRST_M_I2S3_2CH_RX 86
|
||||
#define SRST_H_PDM 87
|
||||
#define SRST_M_PDM 88
|
||||
#define SRST_H_VAD 89
|
||||
#define SRST_H_SPDIF_8CH 90
|
||||
#define SRST_M_SPDIF_8CH 91
|
||||
#define SRST_H_AUDPWM 92
|
||||
#define SRST_S_AUDPWM 93
|
||||
#define SRST_H_ACDCDIG 94
|
||||
#define SRST_ACDCDIG 95
|
||||
|
||||
/* cru_softrst_con6 */
|
||||
#define SRST_A_SECURE_FLASH_NIU 96
|
||||
#define SRST_H_SECURE_FLASH_NIU 97
|
||||
#define SRST_A_CRYPTO_NS 103
|
||||
#define SRST_H_CRYPTO_NS 104
|
||||
#define SRST_CRYPTO_NS_CORE 105
|
||||
#define SRST_CRYPTO_NS_PKA 106
|
||||
#define SRST_CRYPTO_NS_RNG 107
|
||||
#define SRST_H_TRNG_NS 108
|
||||
#define SRST_TRNG_NS 109
|
||||
|
||||
/* cru_softrst_con7 */
|
||||
#define SRST_H_NANDC 112
|
||||
#define SRST_N_NANDC 113
|
||||
#define SRST_H_SFC 114
|
||||
#define SRST_H_SFC_XIP 115
|
||||
#define SRST_S_SFC 116
|
||||
#define SRST_A_EMMC 117
|
||||
#define SRST_H_EMMC 118
|
||||
#define SRST_B_EMMC 119
|
||||
#define SRST_C_EMMC 120
|
||||
#define SRST_T_EMMC 121
|
||||
|
||||
/* cru_softrst_con8 */
|
||||
#define SRST_A_PIPE_NIU 128
|
||||
#define SRST_P_PIPE_NIU 130
|
||||
#define SRST_P_PIPE_GRF 133
|
||||
#define SRST_A_SATA0 134
|
||||
#define SRST_SATA0_PIPE 135
|
||||
#define SRST_SATA0_PMALIVE 136
|
||||
#define SRST_SATA0_RXOOB 137
|
||||
#define SRST_A_SATA1 138
|
||||
#define SRST_SATA1_PIPE 139
|
||||
#define SRST_SATA1_PMALIVE 140
|
||||
#define SRST_SATA1_RXOOB 141
|
||||
|
||||
/* cru_softrst_con9 */
|
||||
#define SRST_A_SATA2 144
|
||||
#define SRST_SATA2_PIPE 145
|
||||
#define SRST_SATA2_PMALIVE 146
|
||||
#define SRST_SATA2_RXOOB 147
|
||||
#define SRST_USB3OTG0 148
|
||||
#define SRST_USB3OTG1 149
|
||||
#define SRST_XPCS 150
|
||||
#define SRST_XPCS_TX_DIV10 151
|
||||
#define SRST_XPCS_RX_DIV10 152
|
||||
#define SRST_XPCS_XGXS_RX 153
|
||||
|
||||
/* cru_softrst_con10 */
|
||||
#define SRST_P_PCIE20 160
|
||||
#define SRST_PCIE20_POWERUP 161
|
||||
#define SRST_MSTR_ARESET_PCIE20 162
|
||||
#define SRST_SLV_ARESET_PCIE20 163
|
||||
#define SRST_DBI_ARESET_PCIE20 164
|
||||
#define SRST_BRESET_PCIE20 165
|
||||
#define SRST_PERST_PCIE20 166
|
||||
#define SRST_CORE_RST_PCIE20 167
|
||||
#define SRST_NSTICKY_RST_PCIE20 168
|
||||
#define SRST_STICKY_RST_PCIE20 169
|
||||
#define SRST_PWR_RST_PCIE20 170
|
||||
|
||||
/* cru_softrst_con11 */
|
||||
#define SRST_P_PCIE30X1 176
|
||||
#define SRST_PCIE30X1_POWERUP 177
|
||||
#define SRST_M_ARESET_PCIE30X1 178
|
||||
#define SRST_S_ARESET_PCIE30X1 179
|
||||
#define SRST_D_ARESET_PCIE30X1 180
|
||||
#define SRST_BRESET_PCIE30X1 181
|
||||
#define SRST_PERST_PCIE30X1 182
|
||||
#define SRST_CORE_RST_PCIE30X1 183
|
||||
#define SRST_NSTC_RST_PCIE30X1 184
|
||||
#define SRST_STC_RST_PCIE30X1 185
|
||||
#define SRST_PWR_RST_PCIE30X1 186
|
||||
|
||||
/* cru_softrst_con12 */
|
||||
#define SRST_P_PCIE30X2 192
|
||||
#define SRST_PCIE30X2_POWERUP 193
|
||||
#define SRST_M_ARESET_PCIE30X2 194
|
||||
#define SRST_S_ARESET_PCIE30X2 195
|
||||
#define SRST_D_ARESET_PCIE30X2 196
|
||||
#define SRST_BRESET_PCIE30X2 197
|
||||
#define SRST_PERST_PCIE30X2 198
|
||||
#define SRST_CORE_RST_PCIE30X2 199
|
||||
#define SRST_NSTC_RST_PCIE30X2 200
|
||||
#define SRST_STC_RST_PCIE30X2 201
|
||||
#define SRST_PWR_RST_PCIE30X2 202
|
||||
|
||||
/* cru_softrst_con13 */
|
||||
#define SRST_A_PHP_NIU 208
|
||||
#define SRST_H_PHP_NIU 209
|
||||
#define SRST_P_PHP_NIU 210
|
||||
#define SRST_H_SDMMC0 211
|
||||
#define SRST_SDMMC0 212
|
||||
#define SRST_H_SDMMC1 213
|
||||
#define SRST_SDMMC1 214
|
||||
#define SRST_A_GMAC0 215
|
||||
#define SRST_GMAC0_TIMESTAMP 216
|
||||
|
||||
/* cru_softrst_con14 */
|
||||
#define SRST_A_USB_NIU 224
|
||||
#define SRST_H_USB_NIU 225
|
||||
#define SRST_P_USB_NIU 226
|
||||
#define SRST_P_USB_GRF 227
|
||||
#define SRST_H_USB2HOST0 228
|
||||
#define SRST_H_USB2HOST0_ARB 229
|
||||
#define SRST_USB2HOST0_UTMI 230
|
||||
#define SRST_H_USB2HOST1 231
|
||||
#define SRST_H_USB2HOST1_ARB 232
|
||||
#define SRST_USB2HOST1_UTMI 233
|
||||
#define SRST_H_SDMMC2 234
|
||||
#define SRST_SDMMC2 235
|
||||
#define SRST_A_GMAC1 236
|
||||
#define SRST_GMAC1_TIMESTAMP 237
|
||||
|
||||
/* cru_softrst_con15 */
|
||||
#define SRST_A_VI_NIU 240
|
||||
#define SRST_H_VI_NIU 241
|
||||
#define SRST_P_VI_NIU 242
|
||||
#define SRST_A_VICAP 247
|
||||
#define SRST_H_VICAP 248
|
||||
#define SRST_D_VICAP 249
|
||||
#define SRST_I_VICAP 250
|
||||
#define SRST_P_VICAP 251
|
||||
#define SRST_H_ISP 252
|
||||
#define SRST_ISP 253
|
||||
#define SRST_P_CSI2HOST1 255
|
||||
|
||||
/* cru_softrst_con16 */
|
||||
#define SRST_A_VO_NIU 256
|
||||
#define SRST_H_VO_NIU 257
|
||||
#define SRST_P_VO_NIU 258
|
||||
#define SRST_A_VOP_NIU 259
|
||||
#define SRST_A_VOP 260
|
||||
#define SRST_H_VOP 261
|
||||
#define SRST_VOP0 262
|
||||
#define SRST_VOP1 263
|
||||
#define SRST_VOP2 264
|
||||
#define SRST_VOP_PWM 265
|
||||
#define SRST_A_HDCP 266
|
||||
#define SRST_H_HDCP 267
|
||||
#define SRST_P_HDCP 268
|
||||
#define SRST_P_HDMI_HOST 270
|
||||
#define SRST_HDMI_HOST 271
|
||||
|
||||
/* cru_softrst_con17 */
|
||||
#define SRST_P_DSITX_0 272
|
||||
#define SRST_P_DSITX_1 273
|
||||
#define SRST_P_EDP_CTRL 274
|
||||
#define SRST_EDP_24M 275
|
||||
#define SRST_A_VPU_NIU 280
|
||||
#define SRST_H_VPU_NIU 281
|
||||
#define SRST_A_VPU 282
|
||||
#define SRST_H_VPU 283
|
||||
#define SRST_H_EINK 286
|
||||
#define SRST_P_EINK 287
|
||||
|
||||
/* cru_softrst_con18 */
|
||||
#define SRST_A_RGA_NIU 288
|
||||
#define SRST_H_RGA_NIU 289
|
||||
#define SRST_P_RGA_NIU 290
|
||||
#define SRST_A_RGA 292
|
||||
#define SRST_H_RGA 293
|
||||
#define SRST_RGA_CORE 294
|
||||
#define SRST_A_IEP 295
|
||||
#define SRST_H_IEP 296
|
||||
#define SRST_IEP_CORE 297
|
||||
#define SRST_H_EBC 298
|
||||
#define SRST_D_EBC 299
|
||||
#define SRST_A_JDEC 300
|
||||
#define SRST_H_JDEC 301
|
||||
#define SRST_A_JENC 302
|
||||
#define SRST_H_JENC 303
|
||||
|
||||
/* cru_softrst_con19 */
|
||||
#define SRST_A_VENC_NIU 304
|
||||
#define SRST_H_VENC_NIU 305
|
||||
#define SRST_A_RKVENC 307
|
||||
#define SRST_H_RKVENC 308
|
||||
#define SRST_RKVENC_CORE 309
|
||||
|
||||
/* cru_softrst_con20 */
|
||||
#define SRST_A_RKVDEC_NIU 320
|
||||
#define SRST_H_RKVDEC_NIU 321
|
||||
#define SRST_A_RKVDEC 322
|
||||
#define SRST_H_RKVDEC 323
|
||||
#define SRST_RKVDEC_CA 324
|
||||
#define SRST_RKVDEC_CORE 325
|
||||
#define SRST_RKVDEC_HEVC_CA 326
|
||||
|
||||
/* cru_softrst_con21 */
|
||||
#define SRST_A_BUS_NIU 336
|
||||
#define SRST_P_BUS_NIU 338
|
||||
#define SRST_P_CAN0 340
|
||||
#define SRST_CAN0 341
|
||||
#define SRST_P_CAN1 342
|
||||
#define SRST_CAN1 343
|
||||
#define SRST_P_CAN2 344
|
||||
#define SRST_CAN2 345
|
||||
#define SRST_P_GPIO1 346
|
||||
#define SRST_GPIO1 347
|
||||
#define SRST_P_GPIO2 348
|
||||
#define SRST_GPIO2 349
|
||||
#define SRST_P_GPIO3 350
|
||||
#define SRST_GPIO3 351
|
||||
|
||||
/* cru_softrst_con22 */
|
||||
#define SRST_P_GPIO4 352
|
||||
#define SRST_GPIO4 353
|
||||
#define SRST_P_I2C1 354
|
||||
#define SRST_I2C1 355
|
||||
#define SRST_P_I2C2 356
|
||||
#define SRST_I2C2 357
|
||||
#define SRST_P_I2C3 358
|
||||
#define SRST_I2C3 359
|
||||
#define SRST_P_I2C4 360
|
||||
#define SRST_I2C4 361
|
||||
#define SRST_P_I2C5 362
|
||||
#define SRST_I2C5 363
|
||||
#define SRST_P_OTPC_NS 364
|
||||
#define SRST_OTPC_NS_SBPI 365
|
||||
#define SRST_OTPC_NS_USR 366
|
||||
|
||||
/* cru_softrst_con23 */
|
||||
#define SRST_P_PWM1 368
|
||||
#define SRST_PWM1 369
|
||||
#define SRST_P_PWM2 370
|
||||
#define SRST_PWM2 371
|
||||
#define SRST_P_PWM3 372
|
||||
#define SRST_PWM3 373
|
||||
#define SRST_P_SPI0 374
|
||||
#define SRST_SPI0 375
|
||||
#define SRST_P_SPI1 376
|
||||
#define SRST_SPI1 377
|
||||
#define SRST_P_SPI2 378
|
||||
#define SRST_SPI2 379
|
||||
#define SRST_P_SPI3 380
|
||||
#define SRST_SPI3 381
|
||||
|
||||
/* cru_softrst_con24 */
|
||||
#define SRST_P_SARADC 384
|
||||
#define SRST_P_TSADC 385
|
||||
#define SRST_TSADC 386
|
||||
#define SRST_P_TIMER 387
|
||||
#define SRST_TIMER0 388
|
||||
#define SRST_TIMER1 389
|
||||
#define SRST_TIMER2 390
|
||||
#define SRST_TIMER3 391
|
||||
#define SRST_TIMER4 392
|
||||
#define SRST_TIMER5 393
|
||||
#define SRST_P_UART1 394
|
||||
#define SRST_S_UART1 395
|
||||
|
||||
/* cru_softrst_con25 */
|
||||
#define SRST_P_UART2 400
|
||||
#define SRST_S_UART2 401
|
||||
#define SRST_P_UART3 402
|
||||
#define SRST_S_UART3 403
|
||||
#define SRST_P_UART4 404
|
||||
#define SRST_S_UART4 405
|
||||
#define SRST_P_UART5 406
|
||||
#define SRST_S_UART5 407
|
||||
#define SRST_P_UART6 408
|
||||
#define SRST_S_UART6 409
|
||||
#define SRST_P_UART7 410
|
||||
#define SRST_S_UART7 411
|
||||
#define SRST_P_UART8 412
|
||||
#define SRST_S_UART8 413
|
||||
#define SRST_P_UART9 414
|
||||
#define SRST_S_UART9 415
|
||||
|
||||
/* cru_softrst_con26 */
|
||||
#define SRST_P_GRF 416
|
||||
#define SRST_P_GRF_VCCIO12 417
|
||||
#define SRST_P_GRF_VCCIO34 418
|
||||
#define SRST_P_GRF_VCCIO567 419
|
||||
#define SRST_P_SCR 420
|
||||
#define SRST_P_WDT_NS 421
|
||||
#define SRST_T_WDT_NS 422
|
||||
#define SRST_P_DFT2APB 423
|
||||
#define SRST_A_MCU 426
|
||||
#define SRST_P_INTMUX 427
|
||||
#define SRST_P_MAILBOX 428
|
||||
|
||||
/* cru_softrst_con27 */
|
||||
#define SRST_A_TOP_HIGH_NIU 432
|
||||
#define SRST_A_TOP_LOW_NIU 433
|
||||
#define SRST_H_TOP_NIU 434
|
||||
#define SRST_P_TOP_NIU 435
|
||||
#define SRST_P_TOP_CRU 438
|
||||
#define SRST_P_DDRPHY 439
|
||||
#define SRST_DDRPHY 440
|
||||
#define SRST_P_MIPICSIPHY 442
|
||||
#define SRST_P_MIPIDSIPHY0 443
|
||||
#define SRST_P_MIPIDSIPHY1 444
|
||||
#define SRST_P_PCIE30PHY 445
|
||||
#define SRST_PCIE30PHY 446
|
||||
#define SRST_P_PCIE30PHY_GRF 447
|
||||
|
||||
/* cru_softrst_con28 */
|
||||
#define SRST_P_APB2ASB_LEFT 448
|
||||
#define SRST_P_APB2ASB_BOTTOM 449
|
||||
#define SRST_P_ASB2APB_LEFT 450
|
||||
#define SRST_P_ASB2APB_BOTTOM 451
|
||||
#define SRST_P_PIPEPHY0 452
|
||||
#define SRST_PIPEPHY0 453
|
||||
#define SRST_P_PIPEPHY1 454
|
||||
#define SRST_PIPEPHY1 455
|
||||
#define SRST_P_PIPEPHY2 456
|
||||
#define SRST_PIPEPHY2 457
|
||||
#define SRST_P_USB2PHY0_GRF 458
|
||||
#define SRST_P_USB2PHY1_GRF 459
|
||||
#define SRST_P_CPU_BOOST 460
|
||||
#define SRST_CPU_BOOST 461
|
||||
#define SRST_P_OTPPHY 462
|
||||
#define SRST_OTPPHY 463
|
||||
|
||||
/* cru_softrst_con29 */
|
||||
#define SRST_USB2PHY0_POR 464
|
||||
#define SRST_USB2PHY0_USB3OTG0 465
|
||||
#define SRST_USB2PHY0_USB3OTG1 466
|
||||
#define SRST_USB2PHY1_POR 467
|
||||
#define SRST_USB2PHY1_USB2HOST0 468
|
||||
#define SRST_USB2PHY1_USB2HOST1 469
|
||||
#define SRST_P_EDPPHY_GRF 470
|
||||
#define SRST_TSADCPHY 471
|
||||
#define SRST_GMAC0_DELAYLINE 472
|
||||
#define SRST_GMAC1_DELAYLINE 473
|
||||
#define SRST_OTPC_ARB 474
|
||||
#define SRST_P_PIPEPHY0_GRF 475
|
||||
#define SRST_P_PIPEPHY1_GRF 476
|
||||
#define SRST_P_PIPEPHY2_GRF 477
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue