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armv8: Update erratum number to align with doc
Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.
Fixes 0cfa00cdb9
(“armv8: Add workaround for USB erratum A-050106”)
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
parent
13ea307f79
commit
390c73b417
2 changed files with 7 additions and 7 deletions
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@ -223,7 +223,7 @@ config ARCH_LX2162A
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_ERRATUM_A050106
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select SYS_FSL_ERRATUM_A050204
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select SYS_FSL_ERRATUM_A011334
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select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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select SYS_FSL_HAS_RGMII
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@ -255,7 +255,7 @@ config ARCH_LX2160A
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_EC1
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select SYS_FSL_EC2
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select SYS_FSL_ERRATUM_A050106
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select SYS_FSL_ERRATUM_A050204
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select SYS_FSL_ERRATUM_A011334
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select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
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select SYS_FSL_HAS_RGMII
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@ -375,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008
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config SYS_FSL_ERRATUM_A009798
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bool "Workaround for USB PHY erratum A009798"
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config SYS_FSL_ERRATUM_A050106
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bool "Workaround for USB PHY erratum A050106"
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config SYS_FSL_ERRATUM_A050204
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bool "Workaround for USB PHY erratum A050204"
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help
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USB3.0 Receiver needs to enable fixed equalization
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for each of PHY instances in an SOC. This is similar
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014-2015 Freescale Semiconductor
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* Copyright 2019-2020 NXP
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* Copyright 2019-2021 NXP
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*/
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#include <common.h>
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@ -218,7 +218,7 @@ static void erratum_a009007(void)
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}
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#if defined(CONFIG_FSL_LSCH3)
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static void erratum_a050106(void)
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static void erratum_a050204(void)
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{
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#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
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void __iomem *dcsr = (void __iomem *)DCSR_BASE;
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@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void)
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erratum_a009798();
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erratum_a008997();
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erratum_a009007();
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erratum_a050106();
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erratum_a050204();
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#ifdef CONFIG_CHAIN_OF_TRUST
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/* In case of Secure Boot, the IBR configures the SMMU
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* to allow only Secure transactions.
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